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    • 12. 发明授权
    • Priority aware selective cache allocation
    • 优先级识别选择性缓存分配
    • US07802057B2
    • 2010-09-21
    • US11965131
    • 2007-12-27
    • Ravishankar IyerRamesh MilekalDonald NewellLi Zhao
    • Ravishankar IyerRamesh MilekalDonald NewellLi Zhao
    • G06F12/06G06F9/50
    • G06F12/126G06F9/5016G06F12/0888
    • A method and apparatus for is herein described providing priority aware and consumption guided dynamic probabilistic allocation for a cache memory. Utilization of a sample size of a cache memory is measured for each priority level of a computer system. Allocation probabilities for each priority level are updated based on the measured consumption/utilization, i.e. allocation is reduced for priority levels consuming too much of the cache and allocation is increased for priority levels consuming too little of the cache. In response to an allocation request, it is assigned a priority level. An allocation probability associated with the priority level is compared with a randomly generated number. If the number is less than the allocation probability, then a fill to the cache is performed normally. In contrast, a spatially or temporally limited fill is performed if the random number is greater than the allocation probability.
    • 本文描述了提供高速缓冲存储器的优先级感知和消耗引导的动态概率分配的方法和装置。 针对计算机系统的每个优先级测量利用高速缓冲存储器的样本大小。 基于所测量的消耗/利用率来更新每个优先级的分配概率,即对于消耗太多高速缓存的优先级降低了分配,并且对于消耗太多缓存的优先级来说,分配增加。 响应于分配请求,它被分配优先级。 将与优先级相关联的分配概率与随机生成的数字进行比较。 如果该数量小于分配概率,则正常地执行对高速缓存的填充。 相比之下,如果随机数大于分配概率,则执行空间或时间有限的填充。
    • 15. 发明申请
    • PRIORITY AWARE SELECTIVE CACHE ALLOCATION
    • 优先注意选择性高速缓存分配
    • US20090172315A1
    • 2009-07-02
    • US11965131
    • 2007-12-27
    • Ravishankar IyerRamesh MilekalDonald NewellLi Zhao
    • Ravishankar IyerRamesh MilekalDonald NewellLi Zhao
    • G06F12/00
    • G06F12/126G06F9/5016G06F12/0888
    • A method and apparatus for is herein described providing priority aware and consumption guided dynamic probabilistic allocation for a cache memory. Utilization of a sample size of a cache memory is measured for each priority level of a computer system. Allocation probabilities for each priority level are updated based on the measured consumption/utilization, i.e. allocation is reduced for priority levels consuming too much of the cache and allocation is increased for priority levels consuming too little of the cache. In response to an allocation request, it is assigned a priority level. An allocation probability associated with the priority level is compared with a randomly generated number. If the number is less than the allocation probability, then a fill to the cache is performed normally. In contrast, a spatially or temporally limited fill is performed if the random number is greater than the allocation probability.
    • 本文描述了提供高速缓冲存储器的优先级感知和消耗引导的动态概率分配的方法和装置。 针对计算机系统的每个优先级测量利用高速缓冲存储器的样本大小。 基于所测量的消耗/利用率来更新每个优先级的分配概率,即对于消耗太多高速缓存的优先级降低了分配,并且对于消耗太多缓存的优先级来说,分配增加。 响应于分配请求,它被分配优先级。 将与优先级相关联的分配概率与随机生成的数字进行比较。 如果该数量小于分配概率,则正常地执行对高速缓存的填充。 相比之下,如果随机数大于分配概率,则执行空间或时间有限的填充。
    • 20. 发明申请
    • Liquid crystal display and driving method thereof
    • 液晶显示及其驱动方法
    • US20080192039A1
    • 2008-08-14
    • US12012868
    • 2008-02-06
    • Zhen-li ZhaoMing-Bo Tai
    • Zhen-li ZhaoMing-Bo Tai
    • G06F3/038
    • G09G3/3648G09G2320/0285G09G2320/0626
    • An exemplary liquid crystal display (2) includes a liquid crystal panel (20) and a data driving circuit (212). The liquid crystal panel includes a first substrate (22), a second substrate (23) parallel to the first substrate, a liquid crystal layer (24) interposed between the first and second substrates, and a common electrode layer (221) provided on first substrate. The second substrate includes a plurality of data lines (242). The data driving circuit includes a main circuit (213). The main circuit is connected with the common electrode layer and the data lines. The main circuit is configured to receive a brightness signal and a display signal, output a common voltage corresponding to the brightness signal to the common electrode layer, and output a gradation voltage corresponding to the brightness signal and the display signal to the data lines.
    • 示例性液晶显示器(2)包括液晶面板(20)和数据驱动电路(212)。 液晶面板包括第一基板(22),平行于第一基板的第二基板(23),介于第一和第二基板之间的液晶层(24),以及设置在第一基板 基质。 第二基板包括多条数据线(242)。 数据驱动电路包括主电路(213)。 主电路与公共电极层和数据线连接。 主电路被配置为接收亮度信号和显示信号,将与亮度信号相对应的公共电压输出到公共电极层,并将对应于亮度信号和显示信号的灰度电压输出到数据线。