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41. 发明申请

US20100050272A1 METHOD AND APPARATUS FOR HIERARCHICAL ASSIGNMENT OF RIGHTS TO DOCUMENTS AND DOCUMENTS HAVING SUCH RIGHTS 审中-公开
标题翻译：对这些权利的文件和文件进行分层分配的方法和装置
公开(公告)号：US20100050272A1
公开(公告)日：2010-02-25
申请号：US12609725
申请日：2009-10-30
申请人： Bijan Tadayon , Aram Nahidipour , Xin Wang , Michael C. Raley , Guillermo Lao , Thanh T. Ta
发明人： Bijan Tadayon , Aram Nahidipour , Xin Wang , Michael C. Raley , Guillermo Lao , Thanh T. Ta
IPC分类号： H04L29/06 , G06F17/00
CPC分类号： G06F21/10 , G06F21/62 , G06F2221/0746 , G06F2221/0768 , G06Q10/10
摘要： A system and method for distribution of digital works in a tree-like structure of devices. A hierarchical right may include a first usage right governing a use for the digital work and a first delegation right governing distribution of the digital work to child nodes of the tree-like structure. A second usage right and/or a second delegation right may be generated based on the hierarchical right, the second usage right governing a use for the digital work and the second delegation right governing distribution of the digital work to child nodes of a first child node of the tree-like structure. The second usage right and/or the second delegation right may be assigned to a version of the digital work, and the second usage right and/or the second delegation right and the version of the digital work may be forwarded to the first child node.
摘要翻译：数字作品在树状结构中分配的系统和方法。分级权限可以包括管理数字作品的使用的第一使用权以及将数字作品分配给树状结构的子节点的第一授权权限。第二使用权和/或第二授权权利可以基于分级权利，管理数字作品使用的第二使用权以及第二授权权利来控制数字作品对第一子节点的子节点的分配的树状结构。可以将第二使用权和/或第二授权权限分配给数字作品的版本，并且可以将第二使用权和/或第二授权权和数字作品的版本转发到第一子节点。

42. 发明申请

US20090227084A1 Novel Method to Enhance Channel Stress in CMOS Processes 有权
标题翻译：在CMOS工艺中增强沟道应力的新方法
公开(公告)号：US20090227084A1
公开(公告)日：2009-09-10
申请号：US12357712
申请日：2009-01-22
申请人： Zhiqiang Wu , Xin Wang
发明人： Zhiqiang Wu , Xin Wang
IPC分类号： H01L21/336
CPC分类号： H01L29/7833 , H01L21/26506 , H01L29/165 , H01L29/6656 , H01L29/6659 , H01L29/7845 , H01L29/7847 , H01L29/7848
摘要： The invention provides a method of fabricating a semiconductor device that enhances the amount of stress that is transmitted to the channel region for carrier mobility enhancement. In one embodiment an amorphous region is formed at or near the gate dielectric interface prior to source/drain anneal. In a second embodiment the gate material is amorphous as deposited and processing temperatures are kept below the gate material crystallization temperature until stress enhancement processing has been completed. The amorphous gate material deforms during high temperature anneal and converts from an amorphous to a polycrystalline phase allowing more stress to be transmitted into the channel region. This enhances carrier mobility and improves transistor drive current.
摘要翻译：本发明提供了一种制造半导体器件的方法，该半导体器件增强了传输到沟道区的载流子迁移率增强的应力量。在一个实施例中，在源极/漏极退火之前，在栅极电介质界面处或附近形成非晶区域。在第二实施例中，栅极材料是非晶态的，并且处理温度保持低于栅极材料结晶温度，直到应力增强处理完成。非晶栅极材料在高温退火期间变形，并从非晶态转变为多晶相，允许更多的应力传输到沟道区。这增强了载流子迁移率并改善了晶体管驱动电流。

43. 发明申请

US20090181506A1 Novel Method to Form Memory Cells to Improve Programming Performance of Embedded Memory Technology 审中-公开
标题翻译：用于形成记忆单元以提高嵌入式存储器技术编程性能的新方法
公开(公告)号：US20090181506A1
公开(公告)日：2009-07-16
申请号：US12407624
申请日：2009-03-19
申请人： Jihong Chen , Eddie Hearl Breashears , Xin Wang , John Howard Macpeak
发明人： Jihong Chen , Eddie Hearl Breashears , Xin Wang , John Howard Macpeak
IPC分类号： H01L21/8239 , H01L21/426
CPC分类号： H01L29/7881 , H01L21/26586 , H01L27/115 , H01L27/11521 , H01L29/40114
摘要： An embedded memory device and method of forming MOS transistors having reduced masking requirements and defects using a single drain sided halo implant in the NMOS FLASH or EEPROM memory regions is discussed. The memory device comprises a memory region and a logic region. Logic transistors within the logic region have halos implanted at an angle underlying the channel from both drain and source region sides. Asymmetric memory cell transistors within the memory region receive a selective halo implant only from the drain side of the channel and not from the source side to form a larger halo on the drain side and leave a higher dopant concentration more deeply into the source side. One method of asymmetrically forming memory cell transistors comprises masking over the memory region; halo implanting a first conductivity dopant in NMOS regions of the logic region in first and second implant directions; masking over the logic region; halo implanting the first conductivity dopant in NMOS regions of the memory region in the second implant direction only, thereby reducing the number of masks required; masking over the memory region; halo implanting a second conductivity dopant in PMOS regions of the logic region in the first and second implant directions.
摘要翻译：讨论了在NMOS闪存或EEPROM存储器区域中使用单个漏极侧卤素注入形成具有减小的掩模要求和缺陷的MOS晶体管的嵌入式存储器件和方法。存储器件包括存储器区域和逻辑区域。逻辑区域内的逻辑晶体管具有从沟道和源极区两侧的通道下方的角度注入的光晕。存储器区域内的不对称存储单元晶体管仅从沟道的漏极侧接收选择性晕圈注入而不从源极接收，以在漏极侧形成较大的卤素，并且在源极侧更高的掺杂浓度。一种不对称形成存储单元晶体管的方法包括：对存储区进行掩蔽; 在第一和第二植入方向上在所述逻辑区域的NMOS区域中注入第一电导率掺杂剂; 屏蔽逻辑区域; 在第二注入方向仅在存储区域的NMOS区域中注入第一电导率掺杂剂，从而减少所需的掩模数量; 掩蔽内存区域; 在所述第一和第二植入方向上在所述逻辑区域的PMOS区域中注入第二电导率掺杂剂。

44. 发明授权

US07521274B2 Pulsed growth of catalyst-free growth of GaN nanowires and application in group III nitride semiconductor bulk material 有权
标题翻译： GaN纳米线无催化剂生长的脉冲生长和在III族氮化物半导体散装材料中的应用
公开(公告)号：US07521274B2
公开(公告)日：2009-04-21
申请号：US11684264
申请日：2007-03-09
申请人： Stephen D. Hersee , Xin Wang , Xinyu Sun
发明人： Stephen D. Hersee , Xin Wang , Xinyu Sun
IPC分类号： H01L21/00
CPC分类号： H01L29/413 , B82Y10/00 , B82Y20/00 , B82Y30/00 , C30B29/60 , H01L21/0237 , H01L21/02458 , H01L21/0254 , H01L21/02573 , H01L21/02603 , H01L21/02609 , H01L21/02612 , H01L21/0262 , H01L21/02636 , H01L21/02639 , H01L21/02642 , H01L29/045 , H01L29/0676 , H01L29/2003 , H01L29/775 , H01L31/0304 , H01L31/035236 , H01L31/184 , H01L33/18 , H01L33/24 , H01L2221/1094 , H01L2924/0002 , H01S5/1042 , H01S5/1835 , H01S5/18369 , H01S5/3428 , Y02E10/544 , Y02P70/521 , Y10S977/762 , Y10S977/816 , Y10T428/24612 , H01L2924/00
摘要： Exemplary embodiments provide semiconductor devices including high-quality (i.e., defect free) group III-N nanowires and uniform group III-N nanowire arrays as well as their scalable processes for manufacturing, where the position, orientation, cross-sectional features, length and the crystallinity of each nanowire can be precisely controlled. A pulsed growth mode can be used to fabricate the disclosed group III-N nanowires and/or nanowire arrays providing a uniform length of about 10 nm to about 1000 microns with constant cross-sectional features including an exemplary diameter of about 10-1000 nm. In addition, high-quality GaN substrate structures can be formed by coalescing the plurality of GaN nanowires and/or nanowire arrays to facilitate the fabrication of visible LEDs and lasers. Furthermore, core-shell nanowire/MQW active structures can be formed by a core-shell growth on the nonpolar sidewalls of each nanowire.
摘要翻译：示例性实施例提供包括高质量（即，无缺陷）III-N族纳米线和均匀III-N纳米线阵列的半导体器件及其可制造的可扩展工艺，其中位置，取向，横截面特征，长度和可以精确地控制每个纳米线的结晶度。可以使用脉冲生长模式来制造公开的提供约10nm至约1000微米的均匀长度的III-N族纳米线和/或纳米线阵列，其具有恒定的横截面特征，包括约10-1000nm的示例性直径。此外，可以通过聚结多个GaN纳米线和/或纳米线阵列来形成高质量的GaN衬底结构，以便制造可见的LED和激光器。此外，核 - 壳纳米线/ MQW活性结构可以通过在每个纳米线的非极性侧壁上的核 - 壳生长形成。

45. 发明申请

US20090085105A1 TRENCH MOSFET AND METHOD OF MANUFACTURE UTILIZING TWO MASKS 失效
标题翻译： TRENCH MOSFET和使用两个掩模的制造方法
公开(公告)号：US20090085105A1
公开(公告)日：2009-04-02
申请号：US11866365
申请日：2007-10-02
申请人： Shih Tzung Su , Jun Zeng , Poi Sun , Kao Way Tu , Tai Chiang Chen , Long Lv , Xin Wang
发明人： Shih Tzung Su , Jun Zeng , Poi Sun , Kao Way Tu , Tai Chiang Chen , Long Lv , Xin Wang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/0661 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42372 , H01L29/4238 , H01L29/456 , H01L29/4925 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A method for manufacturing a trench MOSFET semiconductor device comprises: providing a heavily doped N+ silicon substrate; forming an N type epitaxial layer; forming a thick SiO2 layer; creating P body and source area formations by ion implantation without any masks; utilizing a first mask to define openings for a trench gate and a termination; thermally growing a gate oxide layer followed by formation of a thick poly-Silicon refill layer without a mask to define a gate bus area; forming sidewall spacers; forming P+ areas; removing the sidewall spacers; depositing tungsten to fill contacts and vias; depositing a first thin barrier metal layer; depositing a first thick metal layer; utilizing a second metal mask to open a gate bus area; forming second sidewall spacers; depositing a second thin barrier metal layer; depositing a second thick metal layer; and planarizing at least the second thick metal layer and the second thin metal layer to isolate the source metal portions from gate metal portions, whereby the trench MOSFET semiconductor device is manufactured utilizing only first and second masks.
摘要翻译：一种用于制造沟槽MOSFET半导体器件的方法包括：提供重掺杂的N +硅衬底; 形成N型外延层; 形成厚的SiO 2层; 通过离子注入创建P体和源区形成，而不需要任何掩模; 利用第一掩模来限定沟槽栅极和终端的开口; 热生长栅极氧化层，随后形成厚度不含掩模的多晶硅替代层，以限定栅极总线面积; 形成侧壁间隔物; 形成P +区域; 去除侧壁间隔物; 沉积钨以填充触点和通孔; 沉积第一薄的阻挡金属层; 沉积第一厚金属层; 利用第二金属掩模打开闸总线区域; 形成第二侧壁间隔物; 沉积第二薄的阻挡金属层; 沉积第二厚金属层; 并且至少平面化第二厚金属层和第二薄金属层以将源极金属部分与栅极金属部分隔离，由此仅利用第一和第二掩模制造沟槽MOSFET半导体器件。

46. 外观设计

USD579618S1 Automated trash can 有权
公开(公告)号：USD579618S1
公开(公告)日：2008-10-28
申请号：US29293445
申请日：2007-11-23
申请人： Xin Wang , Jiangqun Chen
设计人： Xin Wang , Jiangqun Chen

47. 发明授权

US07444605B2 Generating a base curve database to reduce storage cost 失效
标题翻译：生成基线曲线数据库以降低存储成本
公开(公告)号：US07444605B2
公开(公告)日：2008-10-28
申请号：US11245550
申请日：2005-10-06
申请人： Xin Wang , Harold J. Levy , Michael N. Misheloff
发明人： Xin Wang , Harold J. Levy , Michael N. Misheloff
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： An enhanced library accessible by an EDA tool can include a base curve database and a plurality of curve data sets. Each curve data set refers to a standard cell having certain timing characteristics. To determine those timing characteristics, each curve data set identifies at least one base curve (in the base curve database) as well as a starting current, a peak current, a peak voltage, and a peak time. In one embodiment, each base curve can be normalized. The base curve(s), the starting current, peak current, peak voltage, and peak time can accurately model the functioning of the IC device, e.g. represented by an I(V) curve.
摘要翻译：由EDA工具可访问的增强库可以包括基线曲线数据库和多个曲线数据集。每个曲线数据集是指具有某些定时特性的标准单元。为了确定这些时序特性，每个曲线数据集识别至少一个基本曲线（在基线曲线数据库中）以及启动电流，峰值电流，峰值电压和峰值时间。在一个实施例中，每个基本曲线可以被归一化。基本曲线，起始电流，峰值电流，峰值电压和峰值时间可以精确地模拟IC器件的功能，例如，由I（V）曲线表示。

48. 发明申请

US20080232513A1 APPARATUS AND METHOD FOR PREAMBLE DETECTION AND INTEGER CARRIER FREQUENCY OFFSET ESTIMATION 有权
标题翻译：预先检测和整体载波频偏估计的装置和方法
公开(公告)号：US20080232513A1
公开(公告)日：2008-09-25
申请号：US12044120
申请日：2008-03-07
申请人： Xin Wang , Yuuta Nakaya , Syuusaku Suzuki , Michiharu Nakamura , Hiroyuki Hayashi
发明人： Xin Wang , Yuuta Nakaya , Syuusaku Suzuki , Michiharu Nakamura , Hiroyuki Hayashi
IPC分类号： H04L27/06 , H03D1/00
CPC分类号： H04L27/2675 , H04L27/2659
摘要： This invention provides an apparatus and method for preamble detection and integer carrier frequency offset estimation, which method comprises the steps of: determining the window of useful subcarriers in preamble transformed to frequency domain based on pre-determined possible integer carrier frequency offset and the length of the preamble, so as to select the useful subcarriers; extracting a plurality of subcarrier sequences having a length equal to that of the preamble from the useful subcarriers; calculating conjugative multiplications of each subcarrier and its neighboring subcarriers in the subcarrier sequences extracted; acquiring the real part of the conjugative multiplications; calculating the cross correlations between the real part of the conjugative multiplications and known preambles modulated by DBPSK, and outputting the calculated correlation values; and detecting preamble index of a target base station with the calculated correlation values to select a target cell, and estimating integer carrier frequency offset with respect to the target base station.
摘要翻译：本发明提供了一种用于前导码检测和整数载波频偏估计的装置和方法，该方法包括以下步骤：基于预定可能的整数载波频率偏移量确定前导码转换到频域的有用子载波的窗口，前导码，以便选择有用的子载波; 从有用的子载波中提取长度等于前导码长度的多个子载波序列; 计算提取的子载波序列中每个子载波及其相邻子载波的共轭乘法; 获取共轭乘法的实部; 计算共轭乘法的实部与由DBPSK调制的已知前同步之间的互相关，并输出所计算的相关值; 以及使用所计算的相关值检测目标基站的前导码索引，以选择目标小区，并且针对目标基站估计整数载波频率偏移。

49. 发明申请

US20080195931A1 Parsing of ink annotations 审中-公开
标题翻译：解析墨迹注释
公开(公告)号：US20080195931A1
公开(公告)日：2008-08-14
申请号：US11589028
申请日：2006-10-27
申请人： Sashi Raghupathy , Paul A. Viola , Michael Shilman , Xin Wang
发明人： Sashi Raghupathy , Paul A. Viola , Michael Shilman , Xin Wang
IPC分类号： G06F17/00
CPC分类号： G06K9/00402
摘要： Annotation recognition and parsing is accomplished by first recognizing and grouping shapes such that relationships between the annotations and the underlying text and/or images can be determined. The recognition and grouping is followed by categorization of recognized annotations according to predefined types. The classification may be according to functionality, relation to content, and the like. In a third phase, the annotations are anchored to the underlying text or images they are found to be related to.
摘要翻译：注释识别和解析是通过首先识别和分组形状来实现的，使得可以确定注释和底层文本和/或图像之间的关系。识别和分组之后是根据预定义类型对所识别的注释进行分类。分类可以根据功能，与内容的关系等。在第三阶段，注释被锚定到被发现与之相关的底层文本或图像。

50. 外观设计

USD551821S1 Container 有权
公开(公告)号：USD551821S1
公开(公告)日：2007-09-25
申请号：US29262620
申请日：2006-07-07
申请人： Xin Wang , Jiang Qun Chen
设计人： Xin Wang , Jiang Qun Chen

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