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91. 发明授权

US08959131B2 Number format pre-conversion instructions 有权
标题翻译：数字格式转换前说明
公开(公告)号：US08959131B2
公开(公告)日：2015-02-17
申请号：US13137950
申请日：2011-09-22
申请人： Jorn Nystad , Andreas Due Engh-Halstvedt , Simon Alex Charles
发明人： Jorn Nystad , Andreas Due Engh-Halstvedt , Simon Alex Charles
IPC分类号： G06F7/38 , G06F7/483 , G06F7/499
CPC分类号： G06F5/00 , G06F7/483 , G06F7/499 , G06F7/49963 , G06F9/30014 , G06F9/30025 , G06F2207/382 , H03M7/24
摘要： Apparatus for processing data includes processing circuitry 16, 18, 20, 22, 24, 26 and decoder circuitry 14 for decoding program instructions. The program instructions decoded include a floating point pre-conversion instruction which performs round-to-nearest ties to even rounding upon the mantissa field of an input floating number to generate an output floating point number with the same mantissa length but with the mantissa rounded to a position corresponding to a shorter mantissa field. The output mantissa field includes a suffix of zero values concatenated the rounded value. The decoder for circuitry 14 is also responsive to an integer pre-conversion instruction to quantize and input integer value using round-to-nearest ties to even rounding to form an output integer operand with a number of significant bits matched to the mantissa size of a floating point number to which the integer is later to be converted using an integer-to-floating point conversion instruction.
摘要翻译：用于处理数据的装置包括用于解码程序指令的处理电路16,18,20,22,24,26和解码器电路14。所解码的程序指令包括一个浮点预转换指令，其执行圆到最近的连接，以便在输入浮点数的尾数字上偶数舍入以产生具有相同尾数长度但尾数四舍五入的输出浮点数对应于较短的尾数字段的位置。输出尾数字段包括将值的后缀连接在舍入值上。用于电路14的解码器还响应于整数预转换指令来量化和输入整数值，使用到最近的连带到偶数舍入以形成输出整数操作数，其具有匹配到的尾数大小的有效位数使用整数到浮点转换指令后续整数的浮点数。

92. 发明授权

US08943119B2 System and method to implement a matrix multiply unit of a broadband processor 有权
标题翻译：实现宽带处理器的矩阵乘法单元的系统和方法
公开(公告)号：US08943119B2
公开(公告)日：2015-01-27
申请号：US13462648
申请日：2012-05-02
申请人： Craig Hansen , Bruce Bateman , John Moussouris
发明人： Craig Hansen , Bruce Bateman , John Moussouris
IPC分类号： G06F7/38 , G06F7/52 , G06F7/533 , G06F7/57 , G06F7/72 , G06F9/30 , G06F17/15 , G06F17/16 , G06F7/48 , G06F7/499
CPC分类号： G06F7/5338 , G06F7/4812 , G06F7/49994 , G06F7/57 , G06F7/724 , G06F9/30014 , G06F9/30036 , G06F17/15 , G06F17/16 , G06F2207/3812 , G06F2207/382 , G06F2207/3824 , G06F2207/3828
摘要： A system and a method are configured to improve the performance of general-purpose processors by implementing a functional unit that computes the product of a matrix operand with a vector operand, producing a vector result. The functional unit fully utilizes the entire resources of a 128 b by 128 b multiplier regardless of the operand size, as the number of elements of the matrix and vector operands increase as operand size is reduced. The unit performs both fixed-point and floating-point multiplications and additions with the highest-possible intermediate accuracy with modest resources.
摘要翻译：一种系统和方法被配置为通过实现一个功能单元来提高通用处理器的性能，该功能单元使用向量操作数来计算矩阵操作数的乘积，产生向量结果。功能单元完全利用128b乘128b乘法器的整个资源，而不考虑操作数大小，因为矩阵和向量操作数的元素数量随着操作数大小的减小而增加。该单元通过适度的资源执行具有最高可能的中间精度的定点和浮点乘法和补充。

93. 发明授权

US08903881B2 Arithmetic circuit, arithmetic processing apparatus and method of controlling arithmetic circuit 有权
标题翻译：算术电路，运算处理装置及运算电路的控制方法
公开(公告)号：US08903881B2
公开(公告)日：2014-12-02
申请号：US13437969
申请日：2012-04-03
申请人： Ryuji Kan , Hideyuki Unno , Kenichi Kitamura
发明人： Ryuji Kan , Hideyuki Unno , Kenichi Kitamura
IPC分类号： G06F7/42 , G06F7/483 , G06F7/499
CPC分类号： G06F7/49942 , G06F7/483
摘要： An arithmetic circuit for quantizing pre-quantized data includes a first input register to store first-format pre-quantized data that includes a mantissa and an exponent, a second input register to store a quantization target exponent, an exponent-correction-value indicating unit to indicate an exponent correction value, an exponent generating unit to generate a quantized exponent obtained by subtracting the exponent correction value from the quantization target exponent, a shift amount generating unit to generate a shift amount obtained by subtracting the exponent of the pre-quantized data and the exponent correction value from the quantization target exponent, a shift unit to generate a quantized mantissa obtained by shifting the mantissa of the pre-quantized data by the shift amount generated by the shift amount generating unit, and an output register to store quantized data that includes the quantized exponent generated by the exponent generating unit and the quantized mantissa generated by the shift unit.
摘要翻译：用于量化预量化数据的算术电路包括：第一输入寄存器，用于存储包括尾数和指数的第一格式的预量化数据;存储量化目标指数的第二输入寄存器;指数校正值指示单元指示指数校正值，指数生成单元，用于生成通过从量化目标指数中减去指数校正值而获得的量化指数;移位量生成单元，生成通过减去预量化数据的指数得到的移位量以及来自量化目标指数的指数校正值，用于生成通过将预量化数据的尾数偏移由移位量产生单元生成的移位量而获得的量化尾数的移位单元和用于存储量化数据的输出寄存器其包括由指数生成单元生成的量化指数和量化的尾数gen 由换档单元擦除。

94. 发明授权

US08799344B2 Comparator unit for comparing values of floating point operands 有权
标题翻译：用于比较浮点运算数值的比较器单元
公开(公告)号：US08799344B2
公开(公告)日：2014-08-05
申请号：US11394081
申请日：2006-03-31
申请人： Guy L. Steele, Jr.
发明人： Guy L. Steele, Jr.
IPC分类号： G06F7/38 , G06F9/38 , G06F7/487 , G06F9/30 , G06F7/483 , G06F7/02 , G06F7/499 , G06F5/01
CPC分类号： G06F5/012 , G06F5/015 , G06F7/026 , G06F7/483 , G06F7/4873 , G06F7/4876 , G06F7/49905 , G06F9/30014 , G06F9/30021 , G06F9/30094 , G06F9/3861 , G06F9/3885
摘要： A floating point comparator circuit for comparing a plurality of floating point operands includes a plurality of analysis circuits, one for each of the floating point operands, configured to determine a format of each of the floating point operands based upon floating point status information encoded within each of the floating point operands, and a result generator circuit coupled to the analysis circuits, the result generator circuit configured to generate a result signal based on the format determined by each analysis circuit and based on a comparative relationship among the floating point operands. The format of each of the floating point operands may be from a group comprising: not-a-number (NaN), infinity, normalized, denormalized, zero, invalid operation, overflow, underflow, division by zero, exact, and inexact. The result generator circuit may ignore the encoded floating point statuses of the plurality of floating point operands when comparing just the magnitudes of the plurality of floating point operands.
摘要翻译：用于比较多个浮点操作数的浮点比较器电路包括多个分析电路，每个分析电路用于每个浮点操作数，其被配置为基于在每个浮点操作数中编码的浮点状态信息来确定每个浮点操作数的格式以及耦合到分析电路的结果生成器电路，所述结果生成器电路被配置为基于由每个分析电路确定的格式并且基于所述浮点操作数之间的比较关系生成结果信号。每个浮点操作数的格式可以来自包括以下的组：非数字（NaN），无穷大，归一化，非归一化，零，无效操作，溢出，下溢，除以零，精确和不精确。当仅比较多个浮点操作数的大小时，结果生成器电路可以忽略多个浮点操作数的编码的浮点状态。

95. 发明申请

US20130282777A1 System and Method for a Floating-Point Format for Digital Signal Processors 有权
标题翻译：数字信号处理器浮点格式的系统和方法
公开(公告)号：US20130282777A1
公开(公告)日：2013-10-24
申请号：US13452701
申请日：2012-04-20
申请人： Yuanbin Guo , Tong Sun , Weizhong Chen
发明人： Yuanbin Guo , Tong Sun , Weizhong Chen
IPC分类号： G06F7/483 , G06F7/499 , G06F17/10
CPC分类号： G06F7/483
摘要： An embodiment of a system and method for performing a numerical operation on input data in a hybrid floating-point format includes representing input data as a sign bit, exponent bits, and mantissa bits. The exponent bits are represented as an unsigned integer including an exponent bias, and a signed numerical value of zero is represented as a first reserved combination of the mantissa bits and the exponent bits. Each of all other combinations of the mantissa bits and the exponent bits represents a real finite non-zero number. The mantissa bits are operated on with a “one” bit before a radix point for the all other combinations of the mantissa bits and the exponent bits.
摘要翻译：用于以混合浮点格式对输入数据进行数值运算的系统和方法的实施例包括将输入数据表示为符号位，指数位和尾数位。指数位被表示为包括指数偏差的无符号整数，并且带符号数值为零被表示为尾数位和指数位的第一保留组合。尾数位和指数位的所有其他组合中的每一个表示真实的有限非零数。尾数位在尾数位和指数位的所有其他组合的小数点之前以“一”位操作。

96. 发明申请

US20130212139A1 MIXED PRECISION ESTIMATE INSTRUCTION COMPUTING NARROW PRECISION RESULT FOR WIDE PRECISION INPUTS 有权
标题翻译：混合精度估计指标计算精度高精度结果进行精确输入
公开(公告)号：US20130212139A1
公开(公告)日：2013-08-15
申请号：US13369470
申请日：2012-02-09
申请人： Michael K. Gschwind , Valentina Salapura
发明人： Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F7/483 , G06F7/499 , G06F17/10
CPC分类号： G06F7/483 , G06F7/499 , G06F7/49905
摘要： A technique is provided for performing a mixed precision estimate. A processing circuit receives an input of a first precision having a wide precision value. The processing circuit computes an output in an output exponent range corresponding to a narrow precision value based on the input having the wide precision value.
摘要翻译：提供了一种用于执行混合精度估计的技术。处理电路接收具有宽精度值的第一精度的输入。处理电路基于宽精度值的输入，计算与窄精度值对应的输出指数范围内的输出。

97. 发明申请

US20110072066A1 Apparatus and method for performing fused multiply add floating point operation 有权
标题翻译：用于执行融合乘法添加浮点运算的装置和方法
公开(公告)号：US20110072066A1
公开(公告)日：2011-03-24
申请号：US12585668
申请日：2009-09-21
申请人： David Raymond Lutz
发明人： David Raymond Lutz
IPC分类号： G06F7/487 , G06F7/499 , G06F7/485
CPC分类号： G06F7/483 , G06F7/5443
摘要： A fused multiply add floating point unit 1 includes multiplying circuitry 4 and adding circuitry 8. The multiply circuitry 4 multiplies operands B and C having N-bit significands to generate an unrounded product B*C. The unrounded product B*C has an M-bit significand, where M>N. The adding circuitry 8 receives an operand A that is input at a later processing cycle than a processing cycle at which the multiplying circuitry 4 receives operands B and C. The adding circuitry 8 commences processing of the operand A after the unrounded product B*C is generated by the multiplying circuitry 4. The adding circuitry 8 adds the operand A to the unrounded product B*C and outputs a rounded result A+B*C.
摘要翻译：融合乘法加法单元1包括乘法电路4和加法电路8.乘法电路4将具有N位有效值的操作数B和C相乘以产生未被包围的乘积B * C。未周边产品B * C具有M位有效位数，其中M> N。加法电路8接收在比乘法电路4接收操作数B和C的处理周期稍晚的处理周期输入的操作数A.加法电路8开始对未包围的乘积B * C之后的操作数A的处理加法电路8将操作数A加到未包围的乘积B * C，并输出舍入结果A + B * C。

98. 发明授权

US07860915B2 Digital signal processing circuit having a pattern circuit for determining termination conditions 有权
标题翻译：具有用于确定终止条件的模式电路的数字信号处理电路
公开(公告)号：US07860915B2
公开(公告)日：2010-12-28
申请号：US11433332
申请日：2006-05-12
申请人： Vasisht Mantra Vadi , Jennifer Wong , Bernard J. New , Alvin Y. Ching , John M. Thendean , Anna Wing Wah Wong , James M. Simkins
发明人： Vasisht Mantra Vadi , Jennifer Wong , Bernard J. New , Alvin Y. Ching , John M. Thendean , Anna Wing Wah Wong , James M. Simkins
IPC分类号： G06F7/499
CPC分类号： G06F7/02 , G06F7/5443 , G06F7/57 , G06F7/575 , G06F2207/025 , G06F2207/3828 , G06K9/00986 , H03K19/1737
摘要： A method for detecting a pattern from an arithmetic logic unit (ALU) in an integrated circuit. The method includes the steps of: generating an output from an ALU; bitwise comparing the ALU output to a pattern to produce a first output; inverting the pattern and comparing the ALU output with the inverted pattern to produce a second output; bitwise masking the first and second outputs using a mask of a plurality of masks to produce third and fourth output bits; combining the third and fourth output bits to produce first and a second output comparison bits; and storing the first and second output comparison bits in a memory.
摘要翻译：一种用于从集成电路中的算术逻辑单元（ALU）检测模式的方法。该方法包括以下步骤：产生来自ALU的输出; 将ALU输出与模式进行比特比较以产生第一输出; 反转图案并将ALU输出与反转图案进行比较以产生第二输出; 使用多个掩模的掩码对第一和第二输出进行逐位掩蔽以产生第三和第四输出位; 组合第三和第四输出比特以产生第一和第二输出比较比特; 以及将第一和第二输出比较位存储在存储器中。

99. 发明授权

US07853636B2 Digital signal processing circuit having a pattern detector circuit for convergent rounding 有权
标题翻译：具有用于收敛四舍五入的图案检测器电路的数字信号处理电路
公开(公告)号：US07853636B2
公开(公告)日：2010-12-14
申请号：US11432847
申请日：2006-05-12
申请人： Bernard J. New , Jennifer Wong , James M. Simkins , Alvin Y. Ching , John M. Thendean , Anna Wing Wah Wong , Vasisht Mantra Vadi
发明人： Bernard J. New , Jennifer Wong , James M. Simkins , Alvin Y. Ching , John M. Thendean , Anna Wing Wah Wong , Vasisht Mantra Vadi
IPC分类号： G06F7/499
CPC分类号： G06F7/02 , G06F7/5443 , G06F7/57 , G06F7/575 , G06F2207/025 , G06F2207/3828 , G06K9/00986 , H03K19/1737
摘要： An integrated circuit (IC) for convergent rounding including: an adder circuit configured to produce a summation; a comparison circuit configured to bitwise compare the summation with an input pattern, bitwise mask the comparison using a mask, and combine the masked comparison to produce a comparison bit; and rounding circuitry for rounding the summation based at least in part on the comparison bit.
摘要翻译：一种用于收敛舍入的集成电路（IC），包括：加法器电路，被配置为产生求和; 比较电路，被配置为将所述求和与输入模式进行逐位比较，使用掩码对所述比较进行逐位掩码，并将所述掩蔽比较结合以产生比较位; 以及舍入电路，用于至少部分地基于所述比较位对所述求和进行舍入。

100. 发明申请

US20100131580A1 APPARATUS AND METHODS FOR HARDWARE-EFFICIENT UNBIASED ROUNDING 有权
标题翻译：用于硬件效率的解决方案的装置和方法
公开(公告)号：US20100131580A1
公开(公告)日：2010-05-27
申请号：US12595961
申请日：2008-09-17
申请人： Ofir Avraham Kanter , Ilan Bar
发明人： Ofir Avraham Kanter , Ilan Bar
IPC分类号： G06F7/499
CPC分类号： G06F7/49963
摘要： A system and method for unbiased rounding away from, or toward, zero comprising apparatus for truncating N bits from an original M bit input number thereby to provide a M−N bit number, and apparatus for adding the equivalent value of ‘½’ to the M−N bit number unless the input number is negative, or positive, respectively, and the N truncated bits represent exactly ½.
摘要翻译：一种用于从零包括用于从原始M位输入数字截断N位的装置的零偏置或朝向零的系统和方法，从而提供M-N位数，以及用于将等效值“1/2”加到 M-N位号，除非输入数字分别为负数，或正数，N个截断位表示正好为1/2。

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