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11. 发明申请

US20100156457A1 PLD PROVIDING SOFT WAKEUP LOGIC 有权
标题翻译： PLD提供软件唤醒逻辑
公开(公告)号：US20100156457A1
公开(公告)日：2010-06-24
申请号：US12340358
申请日：2008-12-19
申请人： Jonathan W. Greene , Gregory Bakker , Vidyadhara Bellippady , Volker Hecht , Theodore Speers
发明人： Jonathan W. Greene , Gregory Bakker , Vidyadhara Bellippady , Volker Hecht , Theodore Speers
IPC分类号： H03K19/177 , H03K19/0175
CPC分类号： H03K19/17784
摘要： A programmable logic device (PLD) with a plurality of programmable regions is disclosed. Some of the programmable regions have switch power or ground supplies to allow them to be put into a low-power state in one or more low-power modes. At least one of the programmable regions always remains on during the low-power modes to enable the user to design custom PLD power management logic that may be placed in the always-on programmable region.
摘要翻译：公开了具有多个可编程区域的可编程逻辑器件（PLD）。一些可编程区域具有开关电源或接地电源，以允许它们在一个或多个低功率模式下进入低功率状态。在低功率模式期间，至少一个可编程区域始终保持接通状态，以使用户能够设计定制的PLD功率管理逻辑，该逻辑可以放置在永久可编程区域中。

12. 发明授权

US07701250B1 (N+1) input flip-flop packing with logic in FPGA architectures 有权
标题翻译：（N + 1）输入触发器封装，具有FPGA架构中的逻辑
公开(公告)号：US07701250B1
公开(公告)日：2010-04-20
申请号：US12360971
申请日：2009-01-28
申请人： Sinan Kaptanoglu
发明人： Sinan Kaptanoglu
IPC分类号： G06F7/38 , H03K19/177
CPC分类号： H03K19/1737 , H03K19/17728
摘要： A logic module and flip-flop includes input multiplexers having data inputs coupled to routing resources. A clock multiplexer has inputs coupled to clock resources, and an output. An input-select multiplexer has a first input coupled to the output of an input multiplexer. A flip-flop has a clock input coupled to the output of the clock multiplexer, and a data output coupled to an input of the input-select multiplexer. A logic module has data inputs coupled to the output of the input select multiplexers. A flip-flop multiplexer is coupled to the data input of the flip-flop, and has inputs input coupled to the output of the first input multiplexer, the data output of the logic module, and a third input coupled to routing resources.
摘要翻译：逻辑模块和触发器包括具有耦合到路由资源的数据输入的输入多路复用器。时钟复用器具有耦合到时钟资源的输入和输出。输入选择多路复用器具有耦合到输入多路复用器的输出的第一输入。触发器具有耦合到时钟复用器的输出的时钟输入和耦合到输入选择多路复用器的输入的数据输出。逻辑模块具有耦合到输入选择多路复用器的输出的数据输入。触发器多路复用器耦合到触发器的数据输入，并具有耦合到第一输入多路复用器的输出，逻辑模块的数据输出和耦合到路由资源的第三输入的输入输入。

13. 发明授权

US07697330B1 Non-volatile memory array having drain-side segmentation for an FPGA device 有权
标题翻译：具有用于FPGA器件的漏极侧分割的非易失性存储器阵列
公开(公告)号：US07697330B1
公开(公告)日：2010-04-13
申请号：US11961203
申请日：2007-12-20
申请人： Vidyahara Bellippady , Santosh Yachareni , Fethi Dhaoui , Zhigang Wang
发明人： Vidyahara Bellippady , Santosh Yachareni , Fethi Dhaoui , Zhigang Wang
IPC分类号： G11C16/00
CPC分类号： G11C16/0441
摘要： A non-volatile memory array for an FPGA comprises a plurality of memory cells arranged in rows and columns and divided into a plurality of row segments. The source of each non-volatile memory transistor in each segment is coupled together to a common source line. A column segment line is associated with each segment of the array, and is coupled to the drains of each non-volatile memory transistor in the segment. A segment select transistor is coupled between each column segment line and its associated column line, and a high-voltage driver transistor is coupled to each column line.
摘要翻译：用于FPGA的非易失性存储器阵列包括以行和列排列并分成多个行段的多个存储单元。每个段中的每个非易失性存储器晶体管的源极耦合到一个共同的源极线。列分段线与阵列的每个段相关联，并且被耦合到段中的每个非易失性存储器晶体管的漏极。段选择晶体管耦合在每个列分段线与其相关联的列线之间，并且高电压驱动晶体管耦合到每个列线。

14. 发明授权

US07683660B1 Programmable logic device with a microcontroller-based control system 有权
标题翻译：可编程逻辑器件，具有基于微控制器的控制系统
公开(公告)号：US07683660B1
公开(公告)日：2010-03-23
申请号：US12023299
申请日：2008-01-31
申请人： Gregory Bakker , Joel Landry , William C. Plants
发明人： Gregory Bakker , Joel Landry , William C. Plants
IPC分类号： H03K19/173
CPC分类号： H03K19/1733 , G06F17/5054
摘要： A computer program product in a computer-readable medium for use in a microcontroller-based control system in a programmable logic integrated circuit device is disclosed. The computer program product comprises first instructions for initializing the device, second instructions for reading programming data from a data source external to the programmable logic integrated circuit device, third instructions for transferring the programming data into control elements internal to the programmable logic integrated circuit device. Provision is made for fourth instructions for saving at least a part of the internal logic state of the user logic programmed into the programmable logic integrated circuit device into a non-volatile memory block and for fifth instructions for restoring at least a part of the internal logic state of the user logic programmed into the programmable logic integrated circuit device from a non-volatile memory block. The programmable logic integrated circuit device, comprises a microcontroller block and a programmable logic block with programming circuitry, and has a sub-bus which couples the microcontroller block to the programming circuitry.
摘要翻译：公开了一种用于可编程逻辑集成电路装置中基于微控制器的控制系统的计算机可读介质中的计算机程序产品。计算机程序产品包括用于初始化设备的第一指令，用于从可编程逻辑集成电路器件外部的数据源读取编程数据的第二指令，用于将编程数据传送到可编程逻辑集成电路器件内部的控制元件的第三指令。规定了第四条指令，用于将编程到可编程逻辑集成电路设备中的用户逻辑的内部逻辑状态的至少一部分保存到非易失性存储器块中，以及用于恢复内部逻辑的至少一部分的第五指令从非易失性存储器块编程到可编程逻辑集成电路器件中的用户逻辑状态。可编程逻辑集成电路器件包括微控制器模块和具有编程电路的可编程逻辑模块，并且具有将微控制器模块耦合到编程电路的子总线。

15. 发明授权

US07646218B2 Architecture and interconnect scheme for programmable logic circuits 失效
标题翻译：可编程逻辑电路的架构和互连方案
公开(公告)号：US07646218B2
公开(公告)日：2010-01-12
申请号：US12215118
申请日：2008-06-24
申请人： Benjamin S. Ting
发明人： Benjamin S. Ting
IPC分类号： H03K19/177
CPC分类号： H03K19/17704 , H03K19/17728 , H03K19/17736 , H03K19/1778 , H03K19/17796
摘要： An architecture of hierarchical interconnect scheme for field programmable gate arrays (FPGAs). A first layer of routing network lines is used to provide connections amongst sets of block connectors where block connectors are used to provide connectability between logical cells and accessibility to the hierarchical routing network. A second layer of routing network lines provides connectability between different first layers of routing network lines. Additional layers of routing network lines are implemented to provide connectability between different prior layers of routing network lines. An additional routing layer is added when the number of cells is increased as the prior cell count in the array increases while the length of the routing lines and the number of routing lines also increases. Switching networks are used to provide connectability among same and different layers of routing network lines, each switching network composed primarily of program controlled passgates and, when needed, drivers.
摘要翻译：用于现场可编程门阵列（FPGA）的分层互连方案架构。第一层路由网络线路用于提供块连接器组之间的连接，其中块连接器用于提供逻辑单元之间的连接性和对分层路由网络的可访问性。第二层路由网络线路提供不同第一层路由网络线路之间的连接性。路由网络线路的附加层被实现以提供不同的现有路由网络线路之间的可连接性。当阵列中的先前单元计数增加时，单元数量增加，而路由线路长度和路由线路数量也增加时，将添加一个额外的路由层。交换网络用于在相同和不同层次的路由网络线路之间提供可连接性，每个交换网络主要由程序控制的门户组成，并且在需要时由驱动程序组成。

16. 发明授权

US07579895B2 Clock-generator architecture for a programmable-logic-based system on a chip 有权
标题翻译：用于芯片上基于可编程逻辑的系统的时钟发生器架构
公开(公告)号：US07579895B2
公开(公告)日：2009-08-25
申请号：US11932807
申请日：2007-10-31
申请人： Shin-Nan Sun , Limin Zhu , Theodore Speers , Gregory Bakker
发明人： Shin-Nan Sun , Limin Zhu , Theodore Speers , Gregory Bakker
IPC分类号： H03K17/62
CPC分类号： H03K19/1776 , G01K7/015 , G06F1/08 , G06F1/28 , G06F1/30 , G06F15/7842 , G06F15/7867 , H03F3/45475 , H03F2203/45136 , H03F2203/45166 , H03K17/223 , H03K19/177 , H03K19/17732
摘要： A programmable system-on-a-chip integrated circuit device comprises at least one of a crystal oscillator circuit, an RC oscillator circuit, and an external oscillator input. A clock conditioning circuit is selectively coupleable to one of the programmable logic block, the crystal oscillator circuit, the RC oscillator circuit, and the external oscillator input. A real-time clock is selectively coupleable to one of the programmable logic block, the crystal oscillator circuit, the RC oscillator circuit, and the external oscillator input. A programmable logic block is coupled to the clock conditioning circuit and the real-time clock.
摘要翻译：一种可编程片上系统集成电路器件，包括晶体振荡器电路，RC振荡器电路和外部振荡器输入中的至少一个。时钟调理电路选择性地耦合到可编程逻辑块，晶体振荡器电路，RC振荡器电路和外部振荡器输入之一。实时时钟可选择性地耦合到可编程逻辑块，晶体振荡器电路，RC振荡器电路和外部振荡器输入之一。可编程逻辑块耦合到时钟调节电路和实时时钟。

17. 发明授权

US07579869B2 Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks 有权
标题翻译：可重复块在具有分段轨道的现场可编程门阵列中产生非均匀路由架构
公开(公告)号：US07579869B2
公开(公告)日：2009-08-25
申请号：US12131258
申请日：2008-06-02
申请人： Arunangshu Kundu , Eric Sather , William C. Plants
发明人： Arunangshu Kundu , Eric Sather , William C. Plants
IPC分类号： H03K19/177 , H01L25/00
CPC分类号： H03K19/17736 , G11C5/063 , H01L27/118
摘要： A repeatable non-uniform segmented routing architecture in a field programmable gate array comprising: a repeatable block of routing tracks, the routing tracks grouped into sets of routing tracks, each set having a first routing track in a first track position, a second routing track in a last track position, a programmable element, and a direct address device for programming the programmable element; wherein at least one of the routing tracks is segmented into non-uniform lengths by the programmable element and the second routing track crosses-over to the first track position in a region adjacent to an edge of the repeatable block; and wherein a first plurality of the routing track sets proceed in a horizontal direction and a second plurality of the routing track sets proceed in a vertical direction.
摘要翻译：在现场可编程门阵列中的可重复的非均匀分段路由架构，包括：可重复的路由轨道块，所述路由轨迹被分组为路由轨道集合，每个路由集合具有处于第一轨道位置的第一路由轨道，第二路由轨迹在最后轨道位置，可编程元件和用于对可编程元件进行编程的直接地址设备; 其中所述路由轨道中的至少一个由所述可编程元件分段成非均匀长度，并且所述第二路由轨道在与所述可重复块的边缘相邻的区域中跨越到所述第一轨道位置; 并且其中第一多个所述路线轨迹组在水平方向上行进，并且所述第二多个所述路线轨迹组在垂直方向上进行。

18. 发明授权

US07560954B2 Programmable system on a chip for temperature monitoring and control 有权
标题翻译：片上可编程系统进行温度监控
公开(公告)号：US07560954B2
公开(公告)日：2009-07-14
申请号：US12178874
申请日：2008-07-24
申请人： Rabindranath Balasubramanian , Limin Zhu , Gregory Bakker
发明人： Rabindranath Balasubramanian , Limin Zhu , Gregory Bakker
IPC分类号： H03K19/173
CPC分类号： H03K19/1776 , G01K7/015 , G06F1/08 , G06F1/28 , G06F1/30 , G06F15/7842 , G06F15/7867 , H03F3/45475 , H03F2203/45136 , H03F2203/45166 , H03K17/223 , H03K19/177 , H03K19/17732
摘要： A programmable system-on-a-chip integrated circuit device includes a programmable logic block, at least one user non-volatile memory block, and temperature sensing and control analog and digital circuits on a single semiconductor integrated circuit chip or a flip chip, face-to-face, or other multiple die configuration. The programmable system-on-a-chip integrated circuit with temperature measuring and control circuitry performs temperature measurement and control functions and can be used to create an on-chip temperature log.
摘要翻译：可编程片上系统集成电路器件包括可编程逻辑块，至少一个用户非易失性存储器块，以及在单个半导体集成电路芯片或倒装芯片上的温度感测和控制模拟和数字电路面对或其他多模配置。具有温度测量和控制电路的可编程片上系统芯片集成电路执行温度测量和控制功能，可用于创建片上温度记录。

19. 发明授权

US07545169B1 FPGA architecture having two-level cluster input interconnect scheme without bandwidth limitation 有权
标题翻译：具有两级集群输入互连方案的FPGA架构，无带宽限制
公开(公告)号：US07545169B1
公开(公告)日：2009-06-09
申请号：US12173225
申请日：2008-07-15
申请人： Wenyi Feng , Sinan Kaptanoglu
发明人： Wenyi Feng , Sinan Kaptanoglu
IPC分类号： H01L25/00 , H03K19/177
CPC分类号： H03K19/17736
摘要： An interconnect architecture for a programmable logic device comprises a plurality of interconnect routing lines. The data inputs of a plurality of first-level multiplexers are connected to the plurality of interconnect routing lines such that each interconnect routing line is connected to only one multiplexer. A plurality of second-level multiplexers are organized into multiplexer groups. Each of a plurality of lookup tables is associated with one of the multiplexer groups and has a plurality of lookup table inputs. Each lookup table input is coupled to the output of a different one of the second-level multiplexers in the one of the multiplexer groups with which it is associated. The data inputs of the second-level multiplexers are connected to the outputs of the first-level multiplexers such that each output of each first-level multiplexer is connected to an input of only one second-level multiplexer in each multiplexer group.
摘要翻译：用于可编程逻辑器件的互连架构包括多个互连路由线。多个第一级复用器的数据输入连接到多个互连路由线，使得每个互连路由线仅连接到一个多路复用器。多个第二级多路复用器被组织成多路复用器组。多个查找表中的每一个与多路复用器组中的一个相关联并且具有多个查找表输入。每个查找表输入耦合到与其相关联的多路复合器组中的一个中的不同的一个二级多路复用器的输出。第二级复用器的数据输入连接到第一级复用器的输出，使得每个第一级多路复用器的每个输出连接到每个多路复用器组中仅一个第二级多路复用器的输入。

20. 发明授权

US07545166B2 Field-programmable gate array low voltage differential signaling driver utilizing two complimentary output buffers 有权
标题翻译：采用两个互补输出缓冲器的现场可编程门阵列低压差分信号驱动器
公开(公告)号：US07545166B2
公开(公告)日：2009-06-09
申请号：US12109487
申请日：2008-04-25
申请人： Donald Y. Yu , Wei-Min Kuo
发明人： Donald Y. Yu , Wei-Min Kuo
IPC分类号： H03K19/173
CPC分类号： H03K19/17744 , H03K19/017581
摘要： A low voltage signaling differential signaling driver comprising a first output line coupled to a delay circuit, a first multiplexer and a first output buffer. The first output line is also coupled to an inverter, a second multiplexer and a second output buffer.
摘要翻译：低电压信号差分信令驱动器，包括耦合到延迟电路的第一输出线，第一多路复用器和第一输出缓冲器。第一输出线还耦合到反相器，第二多路复用器和第二输出缓冲器。

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