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11. 发明授权

US07308633B2 Master controller architecture 失效
标题翻译：主控制器架构
公开(公告)号：US07308633B2
公开(公告)日：2007-12-11
申请号：US10999720
申请日：2004-11-30
申请人： Alexandre Andreev , Sergey Gribok , Anatoli Bolotov
发明人： Alexandre Andreev , Sergey Gribok , Anatoli Bolotov
IPC分类号： G01R31/28 , G11C29/00
CPC分类号： G11C29/16 , G11C29/44 , G11C29/4401 , G11C29/72
摘要： A master controller for an RRAM subsystem. An interface communicates with at least one RRAM controller. A main control unit selects and implements test and repair operations on the RRAM subsystem through the RRAM controller. A timer determines a maximum number of test and repair operations that can be implemented within a given time. Thus, a master controller is included in the RRAM subsystem. The master controller has a relatively simple interface, and performs test and repair operations on the RRAM subsystem. The advantages of using the master controller include an elimination of additional test ports, simplification of the process of preparing the test vectors for RRAM testing, and the master controller is able to accumulate test results and initiate repairs based on those results. In this manner, the RRAM subsystem has a self-repair functionality.
摘要翻译：用于RRAM子系统的主控制器。接口与至少一个RRAM控制器通信。主控单元通过RRAM控制器对RRAM子系统进行测试和修复操作。定时器确定在给定时间内可以实现的最大测试和修复操作数。因此，主控制器包含在RRAM子系统中。主控制器具有相对简单的接口，并对RRAM子系统执行测试和修复操作。使用主控制器的优点包括消除额外的测试端口，简化了用于RRAM测试的测试向量的准备过程，并且主控制器能够根据这些结果积累测试结果并启动修复。以这种方式，RRAM子系统具有自修复功能。

12. 发明授权

US07093228B2 Method and system for classifying an integrated circuit for optical proximity correction 有权
标题翻译：用于对用于光学邻近校正的集成电路进行分类的方法和系统
公开(公告)号：US07093228B2
公开(公告)日：2006-08-15
申请号：US10327304
申请日：2002-12-20
申请人： Alexandre Andreev , Ivan Pavisic , Lav Ivanovic
发明人： Alexandre Andreev , Ivan Pavisic , Lav Ivanovic
IPC分类号： G06F17/50
CPC分类号： G03F1/36 , G03F7/70441
摘要： A method and system for performing optical proximity correction (OPC) on an integrated circuit (IC) chip design is disclosed. The system and method of the present invention includes dividing the IC chip into a plurality of local task regions, identifying congruent local task regions, classifying congruent local task regions into corresponding groups, and performing OPC for each group of congruent local task regions.By identifying and grouping congruent local task regions in the IC chip, according to the method and system disclosed herein, only one OPC procedure (e.g., evaluation and correction) needs to be performed per group of congruent local task regions. The amount of data to be evaluated and the number of corrections performed is greatly reduced because OPC is not performed on repetitive portions of the IC chip design, thereby resulting in significant savings in computing resources and time.
摘要翻译：公开了一种在集成电路（IC）芯片设计上执行光学邻近校正（OPC）的方法和系统。本发明的系统和方法包括将IC芯片划分为多个本地任务区域，识别同一个本地任务区域，将等同的本地任务区域分类为相应的组，并为每组全局本地任务区域执行OPC。通过根据本文所公开的方法和系统识别和分组IC芯片中的一致的本地任务区域，需要在每一组一致的本地任务区域中执行一个OPC过程（例如，评估和校正）。由于不对IC芯片设计的重复部分执行OPC，所以要评估的数据量和校正次数大大降低，从而大大节省了计算资源和时间。

13. 发明申请

US20120278775A1 Method and Apparatus for Generating Memory Models and Timing Database 失效
标题翻译：用于生成内存模型和时序数据库的方法和装置
公开(公告)号：US20120278775A1
公开(公告)日：2012-11-01
申请号：US13547884
申请日：2012-07-12
申请人： Alexandre Andreev , Andrey Nikitin , Ranko Scepanovic , Igor A. Vikhliantsev
发明人： Alexandre Andreev , Andrey Nikitin , Ranko Scepanovic , Igor A. Vikhliantsev
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method and apparatus are provided for using a memory timing database. A plurality of characterization memories are defined, which can be mapped to a memory resource. Each characterization memory has different memory parameters. A plurality of variants of tiling each characterization memory to the memory resource are also defined. Timing characteristics of each tiling variant of each characterization memory are stored in the memory timing database for the memory resource based on sets of input ramptimes and output loads.
摘要翻译：提供了一种使用存储器定时数据库的方法和装置。定义了多个表征存储器，其可被映射到存储器资源。每个表征存储器具有不同的存储器参数。还定义了将每个表征存储器平铺到存储器资源的多种变型。每个表征存储器的每个平铺变体的时序特征基于输入夯实值和输出负载的集合存储在用于存储器资源的存储器定时数据库中。

14. 发明授权

US08176397B2 Variable redundancy reed-solomon encoder 失效
标题翻译：可变冗余雷达独奏编码器
公开(公告)号：US08176397B2
公开(公告)日：2012-05-08
申请号：US12211985
申请日：2008-09-17
申请人： Pavel Panteleev , Alexandre Andreev , Elyar Gasanov , Ilya Neznanov
发明人： Pavel Panteleev , Alexandre Andreev , Elyar Gasanov , Ilya Neznanov
IPC分类号： G06F11/00
CPC分类号： H03M13/1515 , H03M13/2906 , H03M13/2942 , H03M13/6516
摘要： A fixed length Reed-Solomon encoder is configured to produce a first fixed number of redundant symbols. The fixed length Reed-Solomon encoder is configured with an encoding polynomial that is fixed. A symbol preprocessor maps each input data symbol to a transformed input data symbol. A symbol postprocessor maps a second fixed number of redundant symbols output from the fixed length Reed-Solomon encoder to a set of redundant symbols. The second fixed number of redundant symbols is less than the first fixed number of redundant symbols.
摘要翻译：固定长度的里德 - 所罗门编码器被配置为产生第一固定数量的冗余符号。固定长度Reed-Solomon编码器配置有固定的编码多项式。符号预处理器将每个输入数据符号映射到经变换的输入数据符号。符号后处理器将固定长度Reed-Solomon编码器输出的第二固定数量的冗余符号映射到一组冗余符号。第二固定数量的冗余符号小于第一固定数量的冗余符号。

15. 发明授权

US08046643B2 Transport subsystem for an MBIST chain architecture 失效
标题翻译：用于MBIST链架构的传输子系统
公开(公告)号：US08046643B2
公开(公告)日：2011-10-25
申请号：US12183512
申请日：2008-07-31
申请人： Alexandre Andreev , Anatoli Bolotov , Mikhail Grinchuk
发明人： Alexandre Andreev , Anatoli Bolotov , Mikhail Grinchuk
IPC分类号： G11C29/00 , G01R31/28
CPC分类号： G11C29/48 , G11C29/1201 , G11C29/26 , G11C29/32 , G11C2029/2602 , G11C2029/5602
摘要： An apparatus including a controller configured to present one or more commands and receive one or more responses, a plurality of transport circuits configured to receive one of the commands, present the responses, and generate one or more control signals, and a plurality of memory-controlling circuits, each coupled to a respective one of the plurality of transport circuits and configured to generate one or more memory access signals in response to the one or more control signals, receive one or more memory output signals from a respective memory in response to the one or more memory access signals, and generate the responses in response to the one or more memory output signals. Each respective memory may be independently sized. The controller generally provides a common testing routine for each respective memory that may be adjusted for the size of each respective memory by the memory-controlling circuits.
摘要翻译：一种装置，包括：控制器，被配置为呈现一个或多个命令并接收一个或多个响应;多个传输电路，被配置为接收命令中的一个，呈现响应，并产生一个或多个控制信号;以及多个存储器 - 控制电路，每个耦合到所述多个传输电路中的相应一个，并被配置为响应于所述一个或多个控制信号而产生一个或多个存储器访问信号，响应于所述控制电路响应于所述控制电路接收来自相应存储器的一个或多个存储器输出信号一个或多个存储器访问信号，并且响应于一个或多个存储器输出信号而产生响应。各个存储器可以独立地定尺寸。控制器通常为每个相应的存储器提供通用的测试程序，这些存储器可以通过存储器控制电路为每个相应的存储器的大小进行调整。

16. 发明申请

US20100070831A1 VARIABLE REDUNDANCY REED-SOLOMON ENCODER 失效
标题翻译：可变冗余冗余编码器
公开(公告)号：US20100070831A1
公开(公告)日：2010-03-18
申请号：US12211985
申请日：2008-09-17
申请人： Elyar Gasanov , Ilya Neznanov , Pavel Panteleev , Alexandre Andreev
发明人： Elyar Gasanov , Ilya Neznanov , Pavel Panteleev , Alexandre Andreev
IPC分类号： H03M13/15 , G06F11/07
CPC分类号： H03M13/1515 , H03M13/2906 , H03M13/2942 , H03M13/6516
摘要： A fixed length Reed-Solomon encoder is configured to produce a first fixed number of redundant symbols. The fixed length Reed-Solomon encoder is configured with an encoding polynomial that is fixed. A symbol preprocessor maps each input data symbol to a transformed input data symbol. A symbol postprocessor maps a second fixed number of redundant symbols output from the fixed length Reed-Solomon encoder to a set of redundant symbols. The second fixed number of redundant symbols is less than the first fixed number of redundant symbols.
摘要翻译：固定长度的里德 - 所罗门编码器被配置为产生第一固定数量的冗余符号。固定长度Reed-Solomon编码器配置有固定的编码多项式。符号预处理器将每个输入数据符号映射到经变换的输入数据符号。符号后处理器将固定长度Reed-Solomon编码器输出的第二固定数量的冗余符号映射到一组冗余符号。第二固定数量的冗余符号小于第一固定数量的冗余符号。

17. 发明授权

US07584442B2 Method and apparatus for generating memory models and timing database 失效
标题翻译：用于生成内存模型和计时数据库的方法和装置
公开(公告)号：US07584442B2
公开(公告)日：2009-09-01
申请号：US11298894
申请日：2005-12-09
申请人： Alexandre Andreev , Andrey Nikitin , Ranko Scepanovic , Igor A. Vikhliantsev
发明人： Alexandre Andreev , Andrey Nikitin , Ranko Scepanovic , Igor A. Vikhliantsev
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method and apparatus are provided for creating and using a memory timing database. A plurality of characterization memories are defined, which can be mapped to a memory resource. Each characterization memory has different memory parameters. A plurality of variants of tiling each characterization memory to the memory resource are also defined. Timing characteristics of each tiling variant of each characterization memory are stored in the memory timing database for the memory resource based on sets of input ramptimes and output loads.
摘要翻译：提供了一种用于创建和使用存储器定时数据库的方法和装置。定义了多个表征存储器，其可被映射到存储器资源。每个表征存储器具有不同的存储器参数。还定义了将每个表征存储器平铺到存储器资源的多种变型。每个表征存储器的每个平铺变体的时序特征基于输入夯实值和输出负载的集合存储在用于存储器资源的存储器定时数据库中。

18. 发明申请

US20070113212A1 Method and apparatus for mapping design memories to integrated circuit layout 失效
标题翻译：将设计存储器映射到集成电路布局的方法和装置
公开(公告)号：US20070113212A1
公开(公告)日：2007-05-17
申请号：US11280110
申请日：2005-11-16
申请人： Alexandre Andreev , Andrey Nikitin , Ilya Neznanov , Ranko Scepanovic
发明人： Alexandre Andreev , Andrey Nikitin , Ilya Neznanov , Ranko Scepanovic
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G11C5/025
摘要： A method and apparatus are provided for receiving a list of design memories, wherein each type of design memory in the list has a name and at least one instance. A pre-placement model is associated with each named memory type in the list. The design memories in the list are mapped to an integrated circuit layout pattern, wherein at least one memory type comprises first and second instances that are mapped differently from one another. After mapping, at least one of the first and second instances is renamed to have a different name than the other. A post-placement model is then associated with each named memory type in the list, including a separate model for each renamed design memory.
摘要翻译：提供了一种用于接收设计存储器列表的方法和装置，其中列表中的每种类型的设计存储器具有名称和至少一个实例。预置位模型与列表中的每个命名存储器类型相关联。列表中的设计存储器被映射到集成电路布局模式，其中至少一个存储器类型包括彼此不同地映射的第一和第二实例。映射后，第一个和第二个实例中的至少一个被重命名为具有与另一个不同的名称。然后，后置放置模型与列表中的每个命名存储器类型相关联，包括每个重命名的设计存储器的单独模型。

19. 发明申请

US20060104145A1 Memory tiling architecture 有权
标题翻译：记忆瓷砖结构
公开(公告)号：US20060104145A1
公开(公告)日：2006-05-18
申请号：US10990237
申请日：2004-11-16
申请人： Alexandre Andreev , Igor Vikhliantsev , Ivan Pavisic
发明人： Alexandre Andreev , Igor Vikhliantsev , Ivan Pavisic
IPC分类号： G11C8/00
CPC分类号： G06F17/5045
摘要： A method of tiling a customer memory design to configurable memory blocks within a standardized memory matrix. A customer memory capacity and a customer memory width is determined for the customer memory design, and a standardized memory capacity and a standardized memory width is determined for the configurable memory blocks. The customer memory capacity and the customer memory width are selectively transformed by inverse factors based at least in part on a comparison of the customer memory capacity and the standardized memory capacity. Case independent blocks are formed within the configurable memory blocks, where the case independent blocks include gate structures formed in a standardized array in a substrate in which the customer memory design is to be implemented. Case dependent blocks are formed within the configurable memory blocks, where the case dependent blocks are electrically conductive routing layers that selectively connect the case independent blocks according to the transformation of the customer memory design.
摘要翻译：将客户存储器设计平铺到标准化存储器矩阵内的可配置存储器块的方法。为客户存储器设计确定客户存储器容量和客户存储器宽度，并且为可配置存储器块确定标准化存储容量和标准化存储器宽度。至少部分地基于客户存储器容量与标准化存储器容量的比较，客户存储器容量和客户存储器宽度被反向因素选择性地变换。在可配置的存储器块内形成与箱体无关的块，其中与壳体无关的块包括形成在衬底中的标准化阵列中的栅极结构，其中将实现客户存储器设计。在可配置的存储器块内部形成与情况相关的块，其中与盒相关的块是根据客户存储器设计的变换选择性地连接不依赖于盒的块的导电路由层。

20. 发明授权

US08312072B2 Universal Galois field multiplier 有权
标题翻译：通用伽罗瓦域乘法器
公开(公告)号：US08312072B2
公开(公告)日：2012-11-13
申请号：US12211268
申请日：2008-09-16
申请人： Sergei B. Gashkov , Alexandre Andreev
发明人： Sergei B. Gashkov , Alexandre Andreev
IPC分类号： G06F7/72
CPC分类号： G06F7/724
摘要： An apparatus including a multiplier circuit and a multiplexing circuit. The multiplier circuit may be configured to multiply a first multiplicand and a second multiplicand based on a programmable base value and generate a plurality of intermediate values, each intermediate value representing a result of the multiplication reduced by a respective irreducible polynomial. The multiplexing circuit may be configured to generate an output in response to the plurality of intermediate values received from the multiplier circuit and the programmable base value.
摘要翻译：一种包括乘法器电路和复用电路的装置。乘法器电路可以被配置为基于可编程基值乘以第一被乘数和第二被乘数，并且生成多个中间值，每个中间值表示乘法的结果减去相应的不可约多项式。复用电路可以被配置为响应于从乘法器电路接收的多个中间值和可编程基值产生输出。

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