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11. 发明授权

US5760984A Cost reduced interpolated timing recovery in a sampled amplitude read channel 失效
标题翻译：采样幅度读通道中成本降低的插值定时恢复
公开(公告)号：US5760984A
公开(公告)日：1998-06-02
申请号：US546162
申请日：1995-10-20
申请人： Mark S. Spurbeck , Richard T. Behrens
发明人： Mark S. Spurbeck , Richard T. Behrens
IPC分类号： G11B5/09 , G11B20/10 , G11B20/12 , G11B20/14 , H04L7/02
CPC分类号： H04L7/0029 , G11B20/10009 , G11B20/10037 , G11B20/10055 , G11B20/10064 , G11B20/10074 , G11B20/1403 , G11B20/1258 , G11B2020/1234 , H04L2007/047
摘要： A sampled amplitude read channel reads information stored on a magnetic medium by detecting digital data from a sequence of discrete time interpolated sample values, the interpolated sample values generated by interpolating a sequence of discrete time channel sample values generated by sampling pulses in an analog read signal from a magnetic read head positioned over the magnetic medium. A write VFO generates a write clock for writing digital data to the magnetic medium at a predetermined baud rate for a selected zone, and upon read back, the write VFO generates a sampling clock at a frequency slightly higher than the write frequency. A sampling device samples the analog read signal at the sampling clock rate to generate a sequence of discrete time channel samples that are not synchronized to the baud rate, and the channel samples are equalized by a discrete time equalizing filter according to a predetermined partial response (PR4, EPR4, EEPR4, etc.). An interpolating timing recovery circuit, responsive to the equalized channel samples, computes an interpolation interval .tau. and, in response thereto, generates interpolated sample values substantially synchronized to the baud rate. The timing recovery circuit also generates a data clock for clocking a discrete time sequence detector which detects the digital data from the interpolated sample values. In a cost reduced implementation, the interpolation filter coefficients are computed in real time as a function of the interpolation interval .tau..
摘要翻译：采样幅度读取通道通过从离散时间内插采样值序列中检测数字数据来读取存储在磁性介质上的信息，内插采样值是通过内插由模拟读取信号中的采样脉冲产生的离散时间通道采样值序列而产生的从位于磁介质上的磁读头。写入VFO产生写入时钟，用于以预定的波特率为所选区域将数字数据写入磁介质，并且在读回时，写入VFO以略高于写入频率的频率产生采样时钟。采样装置以采样时钟速率对模拟读取信号进行采样，以产生不与波特率同步的离散时间信道采样序列，并且通过离散时间均衡滤波器根据预定的部分响应（ PR4，EPR4，EEPR4等）。内插定时恢复电路响应于均衡信道采样，计算内插间隔τ，并且响应于此产生基本上与波特率同步的内插采样值。定时恢复电路还产生数据时钟，用于计时离散时间序列检测器，其从插值的采样值检测数字数据。在成本降低的实现中，内插滤波器系数作为内插间隔τ的函数被实时计算。

12. 发明授权

US5696639A Sampled amplitude read channel employing interpolated timing recovery 失效
标题翻译：采用内插时序恢复的采样幅度读取通道
公开(公告)号：US5696639A
公开(公告)日：1997-12-09
申请号：US440508
申请日：1995-05-12
申请人： Mark S. Spurbeck , Richard T. Behrens , German S. Feyh
发明人： Mark S. Spurbeck , Richard T. Behrens , German S. Feyh
IPC分类号： G11B20/10 , G11B20/12 , G11B20/14 , H04L7/02 , H04L7/04 , C11B5/09
CPC分类号： G11B20/10009 , G11B20/10037 , G11B20/10055 , G11B20/1403 , H04L7/0029 , G11B20/1258 , H04L2007/047 , H04L7/04
摘要： A sampled amplitude read channel for reading information stored on a magnetic medium by detecting digital data from a sequence of discrete time interpolated sample values, the interpolated sample values generated by interpolating a sequence of discrete time channel sample values generated by sampling pulses in an analog read signal from a magnetic read head positioned over the magnetic medium. A write VFO generates a write clock for writing digital data to the magnetic medium at a predetermined baud rate for a selected zone, and upon read back, the write VFO generates a sampling clock at a frequency slightly higher than the write frequency. A sampling device samples the analog read signal at the sampling clock rate to generate a sequence of discrete time channel samples that are not synchronized to the baud rate. The channel samples are equalized by a discrete time equalizing filter according to a predetermined partial response (PR4, EPR4, EEPR4, etc.). An interpolating timing recovery circuit, responsive to the equalized channel samples, computes an interpolation interval .tau. and, in response thereto, generates interpolated sample values substantially synchronized to the baud rate. The timing recovery circuit also generates a data clock for clocking a discrete time sequence detector for detecting the digital data from the interpolated sample values.
摘要翻译：一种采样振幅读通道，用于通过从离散时间内插样本值序列中检测数字数据来读取存储在磁介质上的信息，该内插样本值是通过内插由模拟读取中的采样脉冲产生的离散时间通道采样值序列而产生的来自位于磁介质上的磁读头的信号。写入VFO产生写入时钟，用于以预定的波特率为所选区域将数字数据写入磁介质，并且在读回时，写入VFO以略高于写入频率的频率产生采样时钟。采样设备以采样时钟速率对模拟读取信号进行采样，以产生不与波特率同步的离散时间通道采样序列。信道样本根据预定的部分响应（PR4，EPR4，EEPR4等）由离散时间均衡滤波器进行均衡。内插定时恢复电路响应于均衡信道采样，计算内插间隔τ，并且响应于此产生基本上与波特率同步的内插采样值。定时恢复电路还产生用于对离散时间序列检测器进行计时的数据时钟，用于从内插样本值检测数字数据。

13. 发明授权

US5297184A Gain control circuit for synchronous waveform sampling 失效
标题翻译：用于同步波形采样的增益控制电路
公开(公告)号：US5297184A
公开(公告)日：1994-03-22
申请号：US12049
申请日：1993-02-01
申请人： Richard T. Behrens , Trent Dudley , Neal Glover
发明人： Richard T. Behrens , Trent Dudley , Neal Glover
IPC分类号： G11B5/09 , G11B20/10 , H03G3/20 , H04L27/08
CPC分类号： H03G3/001 , G11B20/10009 , H03G3/3036
摘要： A mixed analog and digital gain control circuit for controlling the amplitude of an analog input signal. The circuit has a variable gain amplifier that receives the signal from a read/write recording head preamplifier. The output of the variable gain amplifier is connected through a multiplexer and equalizer to an analog to digital converter for converting the analog signal to digital sample values at controlled sampling times. A gain control circuit receives the digital values and the output of a pulse detector indicating when a pulse has occurred. A gain error detector within the gain control circuit determines the amount of error in the amplitude of each detected pulse, and this error amount is filtered and sent through a digital to analog converter and then through an exponentiating circuit. The output of the exponentiating circuit is connected to a gain control input of the variable gain amplifier.
摘要翻译：一种混合的模拟和数字增益控制电路，用于控制模拟输入信号的幅度。该电路具有可变增益放大器，其接收来自读/写记录头前置放大器的信号。可变增益放大器的输出通过多路复用器和均衡器连接到模数转换器，用于在受控采样时将模拟信号转换为数字采样值。增益控制电路接收指示何时发生脉冲的数字值和脉冲检测器的输出。增益控制电路内的增益误差检测器确定每个检测脉冲幅度的误差量，并将该误差量滤波并通过数模转换器发送，然后通过取幂电路。指数电路的输出连接到可变增益放大器的增益控制输入。

14. 发明授权

US08224259B2 Digital architecture for radio-frequency apparatus and associated methods 有权
标题翻译：射频设备数字架构及相关方法
公开(公告)号：US08224259B2
公开(公告)日：2012-07-17
申请号：US12715361
申请日：2010-03-01
申请人： Richard T. Behrens , Tod Paulus , Mark S. Spurbeck , Vishnu S. Srinivasan , Donald A. Kerth , Jeffrey W. Scott , G. Tyson Tuttle , G. Diwakar Vishakhadatta
发明人： Richard T. Behrens , Tod Paulus , Mark S. Spurbeck , Vishnu S. Srinivasan , Donald A. Kerth , Jeffrey W. Scott , G. Tyson Tuttle , G. Diwakar Vishakhadatta
IPC分类号： H04B1/38 , H04W24/00
CPC分类号： H04B1/28 , H04B1/0003 , H04B1/38 , H04B1/406 , H04B15/02 , H04B15/04 , H04B2215/064
摘要： A radio-frequency (RF) receiver includes a receiver analog circuitry and a receiver digital circuitry. The receiver analog circuitry resides within a first integrated circuit and the receiver digital circuitry resides within a second integrated circuit. The second integrated circuit couples to the first integrated circuit via a one-bit digital interface. The receiver analog circuitry receives an RF signal and processes the received RF signal to generate a digital signal. The receiver analog circuitry provides the digital signal to the receiver digital circuitry. The receiver digital circuitry includes a digital down-converter circuitry that mixes the digital signal with an intermediate frequency (IF) local oscillator (LO) signal to generate a digital down-converted signal. The receiver digital circuitry also includes a digital filter circuitry that filters the digital down-converted signal to generate a filtered digital signal.
摘要翻译：射频（RF）接收机包括接收机模拟电路和接收机数字电路。接收器模拟电路驻留在第一集成电路内，并且接收器数字电路位于第二集成电路内。第二集成电路通过一位数字接口耦合到第一集成电路。接收机模拟电路接收RF信号并处理所接收的RF信号以产生数字信号。接收机模拟电路将数字信号提供给接收机数字电路。接收机数字电路包括数字下变频器电路，其将数字信号与中频（IF）本地振荡器（LO）信号混合以产生数字下变频信号。接收机数字电路还包括数字滤波器电路，其对数字下变频信号进行滤波以产生经滤波的数字信号。

15. 发明申请

US20080285549A1 SYNCHRONOUS READ CHANNEL 失效
标题翻译：同步读通道
公开(公告)号：US20080285549A1
公开(公告)日：2008-11-20
申请号：US12126188
申请日：2008-05-23
申请人： Richard T. Behrens , Kent D. Anderson , Alan J. Armstrong , Trent Dudley , Bill R. Foland , Neal Glover , Larry D. King
发明人： Richard T. Behrens , Kent D. Anderson , Alan J. Armstrong , Trent Dudley , Bill R. Foland , Neal Glover , Larry D. King
IPC分类号： H04L12/50
CPC分类号： G11B20/10055 , G11B5/012 , G11B5/09 , G11B20/10 , G11B20/10009 , G11B20/1258 , G11B20/1403 , G11B20/1426 , G11B20/18 , G11B27/3027 , G11B2020/1476 , H03M13/31
摘要： A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(1,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, together with the error-tolerant sync mark detection and the ability to recover data when the sync mark is obliterated, allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery. Various embodiments, including an embodiment incorporating the analog functions as well as the primary digital functions of the read channel in a single integrated circuit, and preferred embodiments utilizing a reduced complexity, programmable modified Viterbi detector supporting a broad class of partial response channels are disclosed.
摘要翻译：公开了具有提供数字增益控制，定时恢复，均衡，数字峰值检测，序列检测，RLL（1,7）编码和解码，容错同步和信道质量测量的单芯片集成电路数字部分的同步读通道。集成电路既适用于中心采样和侧采样，又具有各种脉冲整形和恢复参数的高度可编程性，以及使用序列检测或数字峰值检测提供解码数据的能力。这些特征以及容错同步标记检测以及当同步标记被消除时恢复数据的能力允许各种各样的重试和恢复策略以最大化数据恢复的可能性。公开了包括在单个集成电路中并入模拟功能以及读取通道的主要数字功能的实施例的各种实施例，以及利用支持大类部分响应通道的降低复杂度的可编程修改维特比检测器的优选实施例。

16. 发明授权

US07242912B2 Partitioning of radio-frequency apparatus 有权
标题翻译：射频设备分区
公开(公告)号：US07242912B2
公开(公告)日：2007-07-10
申请号：US10631166
申请日：2003-07-31
申请人： James Maligeorgos , Augusto M. Marques , Lysander Lim , G. Tyson Tuttle , Aslamali A. Rafi , Tod Paulus , Gregory T. Uehara , Jeffrey W. Scott , Richard T. Behrens , Donald A. Kerth , G. Diwakar Vishakhadatta , Vishnu S. Srinivasan , Caiyi Wang
发明人： James Maligeorgos , Augusto M. Marques , Lysander Lim , G. Tyson Tuttle , Aslamali A. Rafi , Tod Paulus , Gregory T. Uehara , Jeffrey W. Scott , Richard T. Behrens , Donald A. Kerth , G. Diwakar Vishakhadatta , Vishnu S. Srinivasan , Caiyi Wang
IPC分类号： H04B1/40
CPC分类号： H04B1/0003 , H03L7/085 , H03L7/087 , H03L7/091 , H03L7/099 , H03L7/187 , H03L7/199 , H03L7/23 , H04B1/28 , H04B1/406 , H04B15/02 , H04B15/04 , H04B2215/064
摘要： Components of a radio-frequency (RF) apparatus including transceiver circuitry and frequency modification circuitry of a crystal oscillator circuit that generates a reference signal with adjustable frequency may be partitioned in a variety of ways, for example, as one or more separate integrated circuits. The frequency modification circuitry may be implemented as part of a crystal oscillator circuit that includes digitally controlled crystal oscillator (“DCXO”) circuitry and a crystal. The frequency modification circuitry may include at least one variable capacitance device and may be employed to generate a reference signal with adjustable frequency. The adjustable reference signal may be provided to other components of the RF apparatus and/or the RF apparatus may be configured to provide the adjustable reference signal to baseband processor circuitry. Automatic frequency control (AFC) circuitry may be integrated with other components of RF circuitry and may generate frequency control signals for the frequency modification circuitry based on, for example, a signal received from a temperature sensor. Digital-to-analog converter (DAC) circuitry may be integrated with other components of RF circuitry to enable all-digital frequency control communications from baseband processor circuitry to RF circuitry.
摘要翻译：包括生成具有可变频率的参考信号的晶体振荡器电路的收发器电路和频率修改电路的射频（RF）设备的组件可以以各种方式被划分，例如作为一个或多个单独的集成电路。频率修改电路可以被实现为包括数字控制的晶体振荡器（“DCXO”）电路和晶体的晶体振荡器电路的一部分。频率修改电路可以包括至少一个可变电容器件，并且可以用于产生具有可调频率的参考信号。可调参考信号可以被提供给RF装置的其他部件，和/或RF装置可以被配置为向基带处理器电路提供可调参考信号。自动频率控制（AFC）电路可以与RF电路的其它组件集成，并且可以基于例如从温度传感器接收的信号来生成用于频率修改电路的频率控制信号。数模转换器（DAC）电路可以与RF电路的其他部件集成，以实现从基带处理器电路到RF电路的全数字频率控制通信。

17. 发明授权

US07138858B2 Apparatus and methods for output buffer circuitry with constant output power in radio-frequency circuitry 失效
公开(公告)号：US07138858B2
公开(公告)日：2006-11-21
申请号：US10079058
申请日：2002-02-19
申请人： Augusto M. Marques , Donald A. Kerth , Richard T. Behrens , Jeffrey W. Scott , G. Diwakar Vishakhadatta , G. Tyson Tuttle , Vishnu S. Srinivasan
发明人： Augusto M. Marques , Donald A. Kerth , Richard T. Behrens , Jeffrey W. Scott , G. Diwakar Vishakhadatta , G. Tyson Tuttle , Vishnu S. Srinivasan
IPC分类号： G01R19/00 , H03F3/38
CPC分类号： H04B1/0003 , H04B1/28 , H04B1/406 , H04B15/02 , H04B15/04 , H04B2215/064
摘要： A buffer circuitry buffers a radio-frequency (RF) signal. The buffer circuitry includes a complementary pair of switches and a power source. The a complementary pair of switches has an input terminal and output terminal. The input terminal of the complementary pair of switches responds to the RF signal. The output terminal of the complementary pair of switches couples to an output of the buffer circuitry. The power source includes a capacitor coupled to a current source. The power source couples to the complementary pair of switches. The power source supplies power to the complementary pair of switches in a manner that the buffer circuitry supplies a substantially constant power level at its output.

18. 发明授权

US07092675B2 Apparatus and methods for generating radio frequencies in communication circuitry using multiple control signals 有权
标题翻译：在使用多个控制信号的通信电路中产生无线电频率的设备和方法
公开(公告)号：US07092675B2
公开(公告)日：2006-08-15
申请号：US10075098
申请日：2002-02-13
申请人： Lysander Lim , Caiyi Wang , David R. Welland , Donald A. Kerth , Richard T. Behrens , Jeffrey W. Scott , G. Diwakar Vishakhadatta , G. Tyson Tuttle , Vishnu S. Srinivasan
发明人： Lysander Lim , Caiyi Wang , David R. Welland , Donald A. Kerth , Richard T. Behrens , Jeffrey W. Scott , G. Diwakar Vishakhadatta , G. Tyson Tuttle , Vishnu S. Srinivasan
IPC分类号： H04B1/40
CPC分类号： H03L7/085 , H03L7/087 , H03L7/091 , H03L7/099 , H03L7/187 , H03L7/199 , H03L7/23 , H04B1/0003 , H04B1/28 , H04B1/406 , H04B15/02 , H04B15/04 , H04B2215/064
摘要： A radio-frequency (RF) apparatus capable of transmitting RF signals includes transmitter path circuitry. The transmitter path circuitry includes a voltage-controlled oscillator (VCO) that generates an output signal. The frequency of the output signal of the VCO circuitry is adjustable in response to a first control signal and a second control signal. The transmitter path circuitry also includes a first feedback circuitry and a second feedback circuitry that are responsive to the output signal of the VCO circuitry. The first feedback circuitry provides the first control signal to the VCO circuitry. The first control signal coarsely adjusts the frequency of the output signal of the VCO circuitry to a desired frequency. The second feedback circuitry supplies the second control signal to the VCO circuitry. The second control signal fine tunes the frequency of the output signal of the voltage-controlled oscillator circuitry to the desired frequency.
摘要翻译：能够发送RF信号的射频（RF）装置包括发射机路径电路。发射机路径电路包括产生输出信号的压控振荡器（VCO）。 VCO电路的输出信号的频率可响应于第一控制信号和第二控制信号而调节。发射机路径电路还包括响应于VCO电路的输出信号的第一反馈电路和第二反馈电路。第一反馈电路向VCO电路提供第一控制信号。第一控制信号粗略地将VCO电路的输出信号的频率调整到期望的频率。第二反馈电路将第二控制信号提供给VCO电路。第二控制信号将压控振荡器电路的输出信号的频率调谐到期望的频率。

19. 发明授权

US07035611B2 Apparatus and method for front-end circuitry in radio-frequency apparatus 有权
公开(公告)号：US07035611B2
公开(公告)日：2006-04-25
申请号：US10079057
申请日：2002-02-19
申请人： Eric R. Garlepp , Donald A. Kerth , Richard T. Behrens , Jeffrey W. Scott , G. Diwakar Vishakhadatta , G. Tyson Tuttle , Vishnu S. Srinivasan
发明人： Eric R. Garlepp , Donald A. Kerth , Richard T. Behrens , Jeffrey W. Scott , G. Diwakar Vishakhadatta , G. Tyson Tuttle , Vishnu S. Srinivasan
IPC分类号： H04B1/06
CPC分类号： H04B1/0003 , H04B1/28 , H04B1/406 , H04B15/02 , H04B15/04 , H04B2215/064
摘要： A radio-frequency (RF) apparatus includes front-end circuitry. The front-end circuitry includes a filter circuitry and an impedance matching circuitry. The filter circuitry has a differential output that has an output impedance. The filter circuitry filters signals outside a signal band of interest. The impedance matching network has a differential input coupled to the output of the filter circuitry. The impedance matching network also has a differential output coupled to a signal processing circuitry. The signal processing circuitry has an input impedance. The impedance matching network matches the input impedance of the signal processing circuitry to the output impedance of the filter circuitry.

20. 发明授权

US07031683B2 Apparatus and methods for calibrating signal-processing circuitry 有权
公开(公告)号：US07031683B2
公开(公告)日：2006-04-18
申请号：US10083633
申请日：2002-02-26
申请人： G. Diwakar Vishakhadatta , Donald A. Kerth , Russell Croman , Jeffrey W. Scott , Richard T. Behrens , G. Tyson Tuttle , Vishnu S. Srinivasan
发明人： G. Diwakar Vishakhadatta , Donald A. Kerth , Russell Croman , Jeffrey W. Scott , Richard T. Behrens , G. Tyson Tuttle , Vishnu S. Srinivasan
IPC分类号： H04B1/26
CPC分类号： H04B1/0003 , H04B1/28 , H04B1/406 , H04B15/02 , H04B15/04 , H04B2215/064
摘要： A calibration circuitry includes an adjustable capacitor, a voltage generator, a reference voltage generator, and a controller. The reference voltage generator provides a reference voltage. The voltage generator provides a measurement voltage that depends on the capacitance of the adjustable capacitor. The capacitance of the adjustable capacitor varies in response to a control signal. The controller provides the control signal based on the relative values of the reference voltage and the measurement voltage.

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