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11. 发明授权

US09225304B1 Single-stage folded cascode buffer amplifiers with analog comparators 有权
标题翻译：具有模拟比较器的单级折叠共源共栅放大器
公开(公告)号：US09225304B1
公开(公告)日：2015-12-29
申请号：US14522678
申请日：2014-10-24
申请人： SanDisk 3D LLC
发明人： Vincent Lai
IPC分类号： H03F3/45 , H03F1/30
CPC分类号： H03F1/308 , G11C11/5642 , G11C27/005 , H03F3/3022 , H03F3/45183 , H03F3/45219 , H03F2200/45 , H03F2200/78 , H03F2203/30096 , H03F2203/30129 , H03F2203/45116
摘要： A single-stage folded cascode buffer including an amplifier, a first analog comparator, a second analog comparator, a first transistor, and a second transistor, The amplifier includes a first input terminal, a second input terminal, and an output terminal coupled to the second input terminal of the amplifier. The first analog comparator includes a first input terminal, a second input terminal, and an output terminal. The second analog comparator includes a first input terminal, a second input terminal, and an output terminal. The first transistor includes a first terminal, a second terminal coupled to the output terminal of the first analog comparator, and a third terminal coupled to the output terminal of the amplifier. The second transistor includes a first terminal coupled to the output terminal of the amplifier, a second terminal coupled to the output terminal of the second analog comparator, and a third terminal.
摘要翻译：包括放大器，第一模拟比较器，第二模拟比较器，第一晶体管和第二晶体管的单级折叠共源共栅缓冲器。放大器包括第一输入端子，第二输入端子和耦合到第二晶体管的输出端子放大器的第二输入端。第一模拟比较器包括第一输入端，第二输入端和输出端。第二模拟比较器包括第一输入端，第二输入端和输出端。第一晶体管包括第一端子，耦合到第一模拟比较器的输出端子的第二端子和耦合到放大器的输出端子的第三端子。第二晶体管包括耦合到放大器的输出端的第一端子，耦合到第二模拟比较器的输出端的第二端子和第三端子。

12. 发明授权

US09202566B2 Vertical cross point reram forming method 有权
标题翻译：垂直交叉点形成方法
公开(公告)号：US09202566B2
公开(公告)日：2015-12-01
申请号：US14246052
申请日：2014-04-05
申请人： SanDisk 3D LLC
发明人： Chang Siau , Tianhong Yan
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0097 , G11C2213/71 , G11C2213/77
摘要： Methods for forming non-volatile storage elements in a non-volatile storage system are described. In some embodiments, a plurality of forming operations may be performed in which non-volatile storage elements located near the far end of a plurality of word line fingers associated with a word line comb are formed prior to forming other non-volatile storage elements. In one example, non-volatile storage elements may be formed in each of the plurality of word line fingers in parallel and in an order that forms non-volatile storage elements in each of the plurality of word line fingers that are located near the far ends of the plurality of word line fingers before forming other non-volatile storage elements. Each non-volatile storage element that is formed during a forming operation may be current limited while a forming voltage is applied across the non-volatile storage element.
摘要翻译：描述了在非易失性存储系统中形成非易失性存储元件的方法。在一些实施例中，可以执行多个形成操作，其中在形成其他非易失性存储元件之前形成位于与字线梳相关联的多个字线手指的远端附近的非易失性存储元件。在一个示例中，非易失性存储元件可以并行地形成在多个字线手指中的每一个中，并且以在多个字线手指中的远端附近形成非易失性存储元件的顺序在形成其他非易失性存储元件之前的多个字线指。在成形操作期间形成的每个非易失性存储元件可以是电流限制的，同时在非易失性存储元件上施加形成电压。

13. 发明申请

US20150333105A1 Resistance-Switching Memory Cell With Multiple Raised Structures In A Bottom Electrode 有权
标题翻译：在底部电极中具有多个凸起结构的电阻切换存储单元
公开(公告)号：US20150333105A1
公开(公告)日：2015-11-19
申请号：US14807370
申请日：2015-07-23
申请人： SanDisk 3D LLC
发明人： George Matamis , James K. Kai , Vinod R. Purayath , Yuan Zhang , Henry Chien
IPC分类号： H01L27/24 , H01L45/00
CPC分类号： H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/1273 , H01L45/144 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/149 , H01L45/16 , H01L45/1675
摘要： A reversible resistance-switching memory cell has multiple narrow, spaced apart bottom electrode structures. The raised structures can be formed by coating a bottom electrode layer with nano-particles and etching the bottom electrode layer. The raised structures can be independent or joined to one another at a bottom of the bottom electrode layer. A resistance-switching material is provided between and above the bottom electrode structure, followed by a top electrode layer. Or, insulation is provided between and above the bottom electrode structures, and the resistance-switching material and top electrode layer are above the insulation. Less than one-third of a cross-sectional area of each resistance-switching memory cell is consumed by the one or more raised structures. When the resistance state of the memory cell is switched, there is a smaller area in the bottom electrode for a current path, so the switching resistance is higher and the switching current is lower.
摘要翻译：可逆电阻切换存储单元具有多个窄间隔开的底部电极结构。凸起结构可以通过用纳米颗粒涂覆底部电极层并蚀刻底部电极层来形成。凸起结构可以在底部电极层的底部是独立的或彼此连接的。电阻切换材料设置在底部电极结构之间和之上，随后是顶部电极层。或者，在底部电极结构之间和之上提供绝缘，并且电阻切换材料和顶部电极层在绝缘体之上。每个电阻切换存储单元的横截面积的不到三分之一被一个或多个凸起结构所消耗。当切换存储单元的电阻状态时，电流路径的底部电极的面积越小，开关电阻越高，开关电流越低。

14. 发明授权

US09190134B2 Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a single-sided word line architecture 有权
标题翻译：具有垂直位线和单面字线结构的可重新编程的非易失性存储元件的三维阵列
公开(公告)号：US09190134B2
公开(公告)日：2015-11-17
申请号：US14153794
申请日：2014-01-13
申请人： SanDisk 3D LLC
发明人： George Samachisa
IPC分类号： G11C11/00 , G11C11/06 , B82Y10/00 , G11C11/56 , G11C13/00 , G11C13/02 , H01L27/24 , G11C16/10 , H01L45/00
CPC分类号： G11C13/0007 , B82Y10/00 , G11C11/06035 , G11C11/5614 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0011 , G11C13/003 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C13/025 , G11C16/10 , G11C2013/0045 , G11C2013/0088 , G11C2213/19 , G11C2213/32 , G11C2213/34 , G11C2213/55 , G11C2213/71 , G11C2213/75 , G11C2213/78 , H01L23/528 , H01L27/2409 , H01L27/2436 , H01L27/2481 , H01L27/249 , H01L45/06 , H01L45/065 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/1233 , H01L45/1253 , H01L45/1266 , H01L45/142 , H01L45/143 , H01L45/146 , H01L45/148 , H01L45/149
摘要： A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. A single-sided word line architecture provides a word line exclusively for each row of memory elements instead of sharing one word line between two rows of memory elements thereby avoids linking the memory element across the array across the word lines. While the row of memory elements is also being accessed by a corresponding row of local bit lines, there is no extension of coupling between adjacent rows of local bit lines and therefore leakage currents beyond the word line.
摘要翻译：特别适用于响应于在其上施加电压差而可逆地改变电导水平的存储元件的三维阵列。存储元件跨越位于半导体衬底上方不同距离的多个平面形成。所有平面的存储元件连接到的位线的二维阵列从衬底垂直定向并穿过多个平面。单面字线架构为每行存储器元件专门提供字线，而不是在两行存储器元件之间共享一个字线，从而避免跨越字线跨越阵列链接存储元件。虽然存储器元件行也被对应的局部位线行访问，但是在局部位线的相邻行之间没有扩展耦合，因此没有扩展超出字线的漏电流。

15. 发明授权

US09184383B2 Nonvolatile memory device having an electrode interface coupling region 有权
标题翻译：具有电极接口耦合区域的非易失性存储器件
公开(公告)号：US09184383B2
公开(公告)日：2015-11-10
申请号：US14156762
申请日：2014-01-16
申请人： Intermolecular Inc. , Kabushiki Kaisha Toshiba , SanDisk 3D LLC
发明人： Yun Wang , Tony P. Chiang , Imran Hashim
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L45/1608 , H01L27/2409 , H01L27/2436 , H01L27/2463 , H01L45/065 , H01L45/08 , H01L45/10 , H01L45/12 , H01L45/1226 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146 , H01L45/1616 , H01L45/1625
摘要： Embodiments of the invention generally relate to a resistive switching nonvolatile memory device having an interface layer structure disposed between at least one of the electrodes and a variable resistance layer formed in the nonvolatile memory device, and a method of forming the same. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players. In one configuration of the resistive switching nonvolatile memory device, the interface layer structure comprises a passivation region, an interface coupling region, and/or a variable resistance layer interface region that are configured to adjust the nonvolatile memory device's performance, such as lowering the formed device's switching currents and reducing the device's forming voltage, and reducing the performance variation from one formed device to another.
摘要翻译：本发明的实施例一般涉及具有设置在至少一个电极和形成在非易失性存储器件中的可变电阻层之间的界面层结构的电阻式开关非易失性存储器件及其形成方法。通常，电阻式开关存储器元件可以形成为可用于各种电子设备（例如数码相机，移动电话，手持式计算机和音乐播放器）的大容量非易失性存储器集成电路的一部分。在电阻式开关非易失性存储器件的一种结构中，界面层结构包括钝化区域，界面耦合区域和/或可变电阻层接口区域，其被配置为调整非易失性存储器件的性能，例如降低形成器件的开关电流并降低器件的成型电压，并降低从一个成形器件到另一个器件的性能变化。

16. 发明授权

US09178148B2 Resistive random access memory cell having three or more resistive states 有权
公开(公告)号：US09178148B2
公开(公告)日：2015-11-03
申请号：US14636421
申请日：2015-03-03
申请人： Intermolecular Inc. , Kabushiki Kaisha Toshiba , SanDisk 3D LLC
发明人： Imran Hashim , Ryan C. Clarke , Nan Lu , Tim Minvielle , Takeshi Yamaguchi
IPC分类号： H01L45/00 , G11C13/00 , G11C11/56
CPC分类号： H01L45/146 , G11C11/56 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C13/0097 , G11C2213/32 , G11C2213/71 , G11C2213/77 , H01L45/08 , H01L45/1233 , H01L45/1253
摘要： Provided are resistive random access memory (ReRAM) cells, each having three or more resistive states and being capable of storing multiple bits of data, as well as methods of fabricating and operating such ReRAM cells. Such ReRAM cells or, more specifically, their resistive switching layer have wide range of resistive states and are capable of being very conductive (e.g., about 1 kOhm) in one state and very resistive (e.g., about 1 MOhm) in another state. In some embodiments, a resistance ratio between resistive states may be between 10 and 1,000 even up to 10,000. The resistive switching layers also allow establishing stable and distinct intermediate resistive states that may be assigned different data values. These layers may be configured to switching between their resistive states using fewer programming pulses than conventional systems by using specific materials, switching pluses, and resistive state threshold.

17. 发明授权

US09178000B1 Resistive random access memory cells having shared electrodes with transistor devices 有权
标题翻译：具有与晶体管器件共享的电极的电阻式随机存取存储器单元
公开(公告)号：US09178000B1
公开(公告)日：2015-11-03
申请号：US14264280
申请日：2014-04-29
申请人： Intermolecular Inc. , Kabushiki Kaisha Toshiba , SanDisk 3D LLC
发明人： Federico Nardi , Ryan C. Clarke , Tim Minvielle , Yun Wang
IPC分类号： H01L29/02 , H01L29/792 , H01L27/11 , H01L21/00 , H01L27/24 , H01L45/00 , H01L29/08 , H01L21/265 , H01L21/02
CPC分类号： H01L27/2463 , H01L21/02532 , H01L21/02595 , H01L21/265 , H01L27/2436 , H01L29/0847 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/1608 , H01L45/1616 , H01L45/1625
摘要： Provided are resistive random access memory (ReRAM) cells having extended conductive layers operable as electrodes of other devices, and methods of fabricating such cells and other devices. A conductive layer of a ReRAM cell extends beyond the cell boundary defined by the variable resistance layer. The extended portion may be used a source or drain region of a FET that may control an electrical current through the cell or other devices. The extended conductive layer may be also operable as electrode of another resistive-switching cell or a different device. The extended conductive layer may be formed from doped silicon. The variable resistance layer of the ReRAM cell may be positioned on the same level as a gate dielectric layer of the FET. The variable resistance layer and the gate dielectric layer may have the same thickness and share common materials, though they may be differently doped.
摘要翻译：提供了具有可操作为其他器件的电极的延伸导电层的电阻随机存取存储器（ReRAM）单元，以及制造这样的单元和其它器件的方法。 ReRAM单元的导电层延伸超过由可变电阻层限定的单元边界。延伸部分可以用于可控制通过电池或其他装置的电流的FET的源极或漏极区域。扩展导电层也可以作为另一电阻式开关电池或不同器件的电极工作。延伸的导电层可以由掺杂的硅形成。 ReRAM单元的可变电阻层可以位于与FET的栅极电介质层相同的水平上。可变电阻层和栅极电介质层可以具有相同的厚度并且共享共同的材料，尽管它们可以是不同的掺杂。

18. 发明授权

US09165933B2 Vertical bit line TFT decoder for high voltage operation 有权
标题翻译：垂直位线TFT解码器，用于高压操作
公开(公告)号：US09165933B2
公开(公告)日：2015-10-20
申请号：US13788990
申请日：2013-03-07
申请人： SanDisk 3D LLC
发明人： Peter Rabkin , Masaaki Higashitani
IPC分类号： H01L27/105 , H01L27/24 , H01L27/115 , G11C13/00 , H01L45/00
CPC分类号： H01L27/1052 , G11C13/0002 , G11C13/0026 , G11C13/004 , G11C13/0069 , G11C2213/71 , H01L27/11551 , H01L27/11578 , H01L27/2454 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/08 , H01L45/1226 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/149 , H01L45/16
摘要： A 3D memory array having a vertically oriented thin film transistor (TFT) selection device that has a channel extension, otherwise referred to as a gate/junction offset, is disclosed. The vertically oriented TFT selection device with channel extension serves as a vertical bit line selection device in the 3D memory array. A vertical TFT select device having a channel extension has a high breakdown voltage and low leakage current. The channel extension can be at the top junction or bottom junction of the TFT. Depending on whether the memory elements undergo a forward FORM or reverse FORM, either the bottom or top junction can have the channel extension. This provides for a high voltage junction where needed.
摘要翻译：公开了一种具有垂直取向的薄膜晶体管（TFT）选择装置的3D存储器阵列，其具有通道延伸，否则称为栅极/结偏移。具有通道扩展的垂直取向的TFT选择装置用作3D存储器阵列中的垂直位线选择装置。具有通道延伸的垂直TFT选择装置具有高击穿电压和低漏电流。沟道延伸可以在TFT的顶部结或底部结。取决于存储器元件是经历正向FORM还是反向FORM，底部或顶部结可以具有通道扩展。这在需要时提供了高压接点。

19. 发明申请

US20150279850A1 TRANSISTOR DEVICE WITH GATE BOTTOM ISOLATION AND METHOD OF MAKING THEREOF 有权
标题翻译：具有门底分离的晶体管器件及其制造方法
公开(公告)号：US20150279850A1
公开(公告)日：2015-10-01
申请号：US14224290
申请日：2014-03-25
申请人： SanDisk 3D LLC
发明人： Seje Takaki
IPC分类号： H01L27/115 , H01L29/66 , H01L45/00
CPC分类号： H01L27/11524 , G11C13/0002 , G11C2213/71 , G11C2213/77 , G11C2213/78 , G11C2213/79 , H01L27/101 , H01L27/11556 , H01L27/11582 , H01L27/2454 , H01L27/249 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926 , H01L45/04 , H01L45/1226 , H01L45/146 , H01L45/16
摘要： An embodiment relates to a transistor device including a pillar of semiconductor material extending vertically from a bottom portion in contact with an electrically conductive contact line, where the electrically conductive contact line extends laterally past the pillar in a horizontal direction, a gate insulating liner layer on a lateral side of the pillar, a gate electrode on the gate insulating layer extending along the lateral side of the pillar, and a region of electrically insulating semiconductor oxide material filling a space between a bottom portion of the gate electrode and a top portion of the electrically conductive contact line.
摘要翻译：一个实施例涉及一种晶体管器件，其包括半导体材料柱，其从与导电接触线接触的底部垂直延伸，其中导电接触线在水平方向上横向延伸穿过柱，栅极绝缘衬垫层所述柱的横向侧，所述栅极绝缘层上沿着所述柱的横向侧延伸的栅电极以及填充所述栅电极的底部与所述栅电极的顶部之间的空间的电绝缘半导体氧化物材料的区域导电接触线。

20. 发明申请

US20150263074A1 TRANSISTOR DEVICE AND METHOD OF MAKING THEREOF 有权
标题翻译：晶体管器件及其制造方法
公开(公告)号：US20150263074A1
公开(公告)日：2015-09-17
申请号：US14206196
申请日：2014-03-12
申请人： SanDisk 3D LLC
发明人： Seje Takaki
IPC分类号： H01L27/24 , H01L29/66 , H01L29/51 , H01L27/115 , H01L21/28 , H01L29/16 , H01L29/04 , H01L21/324 , H01L21/225 , H01L29/49 , H01L29/78 , H01L29/45
CPC分类号： H01L27/2481 , H01L27/11273 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582 , H01L27/2454 , H01L27/249 , H01L29/1033 , H01L29/42356 , H01L29/4925 , H01L29/4983 , H01L29/66666 , H01L29/7827 , H01L29/7889 , H01L29/7926 , H01L45/04 , H01L45/1226 , H01L45/146
摘要： A device is disclosed including one or more field effect transistors, each field effect transistor including: an elongated drain contact line including an electrically conductive material extending along a first horizontal direction; a drain including a first conductivity type semiconductor region overlaying the drain contact line; a source including a the first conductivity type semiconductor region located above the drain; and a gate extending vertically between the drain and the source. Each field effect transistor may include a first channel and a second channel, each including a second conductivity type
摘要翻译：公开了一种包括一个或多个场效应晶体管的器件，每个场效应晶体管包括：细长的漏极接触线，包括沿着第一水平方向延伸的导电材料; 漏极，包括覆盖所述漏极接触线的第一导电类型半导体区域; 源极，包括位于漏极上方的第一导电类型半导体区域; 以及在漏极和源极之间垂直延伸的栅极。每个场效应晶体管可以包括第一通道和第二通道，每个通道包括第二导电类型

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