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21. 发明申请

US20050218441A1 Semiconductor device and method of fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050218441A1
公开(公告)日：2005-10-06
申请号：US11092900
申请日：2005-03-30
申请人： Itaru Kawabata , Hirofumi Inoue
发明人： Itaru Kawabata , Hirofumi Inoue
IPC分类号： H01L27/108 , H01L21/8242 , H01L31/119
CPC分类号： H01L27/1087 , H01L27/10867
摘要： A semiconductor device includes a semiconductor substrate formed with a plurality of trenches, a plurality of trench capacitor type DRAM unit cells including capacitors formed in the trenches and cell transistors formed to be adjacent to the trenches respectively, a plurality of impurity doped regions including boundaries connecting the trenches and the cell transistors and formed in outer peripheries of the trenches, respectively, and a plurality of reverse conduction type impurity regions formed by doping regions of the substrate under the cell transistors with impurity of a reverse conduction type relative to the impurity doped regions, respectively.
摘要翻译：半导体器件包括形成有多个沟槽的半导体衬底，包括形成在沟槽中的电容器和形成为与沟槽相邻的单元晶体管的多个沟槽电容器型DRAM单位单元，多个杂质掺杂区域，包括边界连接沟槽和单元晶体管分别形成在沟槽的外周边，以及多个反向导电型杂质区域，该多个反向导电型杂质区域通过在单元晶体管的下方掺杂具有相对于杂质掺杂区域的反向导电类型的杂质的区域而形成，分别。

22. 发明授权

US08598831B2 Damper system for vehicle 有权
标题翻译：汽车减震器系统
公开(公告)号：US08598831B2
公开(公告)日：2013-12-03
申请号：US13201962
申请日：2009-07-08
申请人： Atsushi Ogawa , Motohiko Honma , Hirofumi Inoue
发明人： Atsushi Ogawa , Motohiko Honma , Hirofumi Inoue
IPC分类号： G05B5/01
CPC分类号： H02P3/12 , B60G17/06 , B60G2300/60 , F16F15/03 , F16F2232/06
摘要： A vehicle damper including an electromagnetic damper configured to generate a damping force with respect to a motion of a sprung portion and an unsprung portion toward each other and a motion thereof away from each other and includes: an electromagnetic motor; a motion converting mechanism; and an external circuit which is disposed outside the electromagnetic motor and including a first connection passage and a second connection passage and which includes a battery-device connection circuit for connecting the motor and a battery device and a battery-device-connection-circuit-current adjuster configured to adjust an electric current that flows in the battery-device connection circuit, wherein the damper system further includes an external-circuit controller configured to control an electric current that flows in the electromagnetic motor by controlling the external circuit and configured to control a flow of an electric current between the battery device and the electromagnetic motor by controlling the battery-device-connection-circuit-current adjuster.
摘要翻译：一种车辆阻尼器，包括电磁阻尼器，其构造成相对于弹簧部分和簧下部分相对于彼此的运动产生阻尼力，并且其运动彼此远离，并且包括：电磁马达; 运动转换机制; 以及外部电路，其设置在所述电磁电动机的外部并且包括第一连接通道和第二连接通道，并且包括用于连接所述电动机和电池装置的电池装置连接电路以及电池装置连接电路电流调整器，被配置为调节在电池装置连接电路中流动的电流，其中所述阻尼器系统还包括外部电路控制器，其被配置为通过控制所述外部电路来控制在所述电磁电动机中流动的电流，并且被配置为控制通过控制电池装置连接电路电流调节器，在电池装置和电磁马达之间流动电流。

23. 发明授权

US08400816B2 Resistance change memory device 有权
标题翻译：电阻变化记忆装置
公开(公告)号：US08400816B2
公开(公告)日：2013-03-19
申请号：US13237500
申请日：2011-09-20
申请人： Haruki Toda , Hirofumi Inoue , Hiroto Nakai
发明人： Haruki Toda , Hirofumi Inoue , Hiroto Nakai
IPC分类号： G11C11/00
CPC分类号： G11C13/00 , G11C5/063 , G11C8/14 , G11C11/56 , G11C13/0028 , G11C13/004 , G11C2013/0054 , G11C2213/71 , G11C2213/72
摘要： A resistance change memory device includes: a memory cell array with memory cells arranged therein, the memory cell having a variable resistance element for storing a rewritable resistance value; a reference cell formed of the same memory cells as those set in a high resistance state in the memory cell array, the reference cell being trimmed with selection of the number of parallel-connected memory cells to have a reference current value used for detecting data in the memory cell array; and a sense amplifier configured to compare a cell current value of a memory cell selected in the memory cell array with the reference current value of the reference cell.
摘要翻译：电阻变化存储器件包括：存储单元阵列，其中布置有存储单元，所述存储单元具有用于存储可重写电阻值的可变电阻元件; 由与存储单元阵列中的高电阻状态相同的存储单元形成的参考单元，通过选择并联连接的存储单元的数量来修整参考单元以具有用于检测数据的参考电流值存储单元阵列; 以及读出放大器，被配置为将存储单元阵列中选择的存储单元的单元电流值与参考单元的参考电流值进行比较。

24. 发明授权

US08391045B2 Information recording/reproducing device 有权
标题翻译：信息记录/再现装置
公开(公告)号：US08391045B2
公开(公告)日：2013-03-05
申请号：US12563739
申请日：2009-09-21
申请人： Kohichi Kubo , Hirofumi Inoue , Mitsuru Sato , Chikayoshi Kamata , Shinya Aoki , Noriko Bota
发明人： Kohichi Kubo , Hirofumi Inoue , Mitsuru Sato , Chikayoshi Kamata , Shinya Aoki , Noriko Bota
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , B82Y10/00 , G11C11/5685 , G11C13/0069 , G11C2013/009 , G11C2213/17 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2481 , H01L45/085 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/147
摘要： An information recording/reproducing device includes a first electrode layer, a second electrode layer, a recording layer as a variable resistance between the first and second electrode layer, and a circuit which supplies a voltage to the recording layer to change a resistance of the recording layer. Each of the first and second electrode layers is comprised of IV or III-V semiconductor doped with p-type carrier or n-type carrier.
摘要翻译：信息记录/再现装置包括第一电极层，第二电极层，作为第一和第二电极层之间的可变电阻的记录层和向记录层提供电压以改变记录电阻的电路层。第一和第二电极层中的每一个由掺杂有p型载体或n型载流子的IV或III-V半导体构成。

25. 发明授权

US08320158B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08320158B2
公开(公告)日：2012-11-27
申请号：US12882685
申请日：2010-09-15
申请人： Hiroshi Kanno , Reika Ichihara , Takayuki Tsukamoto , Kenichi Murooka , Hirofumi Inoue
发明人： Hiroshi Kanno , Reika Ichihara , Takayuki Tsukamoto , Kenichi Murooka , Hirofumi Inoue
IPC分类号： G11C11/00
CPC分类号： G11C7/02 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0064 , G11C13/0097 , G11C2213/31 , G11C2213/71 , G11C2213/72
摘要： Nonvolatile semiconductor memory device of an embodiment includes: a memory cell array including a plurality of first and second lines intersecting each other and plural memory cells provided at intersections of the first and second lines and having data written and erased upon application of voltages of the same polarity; and a writing circuit configured to select first and second lines and supply a set or reset pulse to the memory cell through the selected first and second lines. In an erase operation, the writing circuit repeatedly supplies the reset pulse to a selected memory cell until data is erased, by increasing or decreasing voltage level and voltage application time of the reset pulse within a reset region. The reset region, or an aggregate of combinations of voltage level and voltage application time of the reset pulse, is a region where voltage level and voltage application time are negatively correlated.
摘要翻译：一个实施例的非易失性半导体存储器件包括：存储单元阵列，包括彼此相交的多个第一和第二线，以及设置在第一和第二线的交点处的多个存储单元，并且在施加相同的电压时写入和擦除数据极性; 以及写入电路，被配置为选择第一和第二行，并且通过所选择的第一和第二行向存储器单元提供置位或复位脉冲。在擦除操作中，写入电路通过增加或减小复位区域内的复位脉冲的电压电平和电压施加时间，将复位脉冲重复地提供给所选择的存储单元，直到数据被擦除。复位区域或复位脉冲的电压电平和电压施加时间的组合的总和是电压电平和电压施加时间呈负相关的区域。

26. 发明申请

US20120205612A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20120205612A1
公开(公告)日：2012-08-16
申请号：US13454625
申请日：2012-04-24
申请人： Hideyuki TABATA , Eiji ITO , Hirofumi INOUE
发明人： Hideyuki TABATA , Eiji ITO , Hirofumi INOUE
IPC分类号： H01L45/00 , H01L21/8239
CPC分类号： H01L27/2481 , G11C13/00 , G11C13/0009 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L45/085 , H01L45/1233 , H01L45/147 , H01L45/1675 , H01L2924/0002 , H01L2924/00
摘要： A nonvolatile semiconductor memory device comprises a semiconductor substrate; a cell array block formed on the semiconductor substrate and including plural stacked cell array layers each with a plurality of first lines, a plurality of second lines crossing the plurality of first lines, and memory cells connected at intersections of the first and second lines between both lines; and a plurality of via-holes extending in the stacked direction of the cell array layers to individually connect the first or second line in the each cell array layer to the semiconductor substrate. The via-holes are formed continuously through the plural cell array layers, and multiple via-holes having equal lower end positions and upper end positions are connected to the first or second lines in different cell array layers.
摘要翻译：非易失性半导体存储器件包括半导体衬底; 形成在所述半导体衬底上的单元阵列块，并且包括多个堆叠的单元阵列层，每个堆叠的单元阵列层具有多个第一线，与所述多条第一线交叉的多个第二线，以及在所述第一和第二线的两个交点处连接的存储单元线条以及在单元阵列层的堆叠方向上延伸的多个通孔，以将每个单元阵列层中的第一或第二线分别连接到半导体基板。通孔连续地形成在多个单元阵列层中，并且具有相同的下端位置和上端位置的多个通孔与不同的单元阵列层中的第一或第二线连接。

27. 发明申请

US20120080741A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120080741A1
公开(公告)日：2012-04-05
申请号：US13323965
申请日：2011-12-13
申请人： Shinichi Watanabe , Hirofumi Inoue
发明人： Shinichi Watanabe , Hirofumi Inoue
IPC分类号： H01L27/088
CPC分类号： H01L21/28123 , H01L29/4238
摘要： A semiconductor device includes a device isolation insulating film which is buried in a semiconductor substrate, a gate insulation film which is provided on the semiconductor substrate, a gate electrode which is provided on the gate insulation film, a source region and a drain region which are provided in the semiconductor substrate and spaced apart from each other in a manner to sandwich the gate electrode, both end portions of each of the source region and the drain region being offset from the device isolation insulating film in a channel width direction by a predetermined distance, and first and second gate electrode extension portions which are provided in a manner to cover both end portions of each of the source region and the drain region in a channel length direction.
摘要翻译：半导体器件包括埋在半导体衬底中的器件隔离绝缘膜，设置在半导体衬底上的栅极绝缘膜，设置在栅极绝缘膜上的栅极电极，源极区域和漏极区域设置在半导体基板中并且以夹着栅电极的方式彼此间隔开，源极区域和漏极区域中的每一个的两个端部在沟道宽度方向上偏离器件隔离绝缘膜预定距离以及第一和第二栅电极延伸部分，其以在沟道长度方向上覆盖源极区域和漏极区域中的每一个的两个端部的方式设置。

28. 发明授权

US08109371B2 Damper 有权
标题翻译：阻尼器
公开(公告)号：US08109371B2
公开(公告)日：2012-02-07
申请号：US12298189
申请日：2006-11-07
申请人： Takuhiro Kondo , Hirofumi Inoue
发明人： Takuhiro Kondo , Hirofumi Inoue
IPC分类号： F16F15/03
CPC分类号： F16F15/03 , B60G11/15 , B60G15/062 , B60G15/063 , B60G17/021 , B60G17/0272 , B60G2202/12 , B60G2204/1242 , B60G2204/128 , B60G2204/41 , F16F9/18 , F16F2232/04 , F16F2232/06
摘要： A damper is comprised of an actuator (A) connected to a sprung member (B) side of a vehicle, the actuator (A) including a motion converting mechanism (T) for transforming a linear motion into a rotational motion and a motor (M) to which the rotational motion resulting from the transformation by the motion converting mechanism (T) is transmitted; a hydraulic damper (E) including a cylinder (C), a piston (P) inserted slidably into the cylinder (C) and defining two pressure chambers within the cylinder (C), and a rod (R) connected at one end thereof to the piston (P), wherein a linear motion of the actuator (A) being transmitted to one of the rod (R) and the cylinder (C) while the other of the rod (R) and the cylinder (C) being connected to an unsprung member (W) side of the vehicle; and biasing means (1, 2, X, Y, Z) for biasing the hydraulic damper (E) in both compressing and extending directions.
摘要翻译：阻尼器包括连接到车辆的弹簧构件（B）侧的致动器（A），所述致动器（A）包括用于将线性运动转换为旋转运动的运动转换机构（T）和马达（M ），由运动转换机构（T）进行变换而产生的旋转运动; 液压阻尼器（E），包括气缸（C），可滑动地插入气缸（C）中并限定气缸（C）内的两个压力室的活塞（P），以及在其一端连接到活塞（P），其中致动器（A）的直线运动传递到杆（R）和气缸（C）中的一个，而杆（R）和气缸（C）中的另一个连接到车辆的簧下部件（W）侧; 以及用于在压缩和延伸方向上偏置液压阻尼器（E）的偏压装置（1,2，X，Y，Z）。

29. 发明申请

US20110317326A1 DISCHARGE GAP FILLING COMPOSITION AND ELECTROSTATIC DISCHARGE PROTECTOR 审中-公开
标题翻译：放电气隙填充组合物和静电放电保护器
公开(公告)号：US20110317326A1
公开(公告)日：2011-12-29
申请号：US13254288
申请日：2010-03-01
申请人： Mina Onishi , Yoshimitsu Ishihara , Hirofumi Inoue , Yukihiko Azuma
发明人： Mina Onishi , Yoshimitsu Ishihara , Hirofumi Inoue , Yukihiko Azuma
IPC分类号： H05F1/00 , C08L83/04 , C08K9/02 , H05K1/00 , H05K7/00
CPC分类号： H01T4/02 , H01C7/1006 , H01C7/12 , H01C17/06526 , H01C17/06553 , H01T4/10 , H05K9/0067
摘要： A discharge gap filling composition for an electrostatic discharge protector. The composition contains oxide film coated metal particles (A), a layered substance (B) and a binder component (C). Also disclosed is an electrostatic discharge protector including a discharge gap and a discharge gap filling material containing the discharge gap filling composition that is filled in the discharge gap.
摘要翻译：一种用于静电放电保护器的放电间隙填充组合物。该组合物含有氧化膜被覆的金属粒子（A），层状物质（B）和粘合剂成分（C）。还公开了包括放电间隙的静电放电保护器和包含填充在放电间隙中的放电间隙填充组合物的放电间隙填充材料。

30. 发明申请

US20110241225A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20110241225A1
公开(公告)日：2011-10-06
申请号：US13158098
申请日：2011-06-10
申请人： Hiroyuki NAGASHIMA , Hirofumi INOUE
发明人： Hiroyuki NAGASHIMA , Hirofumi INOUE
IPC分类号： H01L23/48
CPC分类号： G11C8/14 , G11C5/02 , G11C5/063 , G11C13/0004 , G11C13/0007 , G11C13/0028 , G11C2213/31 , G11C2213/71 , G11C2213/72 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory device includes a memory block having a three-dimensional memory cell array structure in which memory cell arrays are stacked, the memory cell array including: a plurality of first interconnections which are parallel to one another; a plurality of second interconnections which are formed so as to intersect with the plurality of first interconnections, the second interconnections being parallel to one another; and a memory cell which is disposed in each intersection portion of the first interconnection and the second interconnection, one end of the memory cell being connected to the first interconnection, the other end of the memory cell being connected to the second interconnection. The first interconnection disposed between the adjacent memory cell arrays is shared by memory cells above and below the first interconnection, and the vertically-overlapping first interconnections are connected to each other.
摘要翻译：一种半导体存储器件包括具有堆叠存储单元阵列的三维存储单元阵列结构的存储块，所述存储单元阵列包括：彼此平行的多个第一互连; 多个第二互连形成为与所述多个第一互连相交，所述第二互连彼此平行; 以及存储单元，其设置在所述第一互连和所述第二互连的每个交叉部分中，所述存储单元的一端连接到所述第一互连，所述存储单元的另一端连接到所述第二互连。设置在相邻存储单元阵列之间的第一互连由第一互连之上和之下的存储单元共享，并且垂直重叠的第一互连彼此连接。

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