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21. 发明授权

US07218560B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07218560B2
公开(公告)日：2007-05-15
申请号：US11293378
申请日：2005-12-05
申请人： Ryo Fukuda , Yohji Watanabe , Shuso Fujii
发明人： Ryo Fukuda , Yohji Watanabe , Shuso Fujii
IPC分类号： G11C7/00
CPC分类号： H01L23/5258 , G11C17/16 , G11C17/18 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory device includes a fuse element including a first terminal and a second terminal, which stores data based on whether or not it is electrically blown by a laser beam, a resistance element connected to the first terminal, a node in which the data is transferred, and a transistor provided between the resistance element and the node, which sets the data to the node.
摘要翻译：一种半导体存储器件，包括：熔丝元件，包括第一端子和第二端子，该第一端子和第二端子基于其是否被激光束电熔接的数据，连接到第一端子的电阻元件，数据为并且设置在电阻元件和节点之间的晶体管，其将数据设置到节点。

22. 发明申请

US20060114052A1 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US20060114052A1
公开(公告)日：2006-06-01
申请号：US11272872
申请日：2005-11-15
申请人： Ryo Fukuda
发明人： Ryo Fukuda
IPC分类号： H01H37/76
CPC分类号： H01L23/5256 , G11C17/14 , H01L2924/0002 , H01L2924/00
摘要： There is here disclosed a semiconductor integrated circuit comprising a laser beam irradiation object having one end portion at which a first potential is applied, a first transistor has a source and a drain wherein one of the source and the drain to which the other end portion of the object is electrically connected, a second transistor has a source and a drain wherein one of the source and the drain of the first transistor to which the other end portion is not electrically connected is electrically connected, and a storage circuit which is electrically connected to the one of the source and the drain of the second transistor to which the first transistor is electrically connected, and which is additionally electrically connected to the one of the source and the drain of the first transistor to which the other end portion is not electrically connected.
摘要翻译：这里公开了一种半导体集成电路，包括：激光束照射对象，其具有施加第一电位的一个端部，第一晶体管具有源极和漏极，源极和漏极中的一个源极和漏极的另一个端部物体电连接，第二晶体管具有源极和漏极，其中第一晶体管的源极和漏极之间的另一个端部未电连接的源极和漏极被电连接，并且存储电路电连接到第一晶体管电连接的第二晶体管的源极和漏极之一，并且另外电连接到第一晶体管的源极和漏极之一，另一个端部未与其电连接。

23. 发明授权

US06847564B2 Semiconductor memory device capable of relieving defective cell 失效
公开(公告)号：US06847564B2
公开(公告)日：2005-01-25
申请号：US10456478
申请日：2003-06-09
申请人： Ryo Fukuda
发明人： Ryo Fukuda
IPC分类号： G11C29/04 , G11C11/401 , G11C11/407 , G11C11/4096 , G11C29/00 , G11C7/00 , G06F12/00
CPC分类号： G11C29/848 , G11C11/4096 , G11C2207/002
摘要： A semiconductor memory device includes a data line shift circuit, a plurality of data mask lines connected to the plurality of sense amplifier write circuits, respectively, and a plurality of mask circuits. The plurality of mask circuits each include at least one shift switch circuit and supply a mask signal to a sense amplifier write circuit, which is connected to a mask circuit different from that before a data line is shifted by the data line shift circuit, through the shift switch circuit and supply the mask signal to a sense amplifier write circuit, which is connected to the same mask circuit as that before the data line is shifted, not through the shift switch circuit.

24. 发明授权

US06601199B1 Memory-embedded LSI 失效
标题翻译：内存式LSI
公开(公告)号：US06601199B1
公开(公告)日：2003-07-29
申请号：US09405128
申请日：1999-09-24
申请人： Ryo Fukuda , Hironori Banba , Toshimasa Namekawa , Shinji Miyano
发明人： Ryo Fukuda , Hironori Banba , Toshimasa Namekawa , Shinji Miyano
IPC分类号： G01R3128
CPC分类号： G01R31/3167 , G01R31/318505 , Y10S257/909
摘要： A plurality of memory macros are laid out in a semiconductor chip. Macro ID generation circuits generate macro IDs for identifying the memory macros, and have different layouts. These macro ID generation circuits are arranged outside the memory macros in the semiconductor chip, so that test control blocks in the memory macros can use the same layouts between all the memory macros to reduce the design load.
摘要翻译：多个存储器宏布置在半导体芯片中。宏ID生成电路生成用于识别存储宏的宏ID，并具有不同的布局。这些宏ID生成电路被布置在半导体芯片中的存储器宏之外，使得存储器宏中的测试控制块可以在所有存储器宏之间使用相同的布局来减少设计负载。

25. 发明授权

US08405428B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US08405428B2
公开(公告)日：2013-03-26
申请号：US13098752
申请日：2011-05-02
申请人： Ryo Fukuda , Masaru Koyanagi
发明人： Ryo Fukuda , Masaru Koyanagi
IPC分类号： H03K5/153
CPC分类号： H03K17/04 , H03K19/018521
摘要： A constant current source circuit includes one end connected to a second node as sources of third and fourth transistors, and the other end connected to a second power supply node that supplies a second voltage different from a first voltage. The clamp circuit is configured to form a current path between the second node and the second power supply node. It adjusts the potential of the second node to a certain potential when a first external input signal is switched from a first state to a second state.
摘要翻译：恒流源电路包括连接到第二节点的一端作为第三和第四晶体管的源极，另一端连接到提供不同于第一电压的第二电压的第二电源节点。钳位电路被配置为在第二节点和第二电源节点之间形成电流路径。当第一外部输入信号从第一状态切换到第二状态时，它将第二节点的电位调整到一定的电位。

26. 发明授权

US07893478B2 Semiconductor storage device and driving method thereof 失效
标题翻译：半导体存储装置及其驱动方法
公开(公告)号：US07893478B2
公开(公告)日：2011-02-22
申请号：US12060522
申请日：2008-04-01
申请人： Tomoki Higashi , Takashi Ohsawa , Ryo Fukuda
发明人： Tomoki Higashi , Takashi Ohsawa , Ryo Fukuda
IPC分类号： H01L27/108 , H01L29/94 , H01L23/52 , H01L21/70 , H01L29/66
CPC分类号： H01L27/1022 , G11C11/4023 , G11C11/4026 , G11C11/405 , G11C11/4085 , G11C2211/4016 , H01L21/8249 , H01L21/84 , H01L27/0207 , H01L27/105 , H01L27/1052 , H01L27/108 , H01L27/10802 , H01L27/1203 , H01L29/7841
摘要： This disclosure concerns a semiconductor storage device comprising a semiconductor layer provided on the insulation layer provided on the semiconductor substrate; a source layer and a drain layer provided in the semiconductor layer; a body provided between the source layer and the drain layer, the body being in an electrically floating state; an emitter layer contacting with the source layer, the emitter layer having an opposite conductive type to the source layer; a word line including the source layer, the drain layer, and the body, the word line being provided to memory cells arrayed in a first direction in a plurality of tow-dimensionally arranged memory cells; a source line connected to the source layers of the memory cells arrayed in the first direction; and a bit line connected to the drain layers of the memory cells arrayed in a second direction intersecting the first direction.
摘要翻译：本公开涉及一种半导体存储装置，其包括设置在设置在半导体衬底上的绝缘层上的半导体层; 设置在所述半导体层中的源极层和漏极层; 设置在所述源极层和所述漏极层之间的主体，所述主体处于电浮动状态; 与源极层接触的发射极层，发射极层与源极层具有相反的导电类型; 包括源层，漏极层和主体的字线，字线被提供给在多个维度上排列的存储单元中沿第一方向排列的存储单元; 连接到沿着第一方向排列的存储单元的源层的源极线; 以及连接到沿与第一方向相交的第二方向排列的存储单元的漏极层的位线。

27. 发明授权

US07855917B2 Semiconductor memory device and driving method thereof 有权
标题翻译：半导体存储器件及其驱动方法
公开(公告)号：US07855917B2
公开(公告)日：2010-12-21
申请号：US12244338
申请日：2008-10-02
申请人： Ryo Fukuda
发明人： Ryo Fukuda
IPC分类号： G11C16/04
CPC分类号： G11C11/404 , G11C11/4076 , G11C2211/4016
摘要： The disclosure concerns a memory including a floating body provided in a semiconductor layer between a source and a drain and storing data; a first gate dielectric provided on a first surface of the body; a first gate electrode provided on the first surface via the first gate dielectric; a second gate dielectric provided on a second surface of the body different from the first surface; a second gate electrode provided on the second surface via the second gate dielectric; a driver driving the first gate electrode and the second gate electrode; and a sense amplifier writing into the memory cells first data showing a sate of a small charge amount in a state that a voltage of the second gate electrode at a data writing time is brought closer to a potential of the source layer than a voltage of the second gate electrode at a data holding time.
摘要翻译：本公开涉及包括设置在源极和漏极之间的半导体层中并且存储数据的浮体的存储器; 设置在所述主体的第一表面上的第一栅极电介质; 经由所述第一栅极电介质设置在所述第一表面上的第一栅电极; 设置在与第一表面不同的主体的第二表面上的第二栅极电介质; 经由所述第二栅极电介质设置在所述第二表面上的第二栅电极; 驱动所述第一栅电极和所述第二栅电极的驱动器; 以及读出放大器，在数据写入时刻的第二栅电极的电压比电源的电压更靠近源极层的电位的状态下，向存储单元写入表示小电荷量的状态的第一数据第二栅电极处于数据保持时间。

28. 发明申请

US20090086559A1 SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF 失效
标题翻译：半导体存储器件及其驱动方法
公开(公告)号：US20090086559A1
公开(公告)日：2009-04-02
申请号：US12243195
申请日：2008-10-01
申请人： Takashi OHSAWA , Ryo Fukuda
发明人： Takashi OHSAWA , Ryo Fukuda
IPC分类号： G11C7/06 , G11C7/00 , G11C8/08
CPC分类号： G11C11/404 , G11C8/08 , G11C11/406 , G11C2211/4016 , G11C2211/4065
摘要： This disclosure concerns a memory including a memory cell including a drain, a source and a floating body, wherein when a refresh operation is executed, a first current is carried from the drain or the source to the body and a second current is carried from the body to the second gate electrode by applying a first voltage and a second voltage to the first gate electrode and the second gate electrode, the first voltage and the second voltage being opposite in polarity to each other, and a state of the memory cell is covered to an stationary state in which an amount of the electric charges based on the first current flowing in one cycle of the refresh operation is almost equal to an amount of the electric charges based on the second current flowing in one cycle of the refresh operation.
摘要翻译：本公开涉及包括包括漏极，源极和浮体的存储单元的存储器，其中当执行刷新操作时，第一电流从漏极或源被传送到主体，并且第二电流从通过向第一栅电极和第二栅电极施加第一电压和第二电压，第一电压和第二电压彼此极性相反，并且覆盖存储器单元的状态到第二栅极电极达到静止状态，其中基于在刷新操作的一个周期中流动的第一电流的电荷的量几乎等于基于在刷新操作的一个周期中流动的第二电流的电荷量。

29. 发明申请

US20080237695A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20080237695A1
公开(公告)日：2008-10-02
申请号：US11860956
申请日：2007-09-25
申请人： Tomoaki SHINO , Akihiro Nitayama , Takeshi Hamamoto , Hideaki Aochi , Takashi Ohsawa , Ryo Fukuda
发明人： Tomoaki SHINO , Akihiro Nitayama , Takeshi Hamamoto , Hideaki Aochi , Takashi Ohsawa , Ryo Fukuda
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , G11C11/404 , G11C11/4074 , G11C14/0018 , G11C2211/4016 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L27/1203 , H01L29/42344 , H01L29/785 , H01L29/78648
摘要： This disclosure concerns a memory comprising a charge trapping film; a gate insulating film; a back gate on the charge trapping film; a front gate on the gate insulating film; and a body region provided between a drain and a source, wherein the memory includes a first storage state for storing data depending on the number of majority carriers in the body region and a second storage state for storing data depending on the amount of charges in the charge trapping film, and the memory is shifted from the first storage state to the second storage state by converting the number of majority carriers in the body region into the amount of charges in the charge trapping film or from the second storage state to the first storage state by converting the amount of charges in the charge trapping film into the number of majority carriers in the body region.
摘要翻译：本公开涉及包含电荷捕获膜的存储器; 栅极绝缘膜; 电荷捕获膜上的后门; 栅极绝缘膜上的前门; 以及设置在漏极和源极之间的体区，其中所述存储器包括用于根据所述身体区域中的多数载体的数量存储数据的第一存储状态和用于根据所述体内区域中的电荷量存储数据的第二存储状态通过将身体区域中的多数载体的数量转换为电荷俘获膜中的电荷量或从第二存储状态到第一存储器，将存储器从第一存储状态转移到第二存储状态通过将电荷俘获膜中的电荷量转换成体区中的多数载体的数量来进行状态。

30. 发明授权

US07362159B2 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US07362159B2
公开(公告)日：2008-04-22
申请号：US11272872
申请日：2005-11-15
申请人： Ryo Fukuda
发明人： Ryo Fukuda
IPC分类号： H01H37/76 , H01H85/00
CPC分类号： H01L23/5256 , G11C17/14 , H01L2924/0002 , H01L2924/00
摘要： There is here disclosed a semiconductor integrated circuit comprising a laser beam irradiation object having one end portion at which a first potential is applied, a first transistor has a source and a drain wherein one of the source and the drain to which the other end portion of the object is electrically connected, a second transistor has a source and a drain wherein one of the source and the drain of the first transistor to which the other end portion is not electrically connected is electrically connected, and a storage circuit which is electrically connected to the one of the source and the drain of the second transistor to which the first transistor is electrically connected, and which is additionally electrically connected to the one of the source and the drain of the first transistor to which the other end portion is not electrically connected.
摘要翻译：这里公开了一种半导体集成电路，包括：激光束照射对象，其具有施加第一电位的一个端部，第一晶体管具有源极和漏极，源极和漏极的另一个端部物体电连接，第二晶体管具有源极和漏极，其中第一晶体管的源极和漏极之间的另一个端部未电连接的源极和漏极被电连接，并且存储电路电连接到第一晶体管电连接的第二晶体管的源极和漏极之一，并且另外电连接到第一晶体管的源极和漏极之一，另一个端部未与其电连接。

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