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31. 发明申请

US20090058476A1 RECEIVER CIRCUIT FOR USE IN A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
标题翻译：在半导体集成电路中使用的接收器电路
公开(公告)号：US20090058476A1
公开(公告)日：2009-03-05
申请号：US12171214
申请日：2008-07-10
申请人： Ic Su Oh , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
发明人： Ic Su Oh , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
IPC分类号： H03L7/00
CPC分类号： H04L7/0337
摘要： A receiver circuit for sensing and transmitting input data in sync with a plurality of clock signals having mutually different phase sequentially enabled comprising a sense amplifier configured to receive, as offset voltages, first signals which can be obtained by amplifying the input data in sync with a first clock signal of the plurality of clock signals, being driven in sync with a second clock signal enabled subsequently to the first clock signal, and outputting second signals, and a discharging controller configured to control a discharging speed of the sense amplifier according to the offset voltages to control a driven speed of the sense amplifier.
摘要翻译：一种接收机电路，用于与具有相互不同相位的多个时钟信号同步地感测和发送输入数据，其顺序地使能，包括读出放大器，其被配置为接收作为偏移电压的第一信号，所述第一信号可以通过与所述多个时钟信号的第一时钟信号与与所述第一时钟信号之后使能的第二时钟信号同步地驱动，并输出第二信号;以及放电控制器，被配置为根据所述偏移来控制所述读出放大器的放电速度电压来控制读出放大器的驱动速度。

32. 发明授权

US09741434B2 Resistance change memory 有权
公开(公告)号：US09741434B2
公开(公告)日：2017-08-22
申请号：US14018287
申请日：2013-09-04
申请人： Akira Katayama , Masahiro Takahashi , Tsuneo Inaba , Hyuck Sang Yim , Dong Keun Kim , Byoung Chan Oh , Ji Wang Lee
发明人： Akira Katayama , Masahiro Takahashi , Tsuneo Inaba , Hyuck Sang Yim , Dong Keun Kim , Byoung Chan Oh , Ji Wang Lee
IPC分类号： G11C5/06 , G11C13/00 , G11C11/16
CPC分类号： G11C13/004 , G11C5/06 , G11C11/16 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C2013/0054
摘要： According to one embodiment, a memory includes a memory cell array including blocks arranged in a column direction, first and second main global conductive lines each extending from a first end to a second end of the memory cell array in the column direction, a first resistance change element connected between the first and second main global conductive lines inside the memory cell array, a first reference global conductive line extending from the first end to the second end of the memory cell array in the column direction, and a second resistance change element connected to the reference global conductive line outside the memory cell array.

33. 发明授权

US08947920B2 Memory device 有权
标题翻译：内存设备
公开(公告)号：US08947920B2
公开(公告)日：2015-02-03
申请号：US14018148
申请日：2013-09-04
申请人： Masahiro Takahashi , Tsuneo Inaba , Dong Keun Kim , Ji Wang Lee
发明人： Masahiro Takahashi , Tsuneo Inaba , Dong Keun Kim , Ji Wang Lee
IPC分类号： G11C11/00 , G11C11/16
CPC分类号： G11C11/1673 , G11C11/161 , G11C11/1659
摘要： According to one embodiment, a memory device includes a memory cell, a sense amplifier, unit structures and a reference signal generator. Each structure includes a first end, a first transistor, a first local line, a variable resistance element, a second transistor, a second local line, and a third transistor coupled in series. The reference signal generator includes first to fourth global lines, and first and second ones of the unit structures. The first unit structure is coupled at the first end to the first global line and coupled at the second end to the third global line. The second unit structure is coupled at the first end to the fourth global line and coupled at the second end to the second global line.
摘要翻译：根据一个实施例，存储器件包括存储器单元，读出放大器，单元结构和参考信号发生器。每个结构包括第一端，第一晶体管，第一局部线，可变电阻元件，第二晶体管，第二本地线和串联耦合的第三晶体管。参考信号发生器包括第一至第四全局线，以及第一和第二单元结构。第一单元结构在第一端耦合到第一全局线并且在第二端耦合到第三全局线。第二单元结构在第一端耦合到第四全局线并且在第二端耦合到第二全局线。

34. 发明申请

US20140286088A1 MEMORY DEVICE 有权
标题翻译：内存设备
公开(公告)号：US20140286088A1
公开(公告)日：2014-09-25
申请号：US14018148
申请日：2013-09-04
申请人： Masahiro TAKAHASHI , Tsuneo INABA , Dong Keun KIM , Ji Wang LEE
发明人： Masahiro TAKAHASHI , Tsuneo INABA , Dong Keun KIM , Ji Wang LEE
IPC分类号： G11C11/16
CPC分类号： G11C11/1673 , G11C11/161 , G11C11/1659
摘要： According to one embodiment, a memory device includes a memory cell, a sense amplifier, unit structures and a reference signal generator. Each structure includes a first end, a first transistor, a first local line, a variable resistance element, a second transistor, a second local line, and a third transistor coupled in series. The reference signal generator includes first to fourth global lines, and first and second ones of the unit structures. The first unit structure is coupled at the first end to the first global line and coupled at the second end to the third global line. The second unit structure is coupled at the first end to the fourth global line and coupled at the second end to the second global line.
摘要翻译：根据一个实施例，存储器件包括存储器单元，读出放大器，单元结构和参考信号发生器。每个结构包括第一端，第一晶体管，第一局部线，可变电阻元件，第二晶体管，第二本地线和串联耦合的第三晶体管。参考信号发生器包括第一至第四全局线，以及第一和第二单元结构。第一单元结构在第一端耦合到第一全局线并且在第二端耦合到第三全局线。第二单元结构在第一端耦合到第四全局线并且在第二端耦合到第二全局线。

35. 发明申请

US20120140870A1 INTEGRATED CIRCUIT AND METHOD FOR DRIVING THE SAME 失效
标题翻译：集成电路及其驱动方法
公开(公告)号：US20120140870A1
公开(公告)日：2012-06-07
申请号：US12980643
申请日：2010-12-29
申请人： Ji-Wang LEE , Shin-Deok KANG
发明人： Ji-Wang LEE , Shin-Deok KANG
IPC分类号： H03K23/00
CPC分类号： G06F1/10 , H03K21/406 , H03K23/425
摘要： An integrated circuit includes a counter configured to perform a counting operation and output a count code value. The integrated circuit further includes an operation controller, a digital circuit and an alignment unit. The operation controller receives the count code value and generates a first control signal and a second control signal. The first control signal is generated, when the count code value is equal to a first value, which is counted by the counter prior to a target count value. The second control signal is generated, when the count code value is equal to the target count value. A digital circuit performs a first operation based on the first control signal, and output a digital signal. An alignment unit aligns the digital signal, and outputs the aligned digital signal as a final digital signal in response to the second control signal.
摘要翻译：集成电路包括配置为执行计数操作并输出计数代码值的计数器。集成电路还包括操作控制器，数字电路和对准单元。操作控制器接收计数代码值并产生第一控制信号和第二控制信号。当计数码值等于由计数器在目标计数值之前计数的第一值时，产生第一控制信号。当计数码值等于目标计数值时，产生第二控制信号。数字电路基于第一控制信号执行第一操作，并输出数字信号。对准单元对准数字信号，并响应于第二控制信号而输出对准的数字信号作为最终的数字信号。

36. 发明授权

US08189400B2 Data alignment circuit of semiconductor memory apparatus 有权
标题翻译：半导体存储装置的数据对准电路
公开(公告)号：US08189400B2
公开(公告)日：2012-05-29
申请号：US12647174
申请日：2009-12-24
申请人： Hyung Soo Kim , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Jae Min Jang , Chang Kun Park
发明人： Hyung Soo Kim , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Jae Min Jang , Chang Kun Park
IPC分类号： G11C7/00
CPC分类号： G11C7/1006 , G11C7/1012 , G11C7/1078 , G11C7/1087
摘要： A data alignment circuit of a semiconductor memory apparatus for receiving and aligning parallel data group includes a first control unit, a second control unit, a first alignment unit and a second alignment unit. The first alignment unit generates a first control signal group in response to an address group, a clock signal, and a latency signal. The second control unit generates a second control signal group in response to the address group, the clock signal, and the latency signal. The first alignment unit aligns the parallel data group as a first serial data group in response to the first control signal group. The second alignment unit aligns the parallel data group as a second serial data group in response to the second control signal group.
摘要翻译：用于接收和对准并行数据组的半导体存储装置的数据对准电路包括第一控制单元，第二控制单元，第一对准单元和第二对准单元。第一对准单元响应于地址组，时钟信号和等待时间信号产生第一控制信号组。第二控制单元响应于地址组，时钟信号和等待时间信号产生第二控制信号组。第一对准单元响应于第一控制信号组将并行数据组对准为第一串行数据组。第二对准单元响应于第二控制信号组将并行数据组对准为第二串行数据组。

37. 发明授权

US08144530B2 Semiconductor memory device and method for generating output enable signal 有权
标题翻译：半导体存储器件和产生输出使能信号的方法
公开(公告)号：US08144530B2
公开(公告)日：2012-03-27
申请号：US12494403
申请日：2009-06-30
申请人： Hyung-Soo Kim , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
发明人： Hyung-Soo Kim , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
IPC分类号： G11C7/00
CPC分类号： H03L7/0816 , G11C7/1066 , G11C7/222 , H03L7/0805
摘要： A semiconductor memory device is able to generate an output enable signal in response to a read command and CAS latency information. The semiconductor memory device includes a delay locked loop configured to detect a phase difference of an external clock signal and a feedback clock signal, generate a delay control signal corresponding to the detected phase difference, and generate a DLL clock signal by delaying the external clock signal for a time corresponding to the delay control signal, a delay configured to output an active signal as an output enable reset signal in response to the delay control signal and an output enable signal generator configured to be reset in response to the output enable reset signal and generate an output enable signal in response to a read signal and a CAS latency signal by counting the external clock signal and the DLL clock signal.
摘要翻译：半导体存储器件能够响应于读取命令和CAS延迟信息而产生输出使能信号。半导体存储器件包括：延迟锁定环，被配置为检测外部时钟信号和反馈时钟信号的相位差，产生对应于检测到的相位差的延迟控制信号，并通过延迟外部时钟信号产生DLL时钟信号延迟一段时间对应于延迟控制信号，延迟配置为响应于延迟控制信号而输出有效信号作为输出使能复位信号;以及输出使能信号发生器，其被配置为响应于输出使能复位信号复位;以及通过对外部时钟信号和DLL时钟信号进行计数，响应于读取信号和CAS等待时间信号产生输出使能信号。

38. 发明授权

US08143940B2 Internal supply voltage generating circuit and method for generating internal supply voltage 失效
标题翻译：内部电源电压发生电路及产生内部电源电压的方法
公开(公告)号：US08143940B2
公开(公告)日：2012-03-27
申请号：US12347605
申请日：2008-12-31
申请人： Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
发明人： Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G05F1/56 , G11C5/145 , H03L7/0812 , H03L7/093
摘要： An internal supply voltage generating circuit includes a clock comparator configured to compare a first clock signal having clock information corresponding to a level of a reference voltage with a second clock signal having clock information corresponding to a level of an internal supply voltage, a control signal generator configured to generate a driving control voltage having a voltage level corresponding to an output signal of the clock comparator; and a driver configured to drive a terminal of the internal supply voltage in response to the driving control voltage.
摘要翻译：内部电源电压产生电路包括：时钟比较器，被配置为将具有与参考电压电平相对应的时钟信息的第一时钟信号与具有对应于内部电源电压电平的时钟信息的第二时钟信号进行比较;控制信号发生器被配置为产生具有与所述时钟比较器的输出信号相对应的电压电平的驱动控制电压; 以及配置为响应于驱动控制电压驱动内部电源电压的端子的驱动器。

39. 发明授权

US08045647B2 Low power, high speed receiver circuit for use in a semiconductor integrated circuit 失效
标题翻译：用于半导体集成电路的低功率，高速接收电路
公开(公告)号：US08045647B2
公开(公告)日：2011-10-25
申请号：US12170254
申请日：2008-07-09
申请人： Ic Su Oh , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
发明人： Ic Su Oh , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
IPC分类号： H03K9/00 , H04L27/00
CPC分类号： G11C7/1051 , G11C7/062 , G11C7/1069 , G11C11/56 , G11C27/026 , G11C2211/5634 , G11C2211/5642 , H04L25/0272 , H04L25/061 , H04L25/4919
摘要： A receiver circuit according to the invention includes a first phase transmission unit that is synchronized with a first clock, detects input data according to a plurality of detection levels, and transmits a first output signal, a first discharging control unit that controls a second phase transmission unit in response to the first output signal and adjusts the transmission speed of the second phase transmission unit by changing a node potential where an output of the second phase transmission is determined, and the second phase transmission unit that is synchronized with a second clock, detects the input data according to an output of the first discharging control unit, and transmits a second output signal.
摘要翻译：根据本发明的接收机电路包括与第一时钟同步的第一相位传输单元，根据多个检测电平检测输入数据，并发送第一输出信号;第一放电控制单元，其控制第二相位传输单元，响应于第一输出信号，并且通过改变确定第二相位传输的输出的节点电位来调整第二相位传输单元的传输速度，并且与第二时钟同步的第二相位传输单元检测所述输入数据根据所述第一放电控制单元的输出，并发送第二输出信号。

40. 发明申请

US20110156772A1 INTERFACE APPARATUS FOR SEMICONDUCTOR INTEGRATED CIRCUIT AND INTERFACING METHOD THEREOF 有权
标题翻译：用于半导体集成电路的接口装置及其接口方法
公开(公告)号：US20110156772A1
公开(公告)日：2011-06-30
申请号：US12650122
申请日：2009-12-30
申请人： Ji-Wang LEE , Yong-Ju Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Wang , Hae-Rang Choi , Jae-Min Jang , Chang-Kun Park
发明人： Ji-Wang LEE , Yong-Ju Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Wang , Hae-Rang Choi , Jae-Min Jang , Chang-Kun Park
IPC分类号： H03L7/06
CPC分类号： H03K19/0175 , H03K5/1565
摘要： An interface apparatus for a semiconductor integrated circuit and an interfacing method thereof controls the VOX of differential signals to a target level in response to the differential signals being outputted by an output block. The interface apparatus for a semiconductor integrated circuit includes an output block configured to output differential signals output by an internal circuit a detector configured to detect a timing error of the differential signals; and a controller configured to control a timing of the differential signals output by the internal circuit according to a detection result of the detector.
摘要翻译：半导体集成电路的接口装置及其接口方法响应于由输出块输出的差分信号，将差分信号的VOX控制到目标电平。用于半导体集成电路的接口装置包括：输出块，被配置为输出由内部电路输出的差分信号;检测器，被配置为检测差分信号的定时误差; 以及控制器，被配置为根据检测器的检测结果来控制由内部电路输出的差分信号的定时。

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