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31. 发明授权

US07288961B2 Tri-state circuit using nanotube switching elements 有权
公开(公告)号：US07288961B2
公开(公告)日：2007-10-30
申请号：US11656253
申请日：2007-01-22
申请人： Claude L. Bertin
发明人： Claude L. Bertin
IPC分类号： H03K19/00 , H03K19/02
CPC分类号： G11C11/56 , B82Y10/00 , G11C13/025 , G11C23/00 , H01H1/0094 , Y10S977/932 , Y10S977/936 , Y10S977/94
摘要： Nanotube-based logic circuitry is disclosed. Tri-stating elements add an enable/disable function to the circuitry. The tri-stating elements may be provided by nanotube-based switching devices. In the disabled state, the outputs present a high impedance, i.e., are tri-stated, which state allows interconnection to a common bus or other shared communication lines. In embodiments wherein the components are non-volatile, the inverter state and the control state are maintained in the absence of power. Such an inverter may be used in conjunction with and in the absence of diodes, resistors and transistors or as part of or as a replacement to CMOS, biCMOS, bipolar and other transistor level technologies.

32. 发明申请

US20070069810A1 SET/RESET latch circuit, Schmitt trigger circuit, and MOBILE based D-type flip flop circuit and frequency divider circuit thereof 失效
标题翻译： SET / RESET锁存电路，施密特触发电路和基于MOBILE的D型触发器电路及其分频器电路
公开(公告)号：US20070069810A1
公开(公告)日：2007-03-29
申请号：US11418207
申请日：2006-05-05
申请人： Kyoung-Hoon Yang , Tae-Ho Kim
发明人： Kyoung-Hoon Yang , Tae-Ho Kim
IPC分类号： H03B7/06 , H03K17/58 , H03K19/10 , H03K19/02 , G06F17/50
CPC分类号： H03K3/315 , H03K3/2885 , H03K3/2897 , H03K5/00006 , H03K17/58
摘要： The present invention relates to SET/RESET latch circuit, Schmitt trigger circuit, and MOBILE based D-type flip flop circuit and frequency divider circuit using the SET/RESET latch circuit and Schmitt trigger circuit. Herein, SET/RESET latch circuit is especially configured with CML-type transistors and negative differential resistance diodes. The SET/RESET latch circuit can be applied for very high speed digital circuits A SET/RESET latch circuit, characterized by including a transistor 1 and 2 in which each emitter of said transistors is commonly connected to a current source, and a negative differential resistance diode 1 and 2 which are respectively connected to each collector of said transistor 1 and 2; and additionally performing to be the relationship of IP
摘要翻译：本发明涉及使用SET / RESET锁存电路和施密特触发电路的SET / RESET锁存电路，施密特触发电路和基于MOBILE的D型触发器电路和分频器电路。这里，SET / RESET锁存电路特别配置有CML型晶体管和负差分电阻二极管。 SET / RESET锁存电路可以应用于非常高速的数字电路A SET / RESET锁存电路，其特征在于包括晶体管1和2，其中所述晶体管的每个发射极共同连接到电流源，负差分电阻二极管1和2分别连接到所述晶体管1和2的每个集电极; 并且另外执行以下的关系：其中，I P ：所述负差分电阻二极管1和2的峰值电流为：与所述晶体管1和2的发射极的公共节点串联连接的电流源的电流; 从而在分别在所述晶体管1和2的基端口上提供归零模式SET和RESET电压的情况下提供单个和差分非归零模式输出。

33. 发明授权

US07167026B2 Tri-state circuit using nanotube switching elements 失效
标题翻译：使用纳米管开关元件的三态电路
公开(公告)号：US07167026B2
公开(公告)日：2007-01-23
申请号：US11032823
申请日：2005-01-10
申请人： Claude L. Bertin
发明人： Claude L. Bertin
IPC分类号： H03K19/00 , H03K19/02 , H03K19/20
CPC分类号： G11C11/56 , B82Y10/00 , G11C13/025 , G11C23/00 , H01H1/0094 , Y10S977/932 , Y10S977/936 , Y10S977/94
摘要： Nanotube-based logic circuitry is disclosed. Tri-stating elements add an enable/disable function to the circuitry. The tri-stating elements may be provided by nanotube-based switching devices. In the disabled state, the outputs present a high impedance, i.e., are tri-stated, which state allows interconnection to a common bus or other shared communication lines. In embodiments wherein the components are non-volatile, the inverter state and the control state are maintained in the absence of power. Such an inverter may be used in conjunction with and in the absence of diodes, resistors and transistors or as part of or as a replacement to CMOS, biCMOS, bipolar and other transistor level technologies.
摘要翻译：公开了基于纳米管的逻辑电路。三态元件为电路添加一个启用/禁用功能。三态元件可以由基于纳米管的开关装置提供。在禁用状态下，输出呈现高阻抗，即三态，哪种状态允许与公共总线或其他共享通信线路的互连。在其中组件是非易失性的实施例中，在没有电力的情况下维持逆变器状态和控制状态。这种反相器可以与二极管，电阻器和晶体管结合使用，也可以用于CMOS，biCMOS，双极晶体管和其他晶体管级技术的一部分或替代。

34. 发明授权

US07161385B2 Circuit elements and parallel computational networks with logically entangled terminals 有权
标题翻译：具有逻辑纠缠终端的电路元件和并行计算网络
公开(公告)号：US07161385B2
公开(公告)日：2007-01-09
申请号：US10803094
申请日：2004-03-18
申请人： Pentti Haikonen
发明人： Pentti Haikonen
IPC分类号： H03K19/02 , H03K19/003
CPC分类号： G06F17/5022
摘要： The invention relates to circuit elements and computing networks for resolving logical entanglement, in which the allowed logical value of a variable in a set of variables depends on the logical values of the other variables in the set. A circuit element according to the invention comprises two or more logically entangled bi-directional terminals, wherein each bi-directional terminal can assume any one of three logical states, which are a logical true state, a logical false state, and an indefinite state, in which state the bi-directional terminal accepts one of the logical true and logical false states as an external input from an external source. An entanglement logic resolves the logical state of the bi-directional terminals according to a predetermined set of logical entanglement rules between the bi-directional terminals.
摘要翻译：本发明涉及用于解决逻辑纠缠的电路元件和计算网络，其中一组变量中的变量的允许逻辑值取决于该集合中其他变量的逻辑值。根据本发明的电路元件包括两个或更多个逻辑上缠结的双向终端，其中每个双向终端可以采取逻辑真实状态，逻辑假状态和不确定状态的三种逻辑状态中的任何一种，在哪种状态下，双向终端从外部源接收作为外部输入的逻辑真实和逻辑假状态之一。纠缠逻辑根据双向终端之间的一组预定的逻辑纠缠规则来解决双向终端的逻辑状态。

35. 发明授权

US07098833B2 Tri-value decoder circuit and method 有权
标题翻译：三值解码电路及方法
公开(公告)号：US07098833B2
公开(公告)日：2006-08-29
申请号：US10860979
申请日：2004-06-04
申请人： Paul Stulik , Hugo Cheung
发明人： Paul Stulik , Hugo Cheung
IPC分类号： H03M1/12 , H03M5/16 , H03K19/00 , H03K19/02
CPC分类号： H03M1/38 , H03M7/06
摘要： A tri-value decoder and method for decoding at least three states of an input signal are provided. An exemplary tri-value decoder and method can facilitate decoding of input signals without the use of threshold values and/or forcing a tri-state input signal to a mid-rail value for tri-state detection, and with less dependence on variations in product, process and temperature. In accordance with an exemplary embodiment, an exemplary tri-value decoder circuit comprises a switch circuit, a feedback loop and a sequence detector. An exemplary switch circuit is configured to facilitate sampling of a tri-state input signal through control by the feedback loop, with the sequence detector configured for decoding the tri-state input signal into a two-bit digital signal by detecting at least two samples of the tri-state input signal during a sampling period.
摘要翻译：提供了三值解码器和用于解码输入信号的至少三种状态的方法。示例性三值解码器和方法可以有助于解码输入信号而不使用阈值和/或强制三态输入信号到三态检测的中间轨值，并且对产品变化的依赖性较小，工艺和温度。根据示例性实施例，示例性三值解码器电路包括开关电路，反馈回路和序列检测器。示例性的开关电路被配置为便于通过反馈环路的控制对三态输入信号进行采样，其中，序列检测器被配置用于通过检测至少两个采样的三态输入信号来解码为三位数字信号采样周期内的三态输入信号。

36. 发明申请

US20050280436A1 Nanotube-based logic driver circuits 失效
标题翻译：基于纳米管的逻辑驱动电路
公开(公告)号：US20050280436A1
公开(公告)日：2005-12-22
申请号：US11033216
申请日：2005-01-10
申请人： Claude Bertin
发明人： Claude Bertin
IPC分类号： G11C13/02 , H03K19/003 , H03K19/02
CPC分类号： G11C13/025 , B82Y10/00 , G11C23/00 , G11C2213/16 , H03K19/02
摘要： Nanotube based logic driver circuits. These include pull-up driver circuits, push-pull driver circuits, tristate driver circuits, among others. Under one embodiment, an off-chip driver circuit includes a differential input having first and second signal links, each coupled to a respective one of two differential, on-chip signals. At least one output link is connectable to an off-chip impedance load, and at least one switching element has an input node, an output node, a nanotube channel element, and a control structure disposed in relation to the nanotube channel element to controllably form and unform an electrically conductive channel between said input node and said output node. The input node is coupled to a reference signal and the control structure is coupled to the first and second signal links. The output node is coupled to the output link, and the channel element is sized to carry sufficient current to drive said off-chip impedance load.
摘要翻译：基于纳米管的逻辑驱动电路。这些包括上拉驱动电路，推挽驱动电路，三态驱动电路等。在一个实施例中，片外驱动器电路包括具有第一和第二信号链路的差分输入，每个信号链路耦合到两个差分片上信号中的相应一个。至少一个输出链路可连接到片外阻抗负载，并且至少一个开关元件具有输入节点，输出节点，纳米管通道元件和相对于纳米管通道元件设置的可控制地形成的控制结构并且在所述输入节点和所述输出节点之间取消导电通道。输入节点耦合到参考信号，并且控制结构耦合到第一和第二信号链路。输出节点耦合到输出链路，并且信道单元的大小适于承载足够的电流以驱动所述片外阻抗负载。

37. 发明授权

US6150844A High voltage tolerance output stage 失效
标题翻译：高电压公差输出级
公开(公告)号：US6150844A
公开(公告)日：2000-11-21
申请号：US898811
申请日：1997-07-23
申请人： Giovanni Campardo , Stefano Zanardi , Carla Golla
发明人： Giovanni Campardo , Stefano Zanardi , Carla Golla
IPC分类号： H03K19/003 , H03K19/0175 , H03K19/02 , H03L5/00
CPC分类号： H03K19/00315 , H03K19/00384
摘要： An output stage for electronic circuits with high voltage tolerance and of the type comprising an output buffer made up of a complementary transistor pair comprising a P-channel MOS pull-up transistor and an N-channel MOS pull-down transistor. The transistors are connected together to make up an output terminal of the stage which comprises in addition a switch having an input connected to the output terminal of the stage and an output connected to the control terminal of the pull-up transistor to drive said control terminal in a state of extinction of the output buffer.
摘要翻译：一种用于具有高电压容限的电子电路的输出级，其类型包括由包括P沟道MOS上拉晶体管和N沟道MOS下拉晶体管的互补晶体管对构成的输出缓冲器。晶体管连接在一起以构成电平的输出端，另外还包括具有连接到电平的输出端的输入的开关和连接到上拉晶体管的控制端的输出，以驱动所述控制端处于输出缓冲区的灭绝状态。

38. 发明授权

US6130555A Driver circuitry for programmable logic devices 失效
标题翻译：用于可编程逻辑器件的驱动电路
公开(公告)号：US6130555A
公开(公告)日：2000-10-10
申请号：US22663
申请日：1998-02-12
申请人： Bruce B. Pedersen
发明人： Bruce B. Pedersen
IPC分类号： H03K19/173 , H03K19/094 , H03K19/02
CPC分类号： H03K19/1736
摘要： Buffers for driving interconnection conductors on programmable logic devices are shared between two types of uses, i.e., to drive static programmable connections to interconnection conductors, and to drive dynamically controllable connections to other interconnection conductors. The dynamically controllable connections are preferably tri-statable. Signals for effectuating the dynamic control are preferably generated on the programmable logic device near the tri-state-type connections. For example, a nearby logic module ("subregion") may provide the dynamic control signal. This reduces the extent of routing for, and consequent delay of, the dynamic control signal.
摘要翻译：用于驱动可编程逻辑器件上的互连导体的缓冲器在两种类型的使用之间共享，即驱动到互连导体的静态可编程连接，以及驱动与其他互连导体的动态可控连接。动态可控的连接优选是三态的。用于实现动态控制的信号优选地在三状态连接附近的可编程逻辑器件上产生。例如，附近的逻辑模块（“子区域”）可以提供动态控制信号。这减少了路由的程度并因此延迟了动态控制信号。

39. 发明授权

US5550488A Self timed driver 失效
标题翻译：自动驾驶
公开(公告)号：US5550488A
公开(公告)日：1996-08-27
申请号：US466904
申请日：1995-06-06
申请人： John A. Fifield , Lawrence G. Heller
发明人： John A. Fifield , Lawrence G. Heller
IPC分类号： H03K19/094 , H03K19/096 , H03K19/00 , H03K19/02
CPC分类号： H03K19/09429 , H03K19/0966
摘要： A self-timed tri-state driver circuit for a dual-rail differential input and single-ended output is disclosed. The circuit generates a tri-state mode in response to an Output Enable (OE) input pulsing low. The OE signal input is driven high to place the driver circuit into a ready state. The circuit is maintained in a tri-state mode until data appears at the inputs. Once a data signal is received after the tri-state circuit is in the ready state, the output immediately outputs this signal. Therefore, the output of the driver is self-timed from the arrival of the data.
摘要翻译：公开了一种用于双轨差分输入和单端输出的自定时三态驱动电路。电路响应于输出使能（OE）输入脉冲为低电平产生三态模式。 OE信号输入被驱动为高电平，以将驱动电路置于就绪状态。电路保持三态模式，直到数据出现在输入端。一旦在三态电路处于就绪状态之后接收到数据信号，输出立即输出该信号。因此，驱动程序的输出是从数据到达时自动进行的。

40. 再颁专利

USRE35125E Pulse control circuit for electric discharge machine using programmable logic 失效
标题翻译：使用可编程逻辑的放电机脉冲控制电路
公开(公告)号：USRE35125E
公开(公告)日：1995-12-19
申请号：US212722
申请日：1994-03-14
申请人： Yuji Kaneko
发明人： Yuji Kaneko
IPC分类号： B23H1/02 , B23H7/04 , H03K19/02
CPC分类号： B23H1/022
摘要： This invention provides a a ROM (10) which stores circuit function definition data for defining specified logic circuits relating to electric discharge machining and a programmable IC (20) which defines a specified logic circuit according to the circuit function definition data. This configuration is cost effective and minimizes hardware space requirements compared with configurations which used different logic circuits combined together. Further, when hardware needs to be reconfigured, the change can be achieved easily by replacing ROM (10) only.
摘要翻译：本发明提供了一种ROM（10），其存储用于定义与放电加工相关的指定逻辑电路的电路功能定义数据和根据电路功能定义数据定义指定逻辑电路的可编程IC（20）。与使用不同逻辑电路组合在一起的配置相比，该配置具有成本效益并最大限度地减少了硬件空间需求。此外，当需要重新配置硬件时，只需更换ROM（10）即可轻松实现更改。

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