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41. 发明申请

US20210098892A1 METHOD AND APPARATUS FOR MILLIMETER WAVE ANTENNA ARRAY 有权
公开(公告)号：US20210098892A1
公开(公告)日：2021-04-01
申请号：US17001451
申请日：2020-08-24
申请人： TENSORCOM, INC.
发明人： Guang-Fu Cheng
IPC分类号： H01Q21/06 , H01Q1/48 , H01Q21/00 , H01Q1/38
摘要： An antenna array system and a method for making the antenna system. The system includes at least two antenna elements serving as transmitter elements, and at least two antenna elements serving as receiver elements. Each of the transmitter antenna and receiver antenna elements include a pair of curved arms, wherein a first arm in the pair of curved arms is configured to be connected from a signal trace of the antenna system. The second arm in the pair of curved arms is configured to be connected to a ground plane.

42. 发明授权

US10200024B2 Method and apparatus for an active negative-capacitor circuit to cancel the input capacitance of comparators 有权
公开(公告)号：US10200024B2
公开(公告)日：2019-02-05
申请号：US15652934
申请日：2017-07-18
申请人： Tensorcom, Inc.
发明人： Dai Dai
IPC分类号： H03K5/24 , H03H11/48 , H03M1/00 , H03M1/08 , H03M1/18
摘要： A circuit comprises a first amplifier coupled to a first and a second node; a differential capacitive load coupled to the first and the second node, the differential capacitive load coupled between drains of transistors in a cross coupled transistor circuit; a current mirror coupled to a source of each transistor; and a capacitor coupled between the sources of the transistors. A plurality of amplifiers can be coupled to the differential capacitive load, wherein each amplifier comprises a clock-less pre-amplifier of a comparator. The amplifiers may be abutted to one another such that an active transistor of a first differential stage in a first amplifier behaves as a dummy transistor for an adjacent differential stage in a second amplifier.

43. 发明授权

US10103757B2 Method and apparatus to detect LO leakage and image rejection using a single transistor 有权
公开(公告)号：US10103757B2
公开(公告)日：2018-10-16
申请号：US15505444
申请日：2015-08-25
申请人： Tensorcom, Inc.
发明人： KhongMeng Tham , Huainan Ma , Zaw Soe , Ricky Lap Kei Cheung
IPC分类号： H04B1/04 , H03D7/12
摘要： Local oscillator (LO) leakage and Image are common and undesirable effects in typical transmitters. Typically, fairly complex hardware and algorithms are used to calibrate and reduce these impairments. A single transistor that draws essentially no dc current and occupies a very small area detects the LO leakage and Image signals. The single transistor operating as a square-law device is used to mix the signals at the input and output ports of a power amplifier. The mixed signal generated by the single transistor enables the simultaneous calibration of the LO leakage and Image Rejection.

44. 发明授权

US09960948B2 Method and apparatus of an input resistance of a passive mixer to broaden the input matching bandwidth of a common source/gate LNA 有权
公开(公告)号：US09960948B2
公开(公告)日：2018-05-01
申请号：US15357566
申请日：2016-11-21
申请人： Tensorcom, Inc.
发明人： Zaw Soe
IPC分类号： H04B1/10 , H04B1/16 , H03F3/22 , H04L27/38 , H03F1/42 , H03D7/14 , H03D7/16 , H03F1/22 , H03F3/193 , H03F3/45
CPC分类号： H03F1/42 , H03D7/125 , H03D7/1441 , H03D7/1466 , H03D7/165 , H03F1/223 , H03F3/193 , H03F3/387 , H03F3/45071 , H03F3/45179 , H03F2200/108 , H03F2200/294 , H03F2200/451 , H03F2200/492 , H03F2200/72 , H03F2200/75 , H04L27/38
摘要： A receiver comprises a Low Noise Amplifier (LNA) configured to amplify an input signal and a resonant circuit coupled to the LNA. A first switch couples current from the resonant circuit to a first capacitor integrating a first voltage, wherein the first switch is enabled with a clock signal. A second switch couples current from the resonant circuit to a second capacitor integrating a second voltage, wherein the second switch is enabled with an inverse clock signal. A differential amplifier comprises a positive input for receiving the first voltage and a negative input for receiving the second voltage in order to produce a sum and a difference frequency spectrum between a signal spectrum carried within the current and a frequency of the clock signal.

45. 发明授权

US09893692B2 High linearly WiGig baseband amplifier with channel select filter 有权
公开(公告)号：US09893692B2
公开(公告)日：2018-02-13
申请号：US15352877
申请日：2016-11-16
申请人： Tensorcom, Inc.
发明人： Zaw Soe , Kevin Jing , Steve Gao
IPC分类号： H03G1/00 , H03F3/45 , H03G5/28
CPC分类号： H03G1/007 , H03F3/45197 , H03F2200/165 , H03F2200/69 , H03F2203/45372 , H03F2203/45374 , H03F2203/45512 , H03F2203/45544 , H03F2203/45594 , H03F2203/45686 , H03F2203/45702 , H03G5/28 , H03H11/1286
摘要： A circuit comprises a Sallen-Key filter, which includes a source follower that implements a unity-gain amplifier; and a programmable-gain amplifier coupled to the Sallen-Key filter. The circuit enables programmable gain via adjustment to a current mirror copying ratio in the programmable-gain amplifier, which decouples the bandwidth of the circuit from its gain settings. The programmable-gain amplifier can comprise a differential voltage-to-current converter, a current mirror pair, and programmable output gain stages. The Sallen-Key filter and at least one branch in the programmable-gain amplifier can comprise transistors arranged in identical circuit configurations.

46. 发明申请

US20170317668A1 Method and Apparatus for an Active Negative-Capacitor Circuit to Cancel the Input Capacitance of Comparators 审中-公开
公开(公告)号：US20170317668A1
公开(公告)日：2017-11-02
申请号：US15652934
申请日：2017-07-18
申请人： Tensorcom, Inc.
发明人： Dai Dai
IPC分类号： H03K5/24 , H03H11/48 , H03M1/00 , H03M1/18 , H03M1/08
CPC分类号： H03K5/2481 , H03H11/481 , H03M1/002 , H03M1/0836 , H03M1/0845 , H03M1/183
摘要： A circuit comprises a first amplifier coupled to a first and a second node; a differential capacitive load coupled to the first and the second node, the differential capacitive load coupled between drains of transistors in a cross coupled transistor circuit; a current mirror coupled to a source of each transistor; and a capacitor coupled between the sources of the transistors. A plurality of amplifiers can be coupled to the differential capacitive load, wherein each amplifier comprises a clock-less pre-amplifier of a comparator. The amplifiers may be abutted to one another such that an active transistor of a first differential stage in a first amplifier behaves as a dummy transistor for an adjacent differential stage in a second amplifier

47. 发明申请

US20170272109A1 Method and Apparatus to Detect LO Leakage and Image Rejection using a Single Transistor 审中-公开
公开(公告)号：US20170272109A1
公开(公告)日：2017-09-21
申请号：US15505444
申请日：2015-08-25
申请人： Tensorcom, Inc.
发明人： KhongMeng Tham , Huainan Ma , Zaw Soe , Ricky Lap Kei Cheung
IPC分类号： H04B1/04 , H03D7/12
CPC分类号： H04B1/0475 , H03C2200/0058 , H03D3/008 , H03D3/009 , H03D7/125 , H03D7/165 , H04B1/04 , H04B1/0458 , H04B2001/0408
摘要： Local oscillator (LO) leakage and Image are common and undesirable effects in typical transmitters. Typically, fairly complex hardware and algorithms are used to calibrate and reduce these impairments. A single transistor that draws essentially no dc current and occupies a very small area detects the LO leakage and Image signals. The single transistor operating as a square-law device is used to mix the signals at the input and output ports of a power amplifier. The mixed signal generated by the single transistor enables the simultaneous calibration of the LO leakage and Image Rejection.

48. 发明申请

US20170063362A1 Method and Apparatus for an Active Negative-Capacitor Circuit to Cancel the Input Capacitance of Comparators 有权
标题翻译：用于消除比较器的输入电容的有源负电容电路的方法和装置
公开(公告)号：US20170063362A1
公开(公告)日：2017-03-02
申请号：US15340430
申请日：2016-11-01
申请人： Tensorcom, Inc.
发明人： Dai Dai
IPC分类号： H03K5/24 , H03H11/48
CPC分类号： H03K5/2481 , H03H11/481 , H03M1/002 , H03M1/0836 , H03M1/0845 , H03M1/183
摘要： A circuit comprises a first amplifier coupled to a first and a second node; a differential capacitive load coupled to the first and the second node, the differential capacitive load coupled between drains of transistors in a cross coupled transistor circuit; a current mirror coupled to a source of each transistor; and a capacitor coupled between the sources of the transistors. A plurality of amplifiers can be coupled to the differential capacitive load, wherein each amplifier comprises a clock-less pre-amplifier of a comparator. The amplifiers may be abutted to one another such that an active transistor of a first differential stage in a first amplifier behaves as a dummy transistor for an adjacent differential stage in a second amplifier
摘要翻译：电路包括耦合到第一和第二节点的第一放大器; 耦合到第一和第二节点的差分电容性负载，耦合在交叉耦合晶体管电路中的晶体管的漏极之间的差分电容性负载; 耦合到每个晶体管的源极的电流镜; 以及耦合在晶体管的源极之间的电容器。多个放大器可以耦合到差分电容性负载，其中每个放大器包括比较器的无时钟前置放大器。放大器可以彼此邻接，使得第一放大器中的第一差分级的有源晶体管在第二放大器中用作相邻差分级的虚拟晶体管

49. 发明授权

US09276610B2 Method and apparatus of a fully-pipelined layered LDPC decoder 有权
标题翻译：全流水线分层LDPC解码器的方法和装置
公开(公告)号：US09276610B2
公开(公告)日：2016-03-01
申请号：US14165505
申请日：2014-01-27
申请人： Tensorcom, Inc.
发明人： Bo Xia , Ricky Lap Kei Cheung , Bo Lu
IPC分类号： H03M13/11
CPC分类号： H03M13/1145 , H03M13/1122 , H03M13/114 , H03M13/1148 , H03M13/116
摘要： The architecture is able to switch to Non-blocking check-node-update (CNU) scheduling architecture which has better performance than blocking CNU scheduling architecture. The architecture uses an Offset Min-Sum with Beta=1 with a clock domain operating at 440 MHz. The constraint macro-matrix is a spare matrix where each “1’ corresponds to a sub-array of a cyclically shifted identity matrix which is a shifted version of an identity matrix. Four core processors are used in the layered architecture where the constraint matrix uses a sub-array of 42 (check nodes)×42 (variable nodes) in the macro-array of 168×672 bits. Pipeline processing is used where the delay for each layer only requires 4 clock cycles.
摘要翻译：该架构能够切换到具有比阻塞CNU调度架构更好的性能的非阻塞校验节点更新（CNU）调度体系结构。该架构使用Beta = 1的偏移最小和，时钟域工作在440 MHz。约束宏矩阵是备用矩阵，其中每个“1”对应于作为单位矩阵的移位版本的循环移位单位矩阵的子阵列。在分层架构中使用四个核心处理器，约束矩阵在168×672位的宏阵列中使用42（校验节点）×42（变量节点）的子阵列。使用管道处理，其中每层的延迟只需要4个时钟周期。

50. 发明授权

US09264056B2 Method and apparatus for an active negative-capacitor circuit to cancel the input capacitance of comparators 有权
标题翻译：用于消除比较器的输入电容的有源负电容电路的方法和装置
公开(公告)号：US09264056B2
公开(公告)日：2016-02-16
申请号：US14672214
申请日：2015-03-29
申请人： Tensorcom, Inc.
发明人： Dai Dai
IPC分类号： H03M1/12 , H03M1/00 , H03K5/24 , H03M1/08 , H03M1/18 , H03H11/48
CPC分类号： H03K5/2481 , H03H11/481 , H03M1/002 , H03M1/0836 , H03M1/0845 , H03M1/183
摘要： The differential output of a Programmable Gain Amplifier (PGA) is loaded by the input differential gate capacitance of a plurality of Analog to Digital convertors (ADC) comparators and the differential metal layer traces to interconnect these comparators to the PGA. The differential capacitive load presented to the PGA is quite large and reduces the bandwidth of this interconnect between the PGA and ADC. To overcome the performance degradation due to the differential capacitive load, an active negative-capacitor circuit cancels the effect of the large input capacitance of the ADC comparators. This cancelation extends the gain characteristics of the interconnect between the PGA's output and the inputs of the first stage of the comparators. The active negative-capacitance is comprised of a cross pair NMOS with a capacitor connecting their sources where each NMOS is biased by a current source.
摘要翻译：可编程增益放大器（PGA）的差分输出由多个模数转换器（ADC）比较器的输入差分栅极电容和差分金属层迹线加载，以将这些比较器与PGA互连。提供给PGA的差分电容性负载相当大，并降低了PGA和ADC之间的这种互连的带宽。为了克服由于差分电容性负载引起的性能下降，有源负电容电路消除了ADC比较器的大输入电容的影响。该取消扩展了PGA输出与比较器的第一级的输入之间的互连的增益特性。有源负电容由交叉对NMOS组成，其中电容器连接其源极，其中每个NMOS由电流源偏置。

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