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51. 发明授权

US07137095B1 Freeway routing system for a gate array 失效
标题翻译：高速公路路由系统为门阵列
公开(公告)号：US07137095B1
公开(公告)日：2006-11-14
申请号：US10077189
申请日：2002-02-15
申请人： Tong Liu , Jung-Cheun Lien , Sheng Feng , Eddy C. Huang , Chung-Yuan Sun , Naihui Liao , Weidong Xiong
发明人： Tong Liu , Jung-Cheun Lien , Sheng Feng , Eddy C. Huang , Chung-Yuan Sun , Naihui Liao , Weidong Xiong
IPC分类号： G06F17/50 , H03K19/177
CPC分类号： G06F17/5054 , G06F17/5077 , H03K19/17732 , H03K19/17736 , H03K19/17796
摘要： A freeway routing system that connects interface groups in said field programmable gate array. The freeway system has a first set of routing conductors configured to transfer signals to the input ports of at least one interface group in a first tile of the field programmable gate array and configured to transfer signals from the output ports of other tiles in the field programmable gate array. The first set of conductors include vertical conductors that form intersections horizontal conductors and programmable interconnect elements located at the intersections of the vertical conductors and horizontal conductors in a diagonal orientation to connect each of horizontal conductors to one of the vertical conductors.
摘要翻译：连接所述现场可编程门阵列中的接口组的高速路由系统。高速公路系统具有第一组路由导体，其被配置为将信号传送到现场可编程门阵列的第一瓦片中的至少一个接口组的输入端口，并且被配置为从现场可编程的其它瓦片的输出端口传送信号门阵列第一组导体包括垂直导体，其形成交叉点水平导体和位于垂直导体和水平导体的交叉点处的对准方向的可编程互连元件，以将每个水平导体连接到垂直导体之一。

52. 发明授权

US07132853B2 Inter-tile buffer system for a field programmable gate array 失效
公开(公告)号：US07132853B2
公开(公告)日：2006-11-07
申请号：US11410413
申请日：2006-04-24
申请人： Sheng Feng , Tong Liu , Jung-Cheun Lien
发明人： Sheng Feng , Tong Liu , Jung-Cheun Lien
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H01L27/118
摘要： An inter-tile buffering system for a field programmable gate array (FPGA) comprising a plurality of FPGA tiles arranged in rows and columns. Each file comprises a plurality of functional and interface groups and a primary routing structure, which is coupled to the functional and interface groups and is configured to receive and route primary output signals within at least one FPGA tile, and provide primary input signals to the functional and interface groups. Each functional group is configured to receive input signals, perform logic operations, and generate output signals and is configured to transfer signals from the routing structure to outside of at least one FPGA file, and includes a plurality of input multiplexers configured to select signals received from outside at least one FPGA tile and provide signals to the routing structure inside at least one FPGA tile.

53. 发明授权

US07129746B1 System-on-a-chip integrated circuit including dual-function analog and digital inputs 有权
公开(公告)号：US07129746B1
公开(公告)日：2006-10-31
申请号：US10877043
申请日：2004-06-25
申请人： Rabindranath Balasubramanian , Limin Zhu , Theodore Speers , Gregory Bakker
发明人： Rabindranath Balasubramanian , Limin Zhu , Theodore Speers , Gregory Bakker
IPC分类号： H03K19/173
CPC分类号： H03K19/1776 , G01K7/015 , G06F1/08 , G06F1/28 , G06F1/30 , G06F15/7842 , G06F15/7867 , H03F3/45475 , H03F2203/45136 , H03F2203/45166 , H03K17/223 , H03K19/177 , H03K19/17732
摘要： An integrated circuit includes a plurality of inputs, a plurality of output pads, a programmable logic block, an analog circuit block, an analog-to-digital converter programmably coupleable to individual analog circuits in the analog circuit block, and an interconnect architecture programmably coupling selected ones of the plurality of inputs, the plurality of outputs, the programmable logic block, the analog circuit block, and the analog-to-digital converter. At least one of the inputs may be programmably configured as one of a digital input programmably coupleable to elements in the programmable logic block or as an analog input to an analog circuit in the analog circuit block.

54. 发明授权

US07126842B2 Deglitching circuits for a radiation-hardened static random access memory based programmable architecture 有权
公开(公告)号：US07126842B2
公开(公告)日：2006-10-24
申请号：US11323417
申请日：2005-12-30
申请人： William C. Plants
发明人： William C. Plants
IPC分类号： G11C11/00
CPC分类号： G11C11/4125
摘要： The present invention comprises a device and a method for a deglitching circuit for a radiation tolerant static random access memory (SRAM) based field programmable gate array. The deglitching circuit for a radiation tolerant static random access memory (SRAM) based field programmable gate array comprises a configuration memory that has a plurality of configuration bits Read and write circuitry is provided to configure the plurality of configuration bits. A radiation hard latch is coupled to and controls a programmable element and an interface couples at least one of the plurality of configuration bits to the radiation hard latch when the write circuitry writes to the plurality of configuration bits.

55. 发明授权

US07119573B2 Field-programmable gate array low voltage differential signaling driver utilizing two complimentary output buffers 有权
公开(公告)号：US07119573B2
公开(公告)日：2006-10-10
申请号：US11123734
申请日：2005-05-05
申请人： Donald Y. Yu , Wei-Min Kuo
发明人： Donald Y. Yu , Wei-Min Kuo
IPC分类号： H03K19/173 , H03H11/26
CPC分类号： H03K19/17744 , H03K19/017581 , H03K19/17784
摘要： A low voltage signaling differential signaling driver comprising a first output line coupled to a delay circuit, a first multiplexer and a first output buffer. The first output line is also coupled to an inverter, a second multiplexer and a second output buffer.

56. 发明授权

US07119393B1 Transistor having fully-depleted junctions to reduce capacitance and increase radiation immunity in an integrated circuit 有权
标题翻译：晶体管具有完全耗尽的结以减少电容并增加集成电路中的辐射抗扰度
公开(公告)号：US07119393B1
公开(公告)日：2006-10-10
申请号：US10629337
申请日：2003-07-28
申请人： John McCollum
发明人： John McCollum
IPC分类号： H01L29/788 , H01L29/76 , H01L29/792
CPC分类号： H01L29/7881
摘要： A floating-gate transistor for an integrated circuit is formed on a p-type substrate. An n-type region is disposed over the p-type substrate. A p-type region is disposed over the n-type region. Spaced apart n-type source and drain regions are disposed in the p-type region forming a channel therein. A floating gate is disposed above and insulated from the channel. A control gate is disposed above and insulated from the floating gate. An isolation trench disposed in the p-type region and surrounding the source and drain regions, the isolation trench extending down into the n-type region. The substrate, the n-type region and the p-type region each biased such that the p-type region is fully depleted.
摘要翻译：用于集成电路的浮栅晶体管形成在p型衬底上。 n型区域设置在p型衬底上。 p型区域设置在n型区域上。间隔开的n型源极和漏极区域设置在形成其中的沟道的p型区域中。浮动栅极设置在通道上方并与通道绝缘。控制栅极设置在浮动栅极的上方并与其隔离。隔离沟槽设置在p型区域中并且围绕源区和漏区，隔离沟槽向下延伸到n型区域。衬底，n型区域和p型区域各自被偏置使得p型区域被完全耗尽。

57. 发明申请

US20060186920A1 Inter-tile buffer system for a field programmable gate array 失效
标题翻译：用于现场可编程门阵列的片间缓冲系统
公开(公告)号：US20060186920A1
公开(公告)日：2006-08-24
申请号：US11410413
申请日：2006-04-24
申请人： Sheng Feng , Tong Liu , Jung-Cheun Lien
发明人： Sheng Feng , Tong Liu , Jung-Cheun Lien
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H01L27/118
摘要： An inter-tile buffering system for a field programmable gate array (FPGA) comprising a plurality of FPGA tiles arranged in rows and columns. Each file comprises a plurality of functional and interface groups and a primary routing structure, which is coupled to the functional and interface groups and is configured to receive and route primary output signals within at least one FPGA tile, and provide primary input signals to the functional and interface groups. Each functional group is configured to receive input signals, perform logic operations, and generate output signals and is configured to transfer signals from the routing structure to outside of at least one FPGA file, and includes a plurality of input multiplexers configured to select signals received from outside at least one FPGA tile and provide signals to the routing structure inside at least one FPGA tile.
摘要翻译：一种用于现场可编程门阵列（FPGA）的片间缓冲系统，包括以行和列排列的多个FPGA片。每个文件包括多个功能和接口组以及主要路由结构，该主要路由结构耦合到功能和接口组，并且被配置为在至少一个FPGA瓦片内接收和路由主输出信号，并且向主要输入信号提供功能和接口组。每个功能组被配置为接收输入信号，执行逻辑操作并产生输出信号，并且被配置为将信号从路由结构传送到至少一个FPGA文件外部，并且包括多个输入多路复用器，被配置为选择从外部至少一个FPGA瓦片，并向至少一个FPGA瓦片内的路由结构提供信号。

58. 发明授权

US07075334B1 Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks 失效
标题翻译：可重复块在具有分段轨道的现场可编程门阵列中产生非均匀路由架构
公开(公告)号：US07075334B1
公开(公告)日：2006-07-11
申请号：US11120509
申请日：2005-05-02
申请人： Arunangshu Kundu , Eric Sather , William C. Plants
发明人： Arunangshu Kundu , Eric Sather , William C. Plants
IPC分类号： H03K19/177 , H01L25/00
CPC分类号： H03K19/17736 , H01L27/118
摘要： The apparatus comprises a repeatable non-uniform segmented routing architecture in a field programmable gate array having a plurality of sets of routing tracks having a first and last track position proceeding in a first direction and having at least one programmable element and at least one direct address device. The tracks are partitioned into uniform lengths and a track in the last position crosses over to a track in the first position immediately prior to said partition. The apparatus of the present system also has a plurality of sets of routing tracks having a first and last track position proceeding in a second direction. The tracks proceeding in the second direction have at least one programmable element and direct address device, wherein the tracks are partitioned into uniform lengths and said last track position crosses over to a first track position immediately prior to said partition.
摘要翻译：该装置包括现场可编程门阵列中的可重复的非均匀分段路由架构，其具有多组路由轨道，其具有在第一方向上进行的第一和最后轨道位置，并且具有至少一个可编程元件和至少一个直接地址设备。轨道被划分成均匀的长度，并且最后位置的轨道在紧接在所述分区之前的第一位置中越过轨道。本系统的装置还具有多组路由轨道，其具有在第二方向上进行的第一和最后轨道位置。在第二方向上进行的轨道具有至少一个可编程元件和直接地址设备，其中轨道被划分成均匀的长度，并且所述最后轨道位置在紧接在所述分区之前跨越到第一轨道位置。

59. 发明申请

US20060145722A1 Apparatus and method of error detection and correction in a radiation-hardened static random access memory field-programmable gate array 失效
标题翻译：辐射硬化静态随机存取存储器现场可编程门阵列中误差检测和校正的装置和方法
公开(公告)号：US20060145722A1
公开(公告)日：2006-07-06
申请号：US11367081
申请日：2006-03-02
申请人： William Plants
发明人： William Plants
IPC分类号： H03K19/007
CPC分类号： G06F11/1008 , G11C5/005 , G11C11/4125 , H01L27/118 , H03K19/00338 , H03K19/1776 , H03K19/17764 , H03K19/1778
摘要： The present system comprises a radiation tolerant programmable logic device having logic modules and routing resources coupling together the logic modules. Configuration data lines providing configuration data control the programming of the logic modules and the routing resources. Error correction circuitry coupled to the configuration data lines analyzes and corrects any errors in the configuration data that may occur due to a single event upset (SEU).
摘要翻译：本系统包括具有将逻辑模块耦合在一起的逻辑模块和路由资源的辐射容忍可编程逻辑器件。提供配置数据的配置数据线控制逻辑模块和路由资源的编程。耦合到配置数据线的错误校正电路分析和校正由于单个事件不正常（SEU）而可能发生的配置数据中的任何错误。

60. 发明授权

US07069419B2 Field programmable gate array and microcontroller system-on-a-chip 有权
公开(公告)号：US07069419B2
公开(公告)日：2006-06-27
申请号：US10821533
申请日：2004-04-08
申请人： Arunangshu Kundu , Arnold Goldfein , William C. Plants , David Hightower
发明人： Arunangshu Kundu , Arnold Goldfein , William C. Plants , David Hightower
IPC分类号： G06F13/42 , G06F15/17
CPC分类号： G06F15/7842 , G06F15/7867
摘要： A system-on-a-chip integrated circuit has a field programmable gate array core having logic clusters, static random access memory modules, and routing resources, a field programmable gate array virtual component interface translator having inputs and outputs, wherein the inputs are connected to the field programmable gate array core, a microcontroller, a microcontroller virtual component interface translator having input and outputs, wherein the inputs are connected to the microcontroller, a system bus connected to the outputs of the field programmable gate array virtual component interface translator and also to the outputs of said microcontroller virtual component interface translator, and direct connections between the microcontroller and the routing resources of the field programmable gate array core.

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