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51. 发明授权

US07490119B2 High speed adder design for a multiply-add based floating point unit 失效
标题翻译：用于基于加法的浮点单元的高速加法器设计
公开(公告)号：US07490119B2
公开(公告)日：2009-02-10
申请号：US10733839
申请日：2003-12-11
申请人： Sang Hoo Dhong , Silvia Melitta Mueller , Hwa-Joon Oh
发明人： Sang Hoo Dhong , Silvia Melitta Mueller , Hwa-Joon Oh
IPC分类号： G06F7/42 , G06F7/38
CPC分类号： G06F7/483 , G06F7/5443
摘要： An apparatus and computer program product are provided for improving a high-speed adder for Floating-Point Units (FPU) in a given computer system. The improved adder utilizes a compound incrementer, a compound adder, a carry network, an adder control/selector, and series of multiplexers (muxes). The carry network performs the end-around-carry function simultaneously to and independent of other required functions optimizing the functioning of the adder. Also, the use of a minimum number of muxes is also utilized to reduce mux delays.
摘要翻译：提供了一种用于在给定计算机系统中改进浮点单元（FPU）的高速加法器的装置和计算机程序产品。改进的加法器利用复合增量器，复合加法器，进位网络，加法器控制/选择器和多路复用器（多路复用器）系列。进位网络同时执行结束进位功能并且独立于优化加法器功能的其他所需功能。此外，还使用最小数量的多路复用器来减少多路复用器延迟。

52. 发明申请

US20080270507A1 DECOMPOSITION OF DECIMAL FLOATING POINT DATA, AND METHODS THEREFOR 有权
标题翻译：十进制浮点数据的分解及其方法
公开(公告)号：US20080270507A1
公开(公告)日：2008-10-30
申请号：US11840359
申请日：2007-08-17
申请人： Shawn D. Lundvall , Eric M. Schwarz , Ronald M. Smith , Phil C. Yeh
发明人： Shawn D. Lundvall , Eric M. Schwarz , Ronald M. Smith , Phil C. Yeh
IPC分类号： G06F7/42
CPC分类号： G06F9/30025 , G06F7/491 , G06F9/30036 , G06F2207/4911 , H03M7/24
摘要： A decimal floating point finite number in a decimal floating point format is composed from the number in a different format. A decimal floating point format includes fields to hold information relating to the sign, exponent and significand of the decimal floating point finite number. Other decimal floating point data, including infinities and NaNs (not a number), are also composed. Decimal floating point data are also decomposed from the decimal floating point format to a different format.
摘要翻译：十进制浮点格式的十进制浮点有限数字由不同格式的数字组成。十进制浮点格式包括用于保存与十进制浮点有限数字的符号，指数和有效数相关的信息的字段。其他十进制浮点数据也包括无限和无数（不是数字）。十进制浮点数据也从十进制浮点格式分解成不同的格式。

53. 发明申请

US20080263121A1 METHOD AND SYSTEM FOR OPTIMIZING FLOATING POINT CONVERSION BETWEEN DIFFERENT BASES 有权
标题翻译：用于优化不同基础之间的浮点转换的方法和系统
公开(公告)号：US20080263121A1
公开(公告)日：2008-10-23
申请号：US11736090
申请日：2007-04-17
申请人： Trevor E. Carlson , Ali Y. Duale
发明人： Trevor E. Carlson , Ali Y. Duale
IPC分类号： G06F7/42
CPC分类号： H03M7/24
摘要： A method of performing floating-point conversions in a digital computing system includes determining a source coefficient, c1, and a source exponent, n, of an input value represented by a floating-point number in a source base, b1; converting the source coefficient to a common base, b2, and storing the converted coefficient in a first digit collection; iteratively multiplying the contents of the first digit collection by b1 and storing the intermediate results therein, wherein one or more overflow bits of the first digit collection are carried and added to one or more additional digit collections once a nonzero value is reached; and an output value in the common base is stored in the digit collections after n multiplication iterations, represented by c2×b2m, wherein c2 is the converted coefficient of the output value in the common base b2 and m is the exponent of the output value.
摘要翻译：一种在数字计算系统中执行浮点转换的方法包括确定源数据c 1和源指数n，源数据n由源中的浮点数表示的输入值碱，b <1> 将源系数转换为公共基数b <2>，并将转换的系数存储在第一数字集合中; 将第一数字集合的内容迭代乘以b 1＆lt; 1＆gt;并将其中的中间结果存储在其中，其中携带第一数字集合的一个或多个溢出比特并将其添加到一个或多个附加数字集合达到非零值; 并且共同基底中的输出值被存储在数字集合中，在n乘法迭代之后，由c 2 2 x b 2，...，m 2表示，其中c ＆lt; 2＆gt; 2是公共基底b 2中的输出值的转换系数，m是输出值的指数。

54. 发明授权

US07322032B1 Methods and apparatus for scheduling operation of a data source 有权
标题翻译：调度数据源操作的方法和装置
公开(公告)号：US07322032B1
公开(公告)日：2008-01-22
申请号：US10446981
申请日：2003-05-28
申请人： Gregory S. Goss , Albert A. Slane , Christopher J. Kappler
发明人： Gregory S. Goss , Albert A. Slane , Christopher J. Kappler
IPC分类号： G06F9/46 , G06F9/30 , G06F7/38 , G06F7/42 , G06F7/50 , G01R31/08
CPC分类号： G06F7/24 , G06F9/3836
摘要： A computerized device has dynamically modifiable hardware, such as an ASIC, that performs queue-scheduling operations. The hardware incorporates a generic sorting processor (GSP) that is dynamically configurable to implement various sorting algorithms to meet specific queue scheduling requirements for the computerized device. The computerized device extracts a first time stamp value and a second time stamp value associated with a first queue and a second queue, respectively. The computerized device receives instructions to configure a table of the GSP with scheduling entries. The computerized device compares the first time stamp value with the second time stamp value to form a comparison result. The computerized device then selects a decision instruction from the table, based upon the comparison result, and identifies a preferred queue of the first queue and the second queue, based upon the decision instruction.
摘要翻译：计算机化设备具有可动态修改的硬件，例如执行队列调度操作的ASIC。该硬件包含通用排序处理器（GSP），可以动态配置，以实现各种排序算法，以满足计算机化设备的特定队列调度要求。计算机化设备分别提取与第一队列和第二队列相关联的第一时间戳值和第二时间戳值。计算机化设备接收指令以配置具有调度条目的GSP表。计算机化设备将第一时间戳值与第二时间戳值进行比较以形成比较结果。计算机化设备然后基于比较结果从表中选择一个决定指令，并且基于该判定指令来识别第一队列和第二队列的首选队列。

55. 发明申请

US20070100923A1 Arithmethic logic and shifting device for use in a processor 有权
标题翻译：用于处理器的逻辑逻辑和移位装置
公开(公告)号：US20070100923A1
公开(公告)日：2007-05-03
申请号：US11266076
申请日：2005-11-02
申请人： Muhammad Ahmed , Ajay Ingle , Sujat Jamil
发明人： Muhammad Ahmed , Ajay Ingle , Sujat Jamil
IPC分类号： G06F7/42
CPC分类号： G06F9/30181 , G06F9/30032 , G06F9/3012 , G06F9/30189 , G06F9/3802 , G06F9/3851 , G06F9/3885
摘要： An arithmetic logic and shifting device is disclosed and includes an arithmetic logic unit that has a first input to receive a first operand from a first register port, a second input to receive a second operand from a second register port, and an output to selectively provide a memory address to a memory unit in a first mode of operation and to selectively provide an arithmetic output in a second mode of operation. Further, the arithmetic logic and shifting device includes a programmable shifter device that has a first input to receive data from the memory unit, a second input to receive the arithmetic output, a third input to receive an operation code of a computer execution instruction, and a shifted output to provide shifted data.
摘要翻译：公开了算术逻辑和移位装置，并且包括算术逻辑单元，该算术逻辑单元具有从第一寄存器端口接收第一操作数的第一输入端，从第二寄存器端口接收第二操作数的第二输入端和选择性地提供以第一操作模式向存储器单元提供存储器地址，并且在第二操作模式中选择性地提供算术输出。此外，算术逻辑和移位装置包括可编程移位器装置，其具有用于从存储器单元接收数据的第一输入端，用于接收算术输出的第二输入端，接收计算机执行指令的操作码的第三输入端，以及移位输出以提供移位数据。

56. 发明申请

US20050210093A1 Data processing apparatus and method for comparing floating point operands 有权
公开(公告)号：US20050210093A1
公开(公告)日：2005-09-22
申请号：US10805502
申请日：2004-03-22
申请人： Christopher Hinds , David Lutz
发明人： Christopher Hinds , David Lutz
IPC分类号： G06F7/02 , G06F7/42 , G06F7/483
CPC分类号： G06F7/026 , G06F7/483
摘要： The present invention provides a data processing apparatus and method for comparing first and second floating point operands to produce a comparison result. Each floating point operand has a sign component, an exponent component, and a fraction component. The data processing apparatus comprises first processing logic operable to receive, for each floating point operand, a first component derived from a predetermined number of most significant bits of the fraction component of that floating point operand, the predetermined number being less than the total number of bits constituting the fraction component. The first processing logic is further operable to receive the sign components and the exponent components of the first and second floating point operands and to compare the sign components, the exponent components and the first components of the first and second floating point operands in order to produce a plurality of signals indicative of the comparison. Evaluation logic is then used to evaluate whether the comparison result can be determined from those plurality of signals, and if so, the comparison result is determined. Further, second processing logic is provided which is operable, in the event that the evaluation logic determines that the comparison result cannot be determined from the plurality of signals, to receive, for each floating point operand, a second component derived from at least the bits of the fraction component of that floating point operand other than the predetermined number of most significant bits. The second processing logic then compares the second components of the first and second floating point operands in order to produce at least one further signal indicative of the comparison, and the evaluation logic is further operable to determine the comparison result from the plurality of signals and the at least one further signal. This technique provides a particularly quick and power efficient technique for producing the comparison result.

57. 发明申请

US20050131981A1 High speed adder design for a multiply-add based floating point unit 失效
标题翻译：用于基于加法的浮点单元的高速加法器设计
公开(公告)号：US20050131981A1
公开(公告)日：2005-06-16
申请号：US10733839
申请日：2003-12-11
申请人： Sang Dhong , Silvia Mueller , Hwa-Joon Oh
发明人： Sang Dhong , Silvia Mueller , Hwa-Joon Oh
IPC分类号： G06F7/42 , G06F7/483 , G06F7/544
CPC分类号： G06F7/483 , G06F7/5443
摘要： An apparatus and computer program product are provided for improving a high-speed adder for Floating-Point Units (FPU) in a given computer system. The improved adder utilizes a compound incrementer, a compound adder, a carry network, an adder control/selector, and series of multiplexers (muxes). The carry network performs the end-around-carry function simultaneously to and independent of other required functions optimizing the functioning of the adder. Also, the use of a minimum number of muxes is also utilized to reduce mux delays.
摘要翻译：提供了一种用于在给定计算机系统中改进浮点单元（FPU）的高速加法器的装置和计算机程序产品。改进的加法器利用复合增量器，复合加法器，进位网络，加法器控制/选择器和多路复用器（多路复用器）系列。进位网络同时执行结束进位功能并且独立于优化加法器功能的其他所需功能。此外，还使用最小数量的多路复用器来减少多路复用器延迟。

58. 发明授权

US06850109B2 Linear voltage subtractor/adder circuit and MOS differential amplifier circuit therefor 失效
标题翻译：线性电压减法器/加法电路及其MOS差分放大电路
公开(公告)号：US06850109B2
公开(公告)日：2005-02-01
申请号：US09940472
申请日：2001-08-29
申请人： Katsuji Kimura
发明人： Katsuji Kimura
IPC分类号： G06G7/14 , H03F1/32 , H03F3/45 , H03G3/10 , G06F7/42
CPC分类号： H03F3/45717 , G06G7/14 , H03F3/45183 , H03F3/4565 , H03F3/4569 , H03F3/45708 , H03F3/45739 , H03F2203/45456 , H03F2203/45484 , H03F2203/45566 , H03F2203/45612 , H03F2203/45702
摘要： A voltage subtractor/adder circuit has a differential pair having first and second MOS transistors. Gate electrodes of the first and second MOS transistors form input terminals for receiving an input differential voltage. Drain electrodes of the first and second MOS transistors form output terminals for outputting a subtraction output signal. Source electrodes of the first and second MOS transistors are commonly coupled to form an output terminal for addition output voltage. The sum of currents flowing through the first and second MOS transistors increases in proportion to the square of the input differential voltage. It is also possible to drive the differential pair by a constant current source. A level shifter may be provided for level-shifting the addition output voltage from the commonly coupled source electrodes.
摘要翻译：电压减法器/加法器电路具有具有第一和第二MOS晶体管的差分对。第一和第二MOS晶体管的栅电极形成用于接收输入差分电压的输入端。第一和第二MOS晶体管的漏极形成用于输出减法输出信号的输出端。第一和第二MOS晶体管的源电极共同耦合以形成用于加法输出电压的输出端。流过第一和第二MOS晶体管的电流的总和与输入差分电压的平方成比例地增加。也可以通过恒定电流源来驱动差分对。可以提供电平移位器用于对来自共同耦合的源电极的相加输出电压进行电平移位。

59. 发明授权

US6003125A High performance adder for multiple parallel add operations 失效
标题翻译：高性能加法器，用于多个并行加法运算
公开(公告)号：US6003125A
公开(公告)日：1999-12-14
申请号：US12381
申请日：1998-01-23
申请人： David Shippy
发明人： David Shippy
IPC分类号： G06F7/50 , G06F7/507 , G06F7/42 , G06F7/44
CPC分类号： G06F7/507 , G06F2207/382 , G06F2207/3828
摘要： An adder unit for a microprocessor, being capable, in response to a first control signal, of adding two full word data values, stored in a first storage location and in a second storage location, respectively, and being capable, in response to a second control signal, of adding in parallel four half word data values, a first half word data value and a second half word data value being stored in the first storage location at the low half and the high half thereof, respectively, and a third half word data value and a fourth half word data value being stored in the second storage location at the low half and the high half thereof, respectively. The adder unit includes a first half word adder, arranged so as to add the first half word and the third half word to provide a first sum output of the adder unit, and a first carry out signal. The adder unit also includes a second half word adder arranged so as to add the second half word and the fourth half word, with a carry-in of 0 to provide a second sum output. The adder unit also includes a third half word adder arranged so as to add the second half word and the fourth half word, with a carry-in of 1 to provide a third sum output. Finally, the adder unit includes logic responsive to the first and the second control signals such that when the first control signal is present and the first carry-out signal is a 0, the logic provides the second sum output as a second sum output of the adder, to be concatenated with the first sum output of the adder, but, when the first control signal is present and the first carry-out signal is a 1, the logic provides the third sum output as a second sum output of the adder, to be concatonated with the first sum output of the adder. On the othe hand, when the second control signal is present, the logic provides the second sum output as a second sum output of the adder.
摘要翻译：一种用于微处理器的加法器单元，其能够响应于第一控制信号分别存储在第一存储位置和第二存储位置中的两个全字数据值，并且能够响应于第二控制信号控制信号，分别并入四个半字数据值，第一半字数据值和第二半字数据值分别存储在第一存储位置的低半部和高半部，第三半字数据值和第四半字数据值分别存储在第二存储位置的低半部和高半部。加法器单元包括第一半字加法器，其被布置为将第一半字和第三半字相加以提供加法器单元的第一和输出和第一进位信号。加法器单元还包括第二半字加法器，其被布置以便以0的进位输入来添加第二半字和第四半字，以提供第二和输出。加法器单元还包括第三半字加法器，其被布置为以第二半字和第四半字相加，进位输入为1以提供第三和输出。最后，加法器单元包括响应于第一和第二控制信号的逻辑，使得当存在第一控制信号并且第一进位输出信号为0时，逻辑提供第二和输出作为第二和输出加法器，与加法器的第一和输出连接，但是当存在第一控制信号并且第一进位输出信号为1时，逻辑提供第三和输出作为加法器的第二和输出，与加法器的第一和输出相加。另一方面，当存在第二控制信号时，逻辑提供第二和输出作为加法器的第二和输出。

60. 发明授权

US5636351A Performance of an operation on whole word operands and on operations in parallel on sub-word operands in a single processor 失效
标题翻译：在单个处理器中对整个字操作数的操作和对子字操作数的并行操作的性能
公开(公告)号：US5636351A
公开(公告)日：1997-06-03
申请号：US390908
申请日：1995-02-17
申请人： Ruby B. Lee
发明人： Ruby B. Lee
IPC分类号： G06F9/38 , G06F7/00 , G06F7/50 , G06F7/508 , G06F7/52 , G06F7/53 , G06F7/57 , G06F9/302 , G06F7/42 , G06F7/44
CPC分类号： G06F7/5324 , G06F7/483 , G06F7/508 , G06F9/30014 , G06F9/30036 , G06F2207/3828
摘要： A system allows parallel data processing within a single processor. In order to allow for parallel processing of data, an arithmetic logic unit or other operation executing entity within the processing system such as a shifter is partitioned. Within each partition operations are performed on a portion of one or more operands. When the operation is to be performed on full word length operands, there is no parallel processing. Thus data is allowed to freely propagate across boundaries between the partitions. When performing the operation in parallel using a plurality of operands of less than one full word in length, data is prevented from being propagated across at least one boundary between the partitions. The principles of the present invention may also be utilized to implement a multiplier which performs parallel multiplication of partial word multiplicands.
摘要翻译：系统允许在单个处理器内进行并行数据处理。为了允许数据的并行处理，划分诸如移位器的处理系统内的算术逻辑单元或其他操作执行实体。在每个分区内，对一个或多个操作数的一部分执行操作。当对全字长操作数执行操作时，不进行并行处理。因此，允许数据在分区之间的边界上自由传播。当使用长度小于一个全字的多个操作数并行地执行操作时，防止数据跨越分区之间的至少一个边界传播。本发明的原理也可以用于实现执行部分字被乘数的并行乘法的乘法器。

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