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51. 发明授权

US09501261B2 Binary array with LSB dithering in a closed loop system 有权
标题翻译：在闭环系统中具有LSB抖动的二进制数组
公开(公告)号：US09501261B2
公开(公告)日：2016-11-22
申请号：US14271402
申请日：2014-05-06
申请人： QUALCOMM Incorporated
发明人： Zhilong Tang
IPC分类号： G06F7/00 , G06F7/485 , H03M1/08 , H03M1/06 , H03M1/74
CPC分类号： G06F7/485 , H03M1/0639 , H03M1/0863 , H03M1/74
摘要： A binary array system and method for operating an electrical system are disclosed. The binary array system includes a binary counter configured to output a number of bit values through a number of bit outputs. Each of the bit values are output through a corresponding one of the bit outputs. The system includes a number of binary array elements. Each of the binary array elements is coupled to a corresponding one of the bit outputs and is configured to provide a unit value based on one of the bit values output through the corresponding one of the bit outputs. The binary array system also includes a controller coupled to the binary counter that is configured to set the bit values of the binary counter.
摘要翻译：公开了用于操作电气系统的二进制阵列系统和方法。二进制数组系统包括二进制计数器，配置为通过多个位输出输出多个位值。每个位值通过相应的一个位输出输出。该系统包括多个二进制数组元素。每个二进制数组元件被耦合到对应的一个比特输出，并且被配置为基于通过相应的一个比特输出输出的比特值之一来提供单位值。二进制数组系统还包括耦合到二进制计数器的控制器，其被配置为设置二进制计数器的位值。

52. 发明授权

US09484946B2 Digital-to-analog converter (DAC), method for operating a DAC and transceiver circuit 有权
标题翻译：数模转换器（DAC），用于操作DAC和收发器电路的方法
公开(公告)号：US09484946B2
公开(公告)日：2016-11-01
申请号：US14468078
申请日：2014-08-25
申请人： NXP B.V.
发明人： Mattieu Deloge , Arnoud Pieter van der Wel
IPC分类号： H04B1/38 , H03M1/66 , H03M1/08 , H03M1/74
CPC分类号： H03M1/661 , H03M1/0881 , H03M1/745 , H04B1/38
摘要： Embodiments of digital-to-analog converters (DACs), methods for operating a DAC, and transceiver circuits are described. In one embodiment, a DAC includes an input terminal configured to receive a digital signal, a converter circuit configured to convert the digital signal into an analog signal using first-order interpolation allowing low electromagnetic emissions, and an output terminal configured to output the analog signal. Other embodiments are also described.
摘要翻译：描述了数模转换器（DAC）的实施例，用于操作DAC的方法和收发器电路。在一个实施例中，DAC包括被配置为接收数字信号的输入端子，被配置为使用允许低电磁发射的一阶插值将数字信号转换成模拟信号的转换器电路，以及被配置为输出模拟信号的输出端子。还描述了其它实施例。

53. 发明授权

US09419657B1 Hybrid I/Q and polar transmitter 有权
标题翻译：混合I / Q和极性发射机
公开(公告)号：US09419657B1
公开(公告)日：2016-08-16
申请号：US14861005
申请日：2015-09-22
申请人： Intel IP Corporation
发明人： Giuseppe Li Puma , Victor Da Fonte Dias
IPC分类号： H04L27/00 , H04B1/04 , H04L27/20 , H03M1/74
CPC分类号： H04L27/2032 , H04B1/0475 , H04B1/0483
摘要： A hybrid polar I-Q transmitter includes an I-Q derivation circuit configured to receive a first and second I-Q data components comprising a first I-Q data pair, and generate a first and second I-Q derived data components comprising a second I-Q data pair, respectively, based thereon, by utilizing a resolution information of a digital-to-analog converter (DAC) and a design criteria. The I-Q derivation circuit is further configured to determine a residual angle corresponding to a phase angle difference between the first I-Q data pair and the second I-Q data pair. The hybrid polar I-Q transmitter further comprises a modulation circuit configured to compensate the determined residual angle corresponding to the phase angle difference between the first I-Q data pair and the second I-Q data pair.
摘要翻译：混合极性IQ发射机包括IQ导出电路，其被配置为接收包括第一IQ数据对的第一和第二IQ数据组件，并且基于此分别通过以下方式生成包括第二IQ数据对的第一和第二IQ导出数据组件利用数模转换器（DAC）的分辨率信息和设计标准。 I-Q导出电路还被配置为确定对应于第一I-Q数据对和第二I-Q数据对之间的相位角差的剩余角度。混合极性I-Q发射机还包括调制电路，其被配置为补偿与第一I-Q数据对和第二I-Q数据对之间的相位角差对应的确定的剩余角度。

54. 发明申请

US20160233878A1 CURRENT OUTPUT CIRCUIT 有权
标题翻译：电流输出电路
公开(公告)号：US20160233878A1
公开(公告)日：2016-08-11
申请号：US14946655
申请日：2015-11-19
申请人： Renesas Electronics Corporation
发明人： Kosuke Fuwa
IPC分类号： H03M1/74 , G06F3/045 , H03M1/68
CPC分类号： G06F3/045 , G06F3/0416 , G06F3/046 , H03M1/68 , H03M1/745 , H03M1/765
摘要： Provided is a current output circuit 1 including a pseudo sine wave separation circuit 11 that separates a pseudo sine wave represented by a digital code Din into two pseudo half-waves represented by digital signals D1 and D2, a DA converter 113 that converts the pseudo half-wave represented by the digital signal D1 into an analog half-wave signal V1, a DA converter 114 that converts the pseudo half-wave represented by the digital signal D2 into an analog half-wave signal V2, and a voltage-current conversion circuit 12 that converts voltages of the half-wave signals V1 and V2 into currents and outputs a current Iout obtained by combining the currents.
摘要翻译：提供了一种电流输出电路1，其包括将由数字代码Din表示的伪正弦波分解成由数字信号D1和D2表示的两个伪半波的伪正弦波分离电路11，DA转换器113，其将伪半由数字信号D1表示为模拟半波信号V1的DA转换器114，将由数字信号D2表示的伪半波变换为模拟半波信号V2的DA转换器114，以及电压电流转换电路 12将半波信号V1和V2的电压转换为电流并输出通过组合电流获得的电流Iout。

55. 发明授权

US09407280B1 Harmonic time domain interleave to extend arbitrary waveform generator bandwidth and sample rate 有权
标题翻译：谐波时域交织以扩展任意波形发生器带宽和采样率
公开(公告)号：US09407280B1
公开(公告)日：2016-08-02
申请号：US14696857
申请日：2015-04-27
申请人： Tektronix, Inc.
发明人： John J. Pickerd
IPC分类号： H03M1/66 , H03M1/74 , H03M1/12
CPC分类号： H03M1/662 , H03M1/08 , H03M1/1215
摘要： A harmonic time interleave (HTI) system, including a reference signal, a first summing component to produce a summed reference signal, a de-interleave block to receive an input signal and output a plurality of de-interleaved input signals, a plurality of digital-to-analog converters, each digital-to-analog converter configured to receive a corresponding one of a plurality of de-interleaved input signals and to output a corresponding analog signal, a plurality of mixing components, each mixing component configured to receive the summed reference signal and an analog signal from a corresponding of the plurality of digital-to-analog converters, and to output a corresponding mixed signal, and a second summing component configured to receive the mixed signal from each of the corresponding mixing components and to produce a substantially full-bandwidth analog signal representation of the input signal.
摘要翻译：包括参考信号的和谐时间交织（HTI）系统，产生相加的参考信号的第一求和分量，接收输入信号并输出多个解交织的输入信号的解交织块，多个数字每个数/模转换器被配置为接收多个解交织的输入信号中的对应的一个，并且输出相应的模拟信号，多个混合分量，每个混合分量被配置为接收相加的参考信号和来自多个数模转换器对应的模拟信号，并输出相应的混合信号，以及第二加法分量，被配置为从每个相应的混合分量接收混合信号并产生一个基本上全带宽的模拟信号表示输入信号。

56. 发明申请

US20160182076A1 Background Calibration for Digital-to-Analog Converters 有权
标题翻译：数模转换器背景校准
公开(公告)号：US20160182076A1
公开(公告)日：2016-06-23
申请号：US14978392
申请日：2015-12-22
申请人： Texas Instruments Incorporated
发明人： Manar Ibrahim El-Chammas
IPC分类号： H03M1/10 , H03M1/74
CPC分类号： H03M1/1009 , H03M1/1061 , H03M1/66 , H03M1/662
摘要： A system and method where a comparator is operatively coupled to an output of a Digital-to-analog Converter (DAC). The DAC may comprise a single DAC core or a plurality of interleaved DAC cores. The comparator is configured to capture properties of DAC core output. A digital engine is operatively coupled to receive output of the comparator and configured to calculate a cross-correlation between comparator output and input to the DAC core(s). The digital engine may be configured to determine if the skew of each DAC core is positive or negative and to determine if a skew correction term for the DAC core(s) should be decreased or increased, based on the skew of each DAC core being positive or negative, respectively. In interleaved DAC core devices, clock frequency sampling edges of the comparator may alternate between clock edges of each of the interleaved DAC cores.
摘要翻译：比较器可操作地耦合到数模转换器（DAC）的输出的系统和方法。 DAC可以包括单个DAC核心或多个交错DAC核心。比较器配置为捕获DAC内核输出的属性。数字引擎可操作地耦合以接收比较器的输出并且被配置为计算比较器输出和DAC核心的输入之间的互相关。数字引擎可以被配置为确定每个DAC核心的偏斜是正还是负，并且基于每个DAC内核的偏移为正的来确定DAC核心的偏斜校正项是否应当减小或增加或负数。在交错DAC核心器件中，比较器的时钟频率采样边沿可在每个交错DAC核心的时钟边沿之间交替。

57. 发明申请

US20160180764A1 SOURCE DRIVER, DISPLAY DEVICE WITH THE SAME AND DRIVING METHOD THEREOF 审中-公开
标题翻译：源驱动器，显示器件及其驱动方法
公开(公告)号：US20160180764A1
公开(公告)日：2016-06-23
申请号：US14967785
申请日：2015-12-14
申请人： LG Display Co., Ltd.
发明人： Ju Young NOH , Jun Hyeok YANG , Kyoung Don WOO
IPC分类号： G09G3/20 , H03M1/74
CPC分类号： G09G3/2018 , G09G3/2003 , G09G3/3275 , G09G3/3688 , G09G2310/027 , G09G2310/0286 , G09G2310/0289 , G09G2310/0291 , G09G2310/08 , G09G2320/0673 , G09G2330/021 , H03M1/74
摘要： A display device includes: a display panel including pixels arranged in a matrix shape; and a source driver to apply data voltages to the pixels. The source driver includes: a shift controller to shift a sampling control signal; a latch array to sample digital video data in response to the sampling control signal shifted by the shift controller; a digital-to-analog converter array to convert the digital video data from the latch array into data voltages by decoding the digital video data and combination-outputting gamma compensation voltages on the basis of a gray value of the decoded data; an output buffer array to output the data voltages from the digital-to-analog converter array; and a bias controller to adjust a bias current, which is applied to the output buffer array, according to delay and stable intervals of the data voltage.
摘要翻译：显示装置包括：显示面板，包括以矩阵形状排列的像素; 以及将数据电压施加到像素的源极驱动器。源极驱动器包括：移位控制器，用于移位采样控制信号; 锁存阵列，用于响应于由所述移位控制器移位的采样控制信号来采样数字视频数据; 数模转换器阵列，用于通过解码数字视频数据并根据解码数据的灰度值组合输出伽马补偿电压将来自锁存器阵列的数字视频数据转换成数据电压; 输出缓冲器阵列，用于从数模转换器阵列输出数据电压; 以及偏置控制器，根据数据电压的延迟和稳定间隔来调整施加到输出缓冲器阵列的偏置电流。

58. 发明授权

US09350372B2 Arrangement for digital-to-analog converter 有权
标题翻译：数模转换器的布置
公开(公告)号：US09350372B2
公开(公告)日：2016-05-24
申请号：US13706428
申请日：2012-12-06
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Ching-Ho Chang , Yung-Chow Peng , Jui-Cheng Huang , Wen-Shen Chou
IPC分类号： H03M1/66 , H03M1/08 , H03M1/74
CPC分类号： H03M1/0827 , H03M1/742
摘要： Among other things, an arrangement for a digital-to-analog converter (DAC) is provided herein. In some embodiments, a metal-oxide semiconductor (MOS) array of the DAS comprises one or more cells respectively comprising one or more current sources. The current sources comprise one or more transistors having a horizontal gate layout. A switch arrangement of the DAS, to which the MOS array is connected, comprises one or more transistors having a vertical gate layout. Accordingly, in some embodiments, a DAC is provided which comprises transistors having a vertical gate layout and transistors having a horizontal gate layout.
摘要翻译：其中提供了一种用于数模转换器（DAC）的装置。在一些实施例中，DAS的金属氧化物半导体（MOS）阵列包括分别包括一个或多个电流源的一个或多个电池。电流源包括具有水平门布局的一个或多个晶体管。 MOS阵列连接到的DAS的开关装置包括具有垂直栅极布局的一个或多个晶体管。因此，在一些实施例中，提供了一种DAC，其包括具有垂直栅极布局的晶体管和具有水平栅极布局的晶体管。

59. 发明授权

US09337860B1 Precision sub-RADIX2 DAC with analog weight based calibration 有权
标题翻译：精密子RADIX2 DAC，具有模拟重量校准
公开(公告)号：US09337860B1
公开(公告)日：2016-05-10
申请号：US14721481
申请日：2015-05-26
申请人： Maxim Integrated Products, Inc.
发明人： Yuanfang Li , David Castaneda , Jean CauXuan Le , Patrick Chan
IPC分类号： H03M1/66 , H03M1/74
CPC分类号： H03M1/0692 , H03M1/1038 , H03M1/68 , H03M1/785
摘要： A system includes a sub-binary radix digital-to-analog converter (DAC) that converts a digital input signal to an analog output signal based on a sub-radix DAC code. A radix conversion module performs radix conversion on the digital input signal. To perform the radix conversion, the radix conversion module associates bit positions corresponding to the digital input signal with respective analog weights and converts the digital input signal to the sub-radix DAC code based on the respective analog weights.
摘要翻译：一个系统包括一个二进制数字数模转换器（DAC），它将数字输入信号转换为基于子基DAC代码的模拟输出信号。基数转换模块对数字输入信号执行基数转换。为了进行基数转换，基数转换模块将对应于数字输入信号的比特位置与相应的模拟权重相关联，并且基于相应的模拟权重将数字输入信号转换为子基DAC代码。

60. 发明授权

US09231607B2 Interconnect structures for minimizing clock and output timing skews in a high speed current steering DAC 有权
标题翻译：互连结构，用于最大限度地减少高速电流转向DAC中的时钟和输出时序偏差
公开(公告)号：US09231607B2
公开(公告)日：2016-01-05
申请号：US14593697
申请日：2015-01-09
申请人： Maxim Integrated Products, Inc.
发明人： Jerzy Teterwak , Dan McMahill
IPC分类号： H03M1/66 , H03M1/06 , H03M1/00 , H03M1/12 , H03M1/74
CPC分类号： H03M1/0624 , H03K19/017545 , H03M1/00 , H03M1/12 , H03M1/66 , H03M1/74 , H03M1/742 , H03M1/747
摘要： A digital-to-analog converter (DAC) system includes a DAC and a clock interconnect module. The DAC includes a plurality of segments and a plurality of drivers. Each of the plurality of segments receives driver signals from a respective one of the plurality of drivers and generates a positive output and a negative output based on the driver signals. Each of the plurality of drivers receives a respective one of a plurality of clock signals and outputs the driver signals based on the respective one of the plurality of clock signals. The clock interconnect module includes an interconnect loop. A clock input is connected to a first portion of the interconnect loop and the plurality of clock signals are output from a second portion of the interconnect loop connected to the plurality of drivers. An output interconnect module receives the positive outputs and the negative outputs generates a differential output signal.
摘要翻译：数模转换器（DAC）系统包括DAC和时钟互连模块。 DAC包括多个段和多个驱动器。多个段中的每一个接收来自多个驱动器中的相应驱动器的驱动器信号，并且基于驱动器信号产生正输出和负输出。多个驱动器中的每个驱动器接收多个时钟信号中的相应一个，并且基于多个时钟信号中的相应一个来输出驱动器信号。时钟互连模块包括互连环路。时钟输入连接到互连环路的第一部分，并且多个时钟信号从连接到多个驱动器的互连环路的第二部分输出。输出互连模块接收正输出，负输出产生差分输出信号。

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