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81. 发明授权

US07035356B1 Efficient method for traceback decoding of trellis (Viterbi) codes 有权
标题翻译：网格（维特比）代码追溯解码的高效方法
公开(公告)号：US07035356B1
公开(公告)日：2006-04-25
申请号：US10032597
申请日：2001-10-25
申请人： Martin Langhammer
发明人： Martin Langhammer
IPC分类号： H04L27/06
CPC分类号： H03M13/4176 , H03M13/4169
摘要： Methods and apparatus are provided for efficiently implementing a traceback decoding of Viterbi codes. A Viterbi decoder circuit having at least two data selection blocks and at least two trace registers is described. The number of registers corresponds to the number of states in a Viterbi trellis diagram applicable to encoded data. The trace registers are used to represent the current state best metric and are each configured to send their output to the inputs of the predecessor states representing the possible branches to the current state. The best metric for the predecessor state is determined using a survivor vector stored in memory. Traceback occurs by sequentially reading survivor vectors from memory, using the vectors to control the data selection blocks, and using the trace registers to sequentially identify predecessor states in the traceback.
摘要翻译：提供了有效实现维特比代码回溯解码的方法和装置。描述了具有至少两个数据选择块和至少两个跟踪寄存器的维特比解码器电路。寄存器的数量对应于适用于编码数据的维特比网格图中的状态数。跟踪寄存器用于表示当前状态最佳度量，并且被配置为将其输出发送到表示可能分支到当前状态的前导状态的输入。使用存储在存储器中的幸存者向量来确定先前状态的最佳度量。通过从存储器中顺序读取幸存者向量，使用向量来控制数据选择块，以及使用跟踪寄存器来顺序地识别回溯中的先前状态，从而发生追溯。

82. 发明授权

US07024446B2 Circuitry for arithmetically accumulating a succession of arithmetic values 失效
标题翻译：用于算术累积一系列算术值的电路
公开(公告)号：US07024446B2
公开(公告)日：2006-04-04
申请号：US10625093
申请日：2003-07-22
申请人： Martin Langhammer , Nitin Prasad
发明人： Martin Langhammer , Nitin Prasad
IPC分类号： G06F7/50
CPC分类号： G06F7/5095 , G06F5/015 , G06F7/53 , G06F7/575 , G06F7/724 , G06F15/7867 , G06F2207/3828 , H03K19/177 , H03K19/17732 , H03K19/17736
摘要： A programmable logic integrated circuit device has at least one function-specific circuit block (e.g., a parallel multiplier, a parallel barrel shifter, a parallel arithmetic logic unit, etc.) in addition to the usual multiple regions of programmable logic and the usual programmable interconnection circuit resources. To reduce the impact of use of the function-specific block (“FSB”) on the general purpose interconnection resources of the device, inputs and/or outputs of the FSB may be coupled relatively directly to a subset of the logic regions. In addition to conserving general purpose interconnect, resources of the logic regions to which the FSB are connected can be used by the FSB to reduce the amount of circuitry that must be dedicated to the FSB. If the FSB is a multiplier, additional features include facilitating accumulation of successive multiplier outputs (using either addition or subtraction and with sign extension if desired) and/or arithmetically combining the outputs of multiple multipliers.
摘要翻译：可编程逻辑集成电路器件除了可编程逻辑的通常多个区域和通常的可编程逻辑器件之外，还具有至少一个功能特定电路块（例如，并行乘法器，并行桶形移位器，并行算术逻辑单元等）互联电路资源。为了减少使用功能特定块（“FSB”）对设备的通用互连资源的影响，FSB的输入和/或输出可以相对直接地耦合到逻辑区域的子集。除了节省通用互连之外，FSB可以使用FSB连接的逻辑区域的资源，以减少必须专用于FSB的电路的数量。如果FSB是乘法器，则附加特征包括促进连续乘法器输出的累积（如果需要，使用加法或减法和符号扩展）和/或算术组合多个乘法器的输出。

83. 发明授权

US06987401B1 Compare, select, sort, and median-filter apparatus in programmable logic devices and associated methods 失效
公开(公告)号：US06987401B1
公开(公告)日：2006-01-17
申请号：US10277627
申请日：2002-10-22
申请人： Martin Langhammer , Jonah Graham
发明人： Martin Langhammer , Jonah Graham
IPC分类号： H03K19/177
CPC分类号： H03K19/17732
摘要： A programmable logic device (PLD) includes a compare-select circuitry. The compare-select circuitry includes logic elements 1 through N. Each logic element comprises a compare circuitry and a selector circuitry. The compare circuitry compares two inputs of the logic element and generates a compare output signal of the logic element. The selector circuitry provides one of the two inputs of the logic element as an output in response to a selection signal. The selection signal for all logic elements (i.e., logic elements 1 through N) constitutes the compare output signal of the Nth logic element. A median-calculation apparatus is also disclosed. The median-filter apparatus includes at least one insertion-sort circuitry. The at least one insertion-sort circuitry performs insertion-sorting of a set of input numbers corresponding to that insertion-sort circuitry to generate a corresponding set of sorted numbers. Each of the sorted set of numbers includes a median value of the corresponding set of input numbers.

84. 发明授权

US06978287B1 DSP processor architecture with write datapath word conditioning and analysis 失效
标题翻译： DSP处理器架构，具有写入数据路径字的条件和分析
公开(公告)号：US06978287B1
公开(公告)日：2005-12-20
申请号：US09826527
申请日：2001-04-04
申请人： Martin Langhammer
发明人： Martin Langhammer
IPC分类号： G06F7/38 , G06F7/499
CPC分类号： G06F9/30014 , G06F7/499 , G06F9/3824 , G06F9/3879 , G06F9/3885 , G06F15/7821
摘要： An improved digital signal processing (DSP) processor architecture is presented in which word conditioning (e.g., rounding, saturation, etc.) and analysis operations (e.g., block floating point analysis) are implemented in the write datapath to memory. By moving word conditioning operations from the critical path to the write datapath, the throughput of common DSP functional blocks such as multiplier-accumulator (MAC) blocks may be improved. Delays may be further reduced by combining analysis operations with write or move operations.
摘要翻译：提出了一种改进的数字信号处理（DSP）处理器体系结构，其中在写入数据路径到存储器中实现字调节（例如，舍入，饱和等）和分析操作（例如，块浮点分析）。通过将关键路径的字节调节操作移动到写数据路径，可以提高诸如乘法器累加器（MAC）块之类的公共DSP功能块的吞吐量。通过将分析操作与写入或移动操作组合可以进一步减少延迟。

85. 发明授权

US06937062B1 Specialized programmable logic region with low-power mode 失效
标题翻译：具有低功耗模式的专用可编程逻辑区域
公开(公告)号：US06937062B1
公开(公告)日：2005-08-30
申请号：US10778930
申请日：2004-02-12
申请人： Chiao Kai Hwang , Gregory Starr , Martin Langhammer
发明人： Chiao Kai Hwang , Gregory Starr , Martin Langhammer
IPC分类号： G06F7/50 , G06F7/508 , H03K19/177 , H03K19/173
CPC分类号： G06F7/508 , G06F7/501 , H03K19/17704 , H03K19/17728 , H03K19/17732 , H03K19/17784
摘要： In a specialized functional region of a programmable logic device, in which certain components may not be used, those components can be placed in a low-power mode so that they do not switch. For example, in an adder which is not being used but is receiving inputs, the current path for the adding circuitry is interrupted, while the output is forced low. If the adder is a carry/look-ahead adder, the GENERATE and PROPAGATE signals normally used in subsequent stages to predict the value of the carry signal are forced to constant values even if the inputs to the adder are changing.
摘要翻译：在可编程逻辑器件的专门功能区域中，其中某些部件可能不被使用，这些部件可以被置于低功率模式，使得它们不切换。例如，在不使用但接收输入的加法器中，加法电路的电流路径被中断，而输出被强制为低电平。如果加法器是进位/先行加法器，即使加法器的输入正在改变，通常在后续级中使用的GENERATE和PROPAGATE信号也被强制为恒定值。

86. 发明申请

US20050187999A1 Saturation and rounding in multiply-accumulate blocks 有权
标题翻译：多重积累块中的饱和度和舍入
公开(公告)号：US20050187999A1
公开(公告)日：2005-08-25
申请号：US10783829
申请日：2004-02-20
申请人： Leon Zheng , Martin Langhammer , Steven Perry , Paul Metzgen , Nitin Prasad , William Hwang
发明人： Leon Zheng , Martin Langhammer , Steven Perry , Paul Metzgen , Nitin Prasad , William Hwang
IPC分类号： G06F7/499 , G06F7/52 , G06F7/523 , G06F7/544
CPC分类号： G06F7/49921 , G06F7/49947 , G06F7/523 , G06F7/5443
摘要： Saturation and rounding capabilities are implemented in MAC blocks to provide rounded and saturated outputs of multipliers and of add-subtract-accumulate circuitrs implemented using DSP. These features support any suitable format of value representation, including the x.15 format. Circuitry within the multipliers and the add-subtract-accumulate circuits implement the rounding and saturation features of the present invention.
摘要翻译：饱和度和舍入能力在MAC块中实现，以提供乘法器的舍入和饱和输出以及使用DSP实现的加减累加电路。这些功能支持任何合适的价值表示形式，包括x.15格式。乘法器和加减累积电路内的电路实现了本发明的舍入和饱和特征。

87. 发明授权

US06781408B1 Programmable logic device with routing channels 有权
标题翻译：具有路由通道的可编程逻辑器件
公开(公告)号：US06781408B1
公开(公告)日：2004-08-24
申请号：US10132873
申请日：2002-04-24
申请人： Martin Langhammer
发明人： Martin Langhammer
IPC分类号： H03K19177
CPC分类号： H03K19/17736 , H03K19/17732
摘要： A programmable logic device (PLD) is provided that includes at least one dedicated output routing channel configured to facilitate the processing of output signals generated by multiple function-specific blocks (FSBs). The output routing channel includes a plurality of functional units that may be programmably selectively chained, wherein each functional unit contains an operational block and output selection logic that are configured to programmably selectively implement any of a variety of operations (e.g., bitwise, logical, arithmetic, etc.) that may be performed on the outputs of single FSBs and/or several FSBs. In addition to the output routing channel, the PLD may also contain at least one input routing channel that is configured to facilitate the routing, registering, and/or selection of FSB input signals. In some cases, the FSB input routing channel may also include circuitry for performing elementary processing operations.
摘要翻译：提供了一种可编程逻辑器件（PLD），其包括至少一个专用输出路由通道，其被配置为便于处理由多个功能特定块（FSB）产生的输出信号。输出路由信道包括可编程地选择性地链接的多个功能单元，其中每个功能单元包含操作块和输出选择逻辑，其被配置为可编程地选择性地执行各种操作（例如，按位，逻辑，运算等），其可以在单个FSB和/或几个FSB的输出上执行。除了输出路由信道之外，PLD还可以包含至少一个输入路由信道，其被配置为便于FSB输入信号的路由，注册和/或选择。在一些情况下，FSB输入路由信道还可以包括用于执行基本处理操作的电路。

88. 发明授权

US06586966B1 Data latch with low-power bypass mode 有权
标题翻译：低功耗旁路模式的数据锁存器
公开(公告)号：US06586966B1
公开(公告)日：2003-07-01
申请号：US09952223
申请日：2001-09-13
申请人： Gregory Starr , Martin Langhammer , Chiao Kai Hwang
发明人： Gregory Starr , Martin Langhammer , Chiao Kai Hwang
IPC分类号： H03K19177
CPC分类号： H03K3/012 , H03K3/0372
摘要： A bypassable latch circuit consumes less power in the bypass mode than it does in the latched mode. The circuit includes a flip-flop whose output is routed to an input of a multiplexer. The other input of the multiplexer is the input of the flip-flop as well. The multiplexer is used to select as the latch output either the registered or latched flip-flop output, or the flip-flop input. The flip-flop is modified by replacing the inverter at the flip-flop clock input with a logic gate that accepts as inputs both the clock input and a control input. The control input can cause the flip-flop to ignore the clock, preventing switching that consumes power by charging and discharging capacitive elements in the flip-flop.
摘要翻译：在旁路模式下，旁路锁存电路消耗的功率要小于锁存模式。该电路包括一个触发器，其触发器的输出被路由到多路复用器的输入端。多路复用器的另一个输入也是触发器的输入。多路复用器用于选择锁存输出，即注册或锁存的触发器输出或触发器输入。通过用触发器时钟输入替换逆变器来修改触发器，逻辑门接受作为时钟输入和控制输入的输入。控制输入可以使触发器忽略时钟，从而防止通过在触发器中对电容元件充电和放电来消耗功率的开关。

89. 发明授权

US06538470B1 Devices and methods with programmable logic and digital signal processing regions 有权
标题翻译：具有可编程逻辑和数字信号处理区域的器件和方法
公开(公告)号：US06538470B1
公开(公告)日：2003-03-25
申请号：US09955645
申请日：2001-09-18
申请人： Martin Langhammer , Gregory Starr , Chiao Kai Hwang
发明人： Martin Langhammer , Gregory Starr , Chiao Kai Hwang
IPC分类号： H03K19177
CPC分类号： G06F7/5095 , G06F5/015 , G06F7/53 , G06F7/575 , G06F7/724 , G06F15/7867 , G06F2207/3828 , H03K19/17732 , H03K19/17736
摘要： A programmable logic integrated circuit device (“PLD”) includes programmable logic and a dedicated (i.e., at least partly hard-wired) digital signal processing region for performing or at least helping to perform digital signal processing tasks that are unduly inefficient to implement in the more general-purpose programmable logic and/or that, if implemented in the programmable logic, would operate unacceptably or at least undesirably slowly. The digital signal processing region may include multiple digital signal processing stages. The digital signal processing region may include a multiplier stage and one ore more stages that can operate in combination with the multiplier stage. The digital signal processing region has a plurality of modes such as for providing multiply-and-accumulate operation, multiply-and-add operation, etc.
摘要翻译：可编程逻辑集成电路器件（“PLD”）包括可编程逻辑和专用（即，至少部分硬连线）的数字信号处理区域，用于执行或至少帮助执行数字信号处理任务，这些任务执行不当更通用的可编程逻辑和/或如果在可编程逻辑中实现，则可以不可接受地或至少不期望地缓慢地操作。数字信号处理区域可以包括多个数字信号处理级。数字信号处理区域可以包括可以与乘法器级结合操作的乘法器级和一级以上级。数字信号处理区域具有多种模式，例如用于提供乘法和累加操作，乘法和加法运算等。

90. 发明公开

US20230368030A1 BLOCK-WISE PRUNING OF WEIGHTS IN DEEP NEURAL NETWORK 审中-公开
公开(公告)号：US20230368030A1
公开(公告)日：2023-11-16
申请号：US18358571
申请日：2023-07-25
申请人： Arnab Raha , Michael Wu , Deepak Abraham Mathaikutty , Martin Langhammer , Nihat Tunali
发明人： Arnab Raha , Michael Wu , Deepak Abraham Mathaikutty , Martin Langhammer , Nihat Tunali
IPC分类号： G06N3/082 , G06N3/048
CPC分类号： G06N3/082 , G06N3/048
摘要： Weights can be pruned during DNN training to increase sparsity in the weights and reduce the amount of computation required for performing the deep learning operations in DNNs. A DNN layer may have one or more weight tensors corresponding to one or more output channels of the layer. A weight tensor has weights, the values of which are determined by training the DNN. A weight tensor may have a dimension corresponding to the input channels of the layer. The weight tensor may be partitioned into subtensors, each of which has a subset of the input channels. The subtensor may have the same number of input channels. One or more subtensors may be selected, e.g., based on the weights in the one or more subtensors. The weights in a selected subtensor are pruned, e.g., changed to zeros. The weights in an unselected subtensor may be modified by further training the DNN.

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