专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20120011182A1 DECIMAL FLOATING-POINT SQUARE-ROOT UNIT USING NEWTON-RAPHSON ITERATIONS 有权
标题翻译：使用NEWTON-RAPHSON迭代的十进制浮点平方根单元
公开(公告)号：US20120011182A1
公开(公告)日：2012-01-12
申请号：US13177488
申请日：2011-07-06
申请人： Ramy Raafat , Amira Mohamed , Hossam Ali Hassan Fahmy , Yasmeen Farouk , Mostafa Elkhouly , Tarek Eldeeb , Rodina Samy
发明人： Ramy Raafat , Amira Mohamed , Hossam Ali Hassan Fahmy , Yasmeen Farouk , Mostafa Elkhouly , Tarek Eldeeb , Rodina Samy
IPC分类号： G06F7/552 , G06F5/01
CPC分类号： G06F7/5525 , G06F7/491 , G06F2207/5355
摘要： A system including: an input processing unit configured to: extract a significant and a bias exponent from the decimal floating-point radicand; and calculate a normalized significand; a square root unit configured to: calculate, using a FMA unit, a refined reciprocal square-root of the normalized significand; calculate an unrounded square-root of the normalized significand by multiplying the refined reciprocal square-root by the normalized significand; and generate a rounded square-root based on a first difference between the normalized significand and a square of the unrounded square-root; a master control unit operatively connected to the input processing hardware unit and the square-root hardware unit and configured to calculate an exponent for the unrounded square-root based on the number of leading zeros and a precision of the decimal floating-point radicand; and an output formulation unit configured to output a decimal floating-point square-root of the radicand based on the rounded square-root and the exponent.
摘要翻译：一种系统，包括：输入处理单元，被配置为：从十进制浮点radic中提取有效偏移指数和偏差指数; 并计算归一化有效位数; 平方根单元，其被配置为：使用FMA单元计算所述归一化有效位数的精确相互平方根; 通过将精确的倒数平方根乘以归一化有效位数来计算标准化有效位数的未圆角平方根; 并且基于归一化有效位数和未包围的平方根的平方之间的第一差异生成舍入的平方根; 主控制单元，可操作地连接到输入处理硬件单元和平方根硬件单元，并且被配置为基于前导零的数量和十进制浮点数的精度来计算未包围的平方根的指数; 以及输出公式单元，被配置为基于所述舍入的平方根和所述指数输出所述radic的十进制浮点平方根。

2. 发明申请

US20120011181A1 DECIMAL FLOATING-POINT FUSED MULTIPLY-ADD UNIT 有权
标题翻译：十进制浮点补偿多路复用单元
公开(公告)号：US20120011181A1
公开(公告)日：2012-01-12
申请号：US13177549
申请日：2011-07-06
申请人： Rodina Samy , Hossam Ali Hassan Fahmy , Tarek Eldeeb , Ramy Raafat , Yasmeen Farouk , Mostafa Elkhouly , Amira Mohamed
发明人： Rodina Samy , Hossam Ali Hassan Fahmy , Tarek Eldeeb , Ramy Raafat , Yasmeen Farouk , Mostafa Elkhouly , Amira Mohamed
IPC分类号： G06F7/487 , G06F7/499 , G06F7/485
CPC分类号： G06F7/483 , G06F7/491 , G06F7/5443
摘要： A decimal floating-point Fused-Multiply-Add (FMA) unit that performs the operation of ±(A×B)±C on decimal floating-point operands. The decimal floating-point FMA unit executes the multiplication and addition operations compliant with the IEEE 754-2008 standard. Specifically, the decimal floating-point FMA includes a parallel multiplier and injects the addend after required alignment as an additional partial product in the reduction tree used in the parallel multiplier. The decimal floating-point FMA unit may be configured to perform addition-subtraction operations or multiplication operations as standalone operations.
摘要翻译：在十进制浮点运算符上执行±（A×B）±C的运算的十进制浮点Fused-Multiply-Add（FMA）单位。十进制浮点FMA单元执行符合IEEE 754-2008标准的乘法和加法运算。具体来说，十进制浮点FMA包括一个并行乘法器，并将所需对齐后的加数作为并行乘法器中使用的还原树中的附加部分乘积进行注入。十进制浮点FMA单元可以被配置为执行加减运算或乘法运算作为独立运算。

3. 发明申请

US20140101215A1 DPD/BCD TO BID CONVERTERS 有权
标题翻译： DPD / BCD转换器
公开(公告)号：US20140101215A1
公开(公告)日：2014-04-10
申请号：US13644374
申请日：2012-10-04
申请人： Ahmed A. Ayoub , Hossam Aly Hassan Fahmy , Tarek Eldeeb
发明人： Ahmed A. Ayoub , Hossam Aly Hassan Fahmy , Tarek Eldeeb
IPC分类号： G06F7/38
CPC分类号： H03M7/02 , H03M7/12
摘要： A method and system for binary coded decimal (BCD) to binary conversion. The conversion includes obtaining a BCD significand corresponding to multiple decimal digits; generating, by a BCD/binary hardware converter and based on the BCD significand, multiple binary vectors corresponding to the multiple decimal digits; and calculating, by the BCD/binary hardware converter, a binary output by summing the multiple binary vectors.
摘要翻译：二进制编码十进制（BCD）到二进制转换的方法和系统。转换包括获得对应于多个十进制数字的BCD有效位数; 通过BCD /二进制硬件转换器和基于BCD有效位数生成对应于多个十进制数字的多个二进制向量; 并且由BCD /二进制硬件转换器通过对多个二进制向量求和来计算二进制输出。

4. 发明申请

US20120011187A1 PARALLEL REDUNDANT DECIMAL FUSED-MULTIPLY-ADD CIRCUIT 有权
标题翻译：并行冗余多路复用多路复用电路
公开(公告)号：US20120011187A1
公开(公告)日：2012-01-12
申请号：US13177491
申请日：2011-07-06
申请人： Amira Mohamed , Ramy Raafat , Hossam Ali Hassan Fahmy , Tarek Eldeeb , Yasmeen Farouk , Rodina Samy , Mostafa Elkhouly
发明人： Amira Mohamed , Ramy Raafat , Hossam Ali Hassan Fahmy , Tarek Eldeeb , Yasmeen Farouk , Rodina Samy , Mostafa Elkhouly
IPC分类号： G06F7/52 , G06F7/50
CPC分类号： G06F7/492 , G06F7/483 , G06F7/5336 , G06F7/5443 , G06F2207/5355
摘要： A circuit for performing a floating-point fused-multiply-add (FMA) calculation of a×b±c. The circuit includes (i) a partial product generation module having (a) a multiples generator unit configured to generate multiples of a multiplicand has m digit binary coded decimal (BCD) format, (b) a recoding unit configured to generate n+1 signed digits (SD) sets from a sum vector and a carry vector of a multiplier, and (c) a multiples selection unit configured to generate partial product vectors from the multiples of the multiplicand based on the n+1 SD sets and the sign of FMA calculation, and (ii) a carry save adder (CSA) tree configured to add the partial product vectors and an addend to generate a result sum vector and a result carry vector in a m+n digit BCD format.
摘要翻译：用于执行×b±c的浮点融合乘法（FMA）计算的电路。电路包括（i）部分乘积生成模块，其具有（a）多个发生器单元，被配置为生成具有m位二进制编码十进制（BCD）格式的被乘数的倍数，（b）被配置为生成n + 1个符号的重新编码单元数字（SD）从乘法器的和向量和进位向量设置，以及（c）多个选择单元，被配置为基于n + 1个SD集合和FMA的符号从被乘数的倍数生成部分乘积向量计算，以及（ii）进位保存加法器（CSA）树，其被配置为添加部分乘积向量和加数以生成m + n位BCD格式的结果和矢量和结果进位向量。

5. 发明授权

US08805917B2 Parallel redundant decimal fused-multiply-add circuit 有权
标题翻译：并行冗余十进制融合乘法电路
公开(公告)号：US08805917B2
公开(公告)日：2014-08-12
申请号：US13177491
申请日：2011-07-06
申请人： Amira Mohamed , Ramy Raafat , Hossam Ali Hassan Fahmy , Tarek Eldeeb , Yasmeen Farouk , Rodina Samy , Mostafa Elkhouly
发明人： Amira Mohamed , Ramy Raafat , Hossam Ali Hassan Fahmy , Tarek Eldeeb , Yasmeen Farouk , Rodina Samy , Mostafa Elkhouly
IPC分类号： G06F7/48
CPC分类号： G06F7/492 , G06F7/483 , G06F7/5336 , G06F7/5443 , G06F2207/5355
摘要： A circuit for performing a floating-point fused-multiply-add (FMA) calculation of a×b±c. The circuit includes (i) a partial product generation module having (a) a multiples generator unit configured to generate multiples of a multiplicand has m digit binary coded decimal (BCD) format, (b) a recoding unit configured to generate n+1 signed digits (SD) sets from a sum vector and a carry vector of a multiplier, and (c) a multiples selection unit configured to generate partial product vectors from the multiples of the multiplicand based on the n+1 SD sets and the sign of FMA calculation, and (ii) a carry save adder (CSA) tree configured to add the partial product vectors and an addend to generate a result sum vector and a result carry vector in a m+n digit BCD format.
摘要翻译：用于执行×b±c的浮点融合乘法（FMA）计算的电路。电路包括（i）部分乘积生成模块，其具有（a）多个发生器单元，被配置为生成具有m位二进制编码十进制（BCD）格式的被乘数的倍数，（b）被配置为生成n + 1个符号的重新编码单元数字（SD）从乘法器的和向量和进位向量设置，以及（c）多个选择单元，被配置为基于n + 1个SD集合和FMA的符号从被乘数的倍数生成部分乘积向量计算，以及（ii）进位保存加法器（CSA）树，其被配置为添加部分乘积向量和加数以生成m + n位BCD格式的结果和矢量和结果进位向量。

6. 发明授权

US08812575B2 Decimal floating-point square-root unit using Newton-Raphson iterations 有权
标题翻译：使用牛顿 - 拉夫逊迭代的十进制浮点平方根单位
公开(公告)号：US08812575B2
公开(公告)日：2014-08-19
申请号：US13177488
申请日：2011-07-06
申请人： Ramy Raafat , Amira Mohamed , Hossam Ali Hassan Fahmy , Yasmeen Farouk , Mostafa Elkhouly , Tarek Eldeeb , Rodina Samy
发明人： Ramy Raafat , Amira Mohamed , Hossam Ali Hassan Fahmy , Yasmeen Farouk , Mostafa Elkhouly , Tarek Eldeeb , Rodina Samy
IPC分类号： G06F7/552
CPC分类号： G06F7/5525 , G06F7/491 , G06F2207/5355
摘要： A system including: an input processing unit configured to: extract a significant and a bias exponent from the decimal floating-point radicand; and calculate a normalized significand; a square root unit configured to: calculate, using a FMA unit, a refined reciprocal square-root of the normalized significand; calculate an unrounded square-root of the normalized significand by multiplying the refined reciprocal square-root by the normalized significand; and generate a rounded square-root based on a first difference between the normalized significand and a square of the unrounded square-root; a master control unit operatively connected to the input processing hardware unit and the square-root hardware unit and configured to calculate an exponent for the unrounded square-root based on the number of leading zeros and a precision of the decimal floating-point radicand; and an output formulation unit configured to output a decimal floating-point square-root of the radicand based on the rounded square-root and the exponent.
摘要翻译：一种系统，包括：输入处理单元，被配置为：从十进制浮点radic中提取有效偏移指数和偏差指数; 并计算归一化有效位数; 平方根单元，其被配置为：使用FMA单元计算所述归一化有效位数的精确相互平方根; 通过将精确的倒数平方根乘以归一化有效位数来计算标准化有效位数的未圆角平方根; 并且基于归一化有效位数和未包围的平方根的平方之间的第一差异生成舍入的平方根; 主控制单元，可操作地连接到输入处理硬件单元和平方根硬件单元，并且被配置为基于前导零的数量和十进制浮点数的精度来计算未包围的平方根的指数; 以及输出公式单元，被配置为基于所述舍入的平方根和所述指数输出所述radic的十进制浮点平方根。

7. 发明授权

US08788560B2 Decimal elementary functions computation 失效
标题翻译：小数基本函数计算
公开(公告)号：US08788560B2
公开(公告)日：2014-07-22
申请号：US13293061
申请日：2011-11-09
申请人： Tarek Eldeeb , Hossam Aly Hassan Fahmy , Mahmoud Y. Hassan
发明人： Tarek Eldeeb , Hossam Aly Hassan Fahmy , Mahmoud Y. Hassan
IPC分类号： G06F7/38
CPC分类号： G06F7/544 , G06F2207/4911
摘要： A method for executing a decimal elementary function (DEF) computation from multiple decimal floating-point operands, including: extracting mantissae and exponents from the operands; generating normalized mantissae by shifting the mantissae based on the number of leading zeros; calculating a plurality of approximations for a logarithm of the first normalized mantissa; calculating, using the plurality of approximations for the logarithm, a plurality of approximations for a product of the second normalized mantissa and a sum based on the logarithm of the first normalized mantissa and an exponent; generating a plurality of shifted values by shifting the plurality of approximations for the product; generating a plurality of fraction components from the plurality of shifted values; calculating an antilog based on the plurality of fraction components; and outputting a decimal floating-point result of the DEF computation comprising a resultant mantissa based on the antilog and a resultant biased exponent.
摘要翻译：一种用于从多个十进制浮点运算执行十进制基本函数（DEF）计算的方法，包括：从操作数中提取mantissae和exponents; 通过基于前导零的数量移动镰刀生成归一化的镰刀; 计算第一标准化尾数的对数的多个近似值; 使用所述对数的所述近似来计算所述第二标准化尾数与基于所述第一标准化尾数和指数的对数的乘积的乘积的多个近似; 通过移动产品的多个近似来产生多个移位值; 从所述多个移位值生成多个分数分量; 基于多个分数分量计算反对数; 并输出DEF运算的十进制浮点运算结果，该结果包括基于反序号和合成偏移指数的合成尾数。

8. 发明授权

US08751555B2 Rounding unit for decimal floating-point division 有权
标题翻译：十进制浮点除法的舍入单位
公开(公告)号：US08751555B2
公开(公告)日：2014-06-10
申请号：US13177484
申请日：2011-07-06
申请人： Amira Mohamed , Hossam Ali Hassan Fahmy , Ramy Raafat , Yasmeen Farouk , Mostafa Elkhouly , Rodina Samy , Tarek Eldeeb
发明人： Amira Mohamed , Hossam Ali Hassan Fahmy , Ramy Raafat , Yasmeen Farouk , Mostafa Elkhouly , Rodina Samy , Tarek Eldeeb
IPC分类号： G06F7/38
CPC分类号： G06F7/49957 , G06F7/4917 , G06F2207/5355 , G06F2207/5356
摘要： A method for performing a decimal floating-point division, including: receiving, by a decimal floating-point divider, a decimal floating-point dividend and a decimal floating-point divisor; obtaining, by the decimal floating-point divider, a preliminary quotient having a first precision level, where the preliminary quotient is calculated from the decimal floating-point dividend and the decimal-floating point divisor; receiving, by the decimal floating-point divider, a rounding mode; selecting a rounding action based on the preliminary quotient and the rounding mode; and obtaining a rounded quotient having a second precision level by rounding the preliminary quotient according to the rounding action, where the first precision level is at least one digit greater than the second precision level.
摘要翻译：一种用于执行十进制浮点除法的方法，包括：由十进制浮点除法器接收十进制浮点除数和十进制浮点除数; 通过十进制浮点除法器获得具有第一精度水平的初级商，其中从十进制浮点除数和十进制浮点除数计算初步商; 通过十进制浮点分频器接收舍入模式; 基于初步商和舍入模式选择舍入动作; 以及通过根据所述舍入动作舍入所述初级商，获得具有第二精度等级的舍入商，其中所述第一精度级别比所述第二精度级别大至少一位数。

9. 发明授权

US08694572B2 Decimal floating-point fused multiply-add unit 有权
标题翻译：十进制浮点融合乘法单元
公开(公告)号：US08694572B2
公开(公告)日：2014-04-08
申请号：US13177549
申请日：2011-07-06
申请人： Rodina Samy , Hossam Ali Hassan Fahmy , Tarek Eldeeb , Ramy Raafat , Yasmeen Farouk , Mostafa Elkhouly , Amira Mohamed
发明人： Rodina Samy , Hossam Ali Hassan Fahmy , Tarek Eldeeb , Ramy Raafat , Yasmeen Farouk , Mostafa Elkhouly , Amira Mohamed
IPC分类号： G06F7/38
CPC分类号： G06F7/483 , G06F7/491 , G06F7/5443
摘要： A decimal floating-point Fused-Multiply-Add (FMA) unit that performs the operation of ±(A×B)±C on decimal floating-point operands. The decimal floating-point FMA unit executes the multiplication and addition operations compliant with the IEEE 754-2008 standard. Specifically, the decimal floating-point FMA includes a parallel multiplier and injects the addend after required alignment as an additional partial product in the reduction tree used in the parallel multiplier. The decimal floating-point FMA unit may be configured to perform addition-subtraction operations or multiplication operations as standalone operations.
摘要翻译：在十进制浮点运算符上执行±（A×B）±C的运算的十进制浮点Fused-Multiply-Add（FMA）单位。十进制浮点FMA单元执行符合IEEE 754-2008标准的乘法和加法运算。具体来说，十进制浮点FMA包括一个并行乘法器，并将所需对齐后的加数作为并行乘法器中使用的还原树中的附加部分乘积进行注入。十进制浮点FMA单元可以被配置为执行加减运算或乘法运算作为独立运算。

10. 发明申请

US20130117341A1 DECIMAL ELEMENTARY FUNCTIONS COMPUTATION 失效
标题翻译： DECIMAL ELEMENTARY功能计算
公开(公告)号：US20130117341A1
公开(公告)日：2013-05-09
申请号：US13293061
申请日：2011-11-09
申请人： Tarek Eldeeb , Hossam Aly Hassan Fahmy , Mahmoud Y. Hassan
发明人： Tarek Eldeeb , Hossam Aly Hassan Fahmy , Mahmoud Y. Hassan
IPC分类号： G06F7/42 , G06F7/44
CPC分类号： G06F7/544 , G06F2207/4911
摘要： A method for executing a decimal elementary function (DEF) computation from multiple decimal floating-point operands, including: extracting mantissae and exponents from the operands; generating normalized mantissae by shifting the mantissae based on the number of leading zeros; calculating a plurality of approximations for a logarithm of the first normalized mantissa; calculating, using the plurality of approximations for the logarithm, a plurality of approximations for a product of the second normalized mantissa and a sum based on the logarithm of the first normalized mantissa and an exponent; generating a plurality of shifted values by shifting the plurality of approximations for the product; generating a plurality of fraction components from the plurality of shifted values; calculating an antilog based on the plurality of fraction components; and outputting a decimal floating-point result of the DEF computation comprising a resultant mantissa based on the antilog and a resultant biased exponent.
摘要翻译：一种用于从多个十进制浮点运算执行十进制基本函数（DEF）计算的方法，包括：从操作数中提取出mantissae和exponents; 通过基于前导零的数量移动镰刀生成归一化的镰刀; 计算第一标准化尾数的对数的多个近似值; 使用所述对数的所述近似来计算所述第二标准化尾数与基于所述第一标准化尾数和指数的对数的乘积的乘积的多个近似; 通过移动产品的多个近似来产生多个移位值; 从所述多个移位值生成多个分数分量; 基于多个分数分量计算反对数; 并输出DEF运算的十进制浮点运算结果，该结果包括基于反序号和合成偏移指数的合成尾数。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式