专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07805691B2 Semiconductor failure analysis apparatus, failure analysis method, and failure analysis program 有权
标题翻译：半导体故障分析装置，故障分析方法和故障分析程序
公开(公告)号：US07805691B2
公开(公告)日：2010-09-28
申请号：US11586719
申请日：2006-10-26
申请人： Toshiyuki Majima , Akira Shimase , Hirotoshi Terada , Kazuhiro Hotta
发明人： Toshiyuki Majima , Akira Shimase , Hirotoshi Terada , Kazuhiro Hotta
IPC分类号： G06F17/50
CPC分类号： G01R31/311 , G01N21/95607 , G01R31/2894
摘要： A failure analysis apparatus 10 is composed of an inspection information acquirer 11 for acquiring a failure observed image P2 of a semiconductor device, a layout information acquirer 12 for acquiring layout information, and a failure analyzer 13 for analyzing a failure. The failure analyzer 13 extracts candidate nets passing at least one of analysis regions set from the failure observed image, out of a plurality of nets in the semiconductor device, and passage counts of the respective candidate nets through the analysis regions, selects a candidate net with the largest passage count as a first failure net, and selects a second failure net with attention to analysis regions where the first failure net does not pass. This substantializes a semiconductor failure analysis apparatus, failure analysis method, and failure analysis program capable of securely and efficiently performing the analysis of the failure of the semiconductor device using the failure observed image.
摘要翻译：故障分析装置10由用于获取半导体装置的故障观察图像P2的检查信息获取部11，用于获取布局信息的布局信息获取部12以及用于分析故障的故障分析部13构成。故障分析部13从通过半导体装置的多个网络中的故障观察图像，从故障观察图像设定的分析区域中的至少一个以及通过分析区域的各个候选网络的通过计数来提取候补网络，选择候补网络作为第一故障网络的最大通行数，并且选择第二故障网络，注意第一故障网络不通过的分析区域。这实现了半导体故障分析装置，故障分析方法和故障分析程序，其能够安全有效地执行使用故障观察图像的半导体器件的故障的分析。

2. 发明申请

US20070294053A1 Semiconductor failure analysis apparatus, failure analysis method, and failure analysis program 有权
标题翻译：半导体故障分析装置，故障分析方法和故障分析程序
公开(公告)号：US20070294053A1
公开(公告)日：2007-12-20
申请号：US11586719
申请日：2006-10-26
申请人： Toshiyuki Majima , Akira Shimase , Hirotoshi Terada , Kazuhiro Hotta
发明人： Toshiyuki Majima , Akira Shimase , Hirotoshi Terada , Kazuhiro Hotta
IPC分类号： G01R31/00
CPC分类号： G01R31/311 , G01N21/95607 , G01R31/2894
摘要： A failure analysis apparatus 10 is composed of an inspection information acquirer 11 for acquiring a failure observed image P2 of a semiconductor device, a layout information acquirer 12 for acquiring layout information, and a failure analyzer 13 for analyzing a failure. The failure analyzer 13 extracts candidate nets passing at least one of analysis regions set from the failure observed image, out of a plurality of nets in the semiconductor device, and passage counts of the respective candidate nets through the analysis regions, selects a candidate net with the largest passage count as a first failure net, and selects a second failure net with attention to analysis regions where the first failure net does not pass. This substantializes a semiconductor failure analysis apparatus, failure analysis method, and failure analysis program capable of securely and efficiently performing the analysis of the failure of the semiconductor device using the failure observed image.
摘要翻译：失效分析装置10由用于获取半导体器件的故障观察图像P 2的检查信息获取器11，用于获取布局信息的布局信息获取器12以及用于分析故障的故障分析器13组成。故障分析部13从通过半导体装置的多个网络中的故障观察图像，从故障观察图像设定的分析区域中的至少一个以及通过分析区域的各个候选网络的通过计数来提取候补网络，选择候补网络作为第一故障网络的最大通行数，并且选择第二故障网络，注意第一故障网络不通过的分析区域。这实现了半导体故障分析装置，故障分析方法和故障分析程序，其能够安全有效地执行使用故障观察图像的半导体器件的故障的分析。

3. 发明申请

US20070290696A1 Semiconductor failure analysis apparatus, failure analysis method, and failure analysis program 审中-公开
标题翻译：半导体故障分析装置，故障分析方法和故障分析程序
公开(公告)号：US20070290696A1
公开(公告)日：2007-12-20
申请号：US11586720
申请日：2006-10-26
申请人： Toshiyuki Majima , Akira Shimase , Hirotoshi Terada , Kazuhiro Hotta
发明人： Toshiyuki Majima , Akira Shimase , Hirotoshi Terada , Kazuhiro Hotta
IPC分类号： G01R31/302
CPC分类号： G01R31/303
摘要： A failure analysis apparatus 10 is composed of an inspection information acquirer 11 for acquiring a failure observed image P2 of a semiconductor device, a layout information acquirer 12 for acquiring layout information, and a failure analyzer 13 for analyzing a failure of the semiconductor device. The failure analyzer 13 has an analysis region setter for comparing an intensity distribution in the failure observed image with a predetermined intensity threshold to extract a reaction region arising from a failure, and for setting an analysis region used in the failure analysis of the semiconductor device, in correspondence to the reaction region. This substantializes a semiconductor failure analysis apparatus, failure analysis method, and failure analysis program capable of securely and efficiently performing the analysis of the failure of the semiconductor device using the failure observed image.
摘要翻译：故障分析装置10由用于获取半导体器件的故障观察图像P 2的检查信息获取器11，用于获取布局信息的布局信息获取器12以及用于分析半导体器件的故障的故障分析器13构成。故障分析器13具有分析区域设定器，用于将故障观察图像中的强度分布与预定强度阈值进行比较，以提取由故障引起的反应区域，并且用于设定在半导体器件的故障分析中使用的分析区域，对应于反应区域。这实现了半导体故障分析装置，故障分析方法和故障分析程序，其能够安全有效地执行使用故障观察图像的半导体器件的故障的分析。

4. 发明授权

US06507029B1 Sample processing apparatus and method for removing charge on sample through light irradiation 有权
标题翻译：用于通过光照射去除样品上的电荷的样品处理装置和方法
公开(公告)号：US06507029B1
公开(公告)日：2003-01-14
申请号：US09255700
申请日：1999-02-23
申请人： Norimasa Nishimura , Akira Shimase , Junzou Azuma , Asahiro Kuni , Hiroya Koshishiba
发明人： Norimasa Nishimura , Akira Shimase , Junzou Azuma , Asahiro Kuni , Hiroya Koshishiba
IPC分类号： H01J3730
CPC分类号： B82Y15/00 , H01J37/026 , H01J2237/0047 , H01J2237/28
摘要： In an electron particle machine for observing, inspecting, processing or analyzing a semiconductor wafer as a substrate or a sample, a light source is installed in a preparation chamber. A chucking stage for chucking the semiconductor wafer with a chuck using static electricity is provided with parts for connecting to earth such that they are in contact with the chucked semiconductor wafer. After the chuck using static electricity is released after observation, inspection, process or analysis, a surface of the semiconductor wafer and the parts for connecting to earth are irradiated with light from the light source. This provides conductivity to the surface of the semiconductor wafer, so that charge accumulated on the semiconductor wafer is removed from the surface through the parts for connecting to earth.
摘要翻译：在用于观察，检查，处理或分析作为基板或样品的半导体晶片的电子粒子机中，将光源安装在准备室中。使用静电用卡盘夹住半导体晶片的夹持台设置有用于连接到地面的部件，使得它们与夹持的半导体晶片接触。在观察，检查，处理或分析之后释放使用静电的卡盘后，用来自光源的光照射半导体晶片的表面和用于连接到地球的部分。这为半导体晶片的表面提供导电性，从而通过用于连接到地球的部件从表面去除积聚在半导体晶片上的电荷。

5. 发明授权

US06344115B1 Pattern forming method using charged particle beam process and charged particle beam processing system 有权
标题翻译：使用带电粒子束工艺和带电粒子束处理系统的图案形成方法
公开(公告)号：US06344115B1
公开(公告)日：2002-02-05
申请号：US09417996
申请日：1999-10-13
申请人： Junzou Azuma , Akira Shimase , Yuichi Hamamura , Hidemi Koike
发明人： Junzou Azuma , Akira Shimase , Yuichi Hamamura , Hidemi Koike
IPC分类号： C23C1400
CPC分类号： H01J37/18 , C23C16/26 , H01J2237/317
摘要： A pattern forming method using an improved charged particle beam process, and a charged particle beam processing system prevent effectively the corrosion of a workpiece by a reactive gas adsorbed by and adhering to the surface of the workpiece when the workpiece is taken out into the atmosphere after pattern formation. The charged particle beam processing system comprises, as principal components, an ion beam chamber provided with an ion beam optical system, a processing chamber provided with a gas nozzle through which a reactive gas is blown against a workpiece, a load-lock chamber connected through a gate valve to the processing chamber. The load-lock chamber is capable of producing a plasma of an inert gas for processing the surface of the workpiece by sputtering. The workpiece is returned to the load-lock chamber after a pattern has been formed thereon in the processing chamber by reactive processing including irradiating the surface of the workpiece with a charged particle beam in an environment of the reactive gas, and the workpiece is subjected to a plasma process to remove the reactive gas adsorbed by the workpiece during pattern formation and adhering to the workpiece.
摘要翻译：使用改进的带电粒子束工艺的图案形成方法和带电粒子束处理系统，当工件被排出到大气中之后，通过被吸收并附着在工件表面上的反应气体有效地防止工件的腐蚀图案形成。带电粒子束处理系统作为主要部件包括设置有离子束光学系统的离子束室，设置有气体喷嘴的处理室，反应气体通过该喷嘴吹向工件，负载锁定室通过一个闸阀到处理室。负载锁定室能够产生用于通过溅射处理工件的表面的惰性气体的等离子体。在通过反应性处理在处理室中形成图案之后，工件返回到装载锁定室，包括在反应气体的环境中用带电粒子束照射工件的表面，并且对工件进行等离子体处理，以在图案形成期间去除被工件吸附的反应气体并附着到工件上。

6. 发明授权

US5656811A Method for making specimen and apparatus thereof 失效
标题翻译：制作标本及其装置的方法
公开(公告)号：US5656811A
公开(公告)日：1997-08-12
申请号：US490423
申请日：1995-06-14
申请人： Fumikazu Itoh , Toshihiko Nakata , Tohru Ishitani , Akira Shimase , Hiroshi Yamaguchi , Takashi Kamimura
发明人： Fumikazu Itoh , Toshihiko Nakata , Tohru Ishitani , Akira Shimase , Hiroshi Yamaguchi , Takashi Kamimura
IPC分类号： G01B11/06 , B23K15/00 , C23F4/00 , G01N1/28 , G01N1/32 , G01Q60/00 , H01J37/26 , H01J37/28 , H01J37/304 , H01J37/305 , H01J37/317 , H01L21/66 , H01J37/30
CPC分类号： H01J37/3056 , G01N1/32 , H01J37/226 , H01J37/3005 , H01J37/304 , H01J2237/30466 , H01J2237/3114 , H01J2237/31745
摘要： A method for making a specimen for use in observation through a transparent electron microscope, includes a step of milling part of the specimen into a thin film part, which can be observed through a transparent electron microscope, by scanning and irradiating a focused ion beam onto the specimen, a step of observing a mark for detection of a position provided on the specimen as a secondary charged particle image by scanning and irradiating a charged particle beam onto the specimen without irradiating the charged particle beam onto the portion to be milled into the thin film part during the milling, and a step of compensating for positional drift of the focused ion beam during milling in accordance with a result of the observation. The method is carried out by an apparatus which includes irradiation area control means for controlling an irradiation area of the focused ion beam onto the specimen so that a surface of the specimen to be milled into the thin film part is not included in the secondary charged particle image when the secondary charged particle image of the surface, on which the mark for detecting the milling position of the specimen is formed, is displayed by the secondary charged particle image during milling part of the specimen, and compensation means for compensating the positional drift of the focused ion beam during milling in accordance with the mark for detecting the milling position.
摘要翻译：通过透明电子显微镜制造用于观察的试样的方法包括通过扫描和照射聚焦离子束将样品的一部分研磨成薄膜部分的步骤，其可以通过透明电子显微镜观察样品，通过扫描并将带电粒子束照射到样本上而不将所述被加入的颗粒束照射到待研磨的部分上来观察用于检测设置在样品上的位置的标记作为二次带电粒子图像的步骤，在研磨期间的薄膜部分，以及根据观察结果补偿在研磨期间聚焦离子束的位置漂移的步骤。该方法由包括照射区域控制装置的装置进行，该照射区域控制装置用于将聚焦离子束的照射区域控制在样本上，使得待研磨到薄膜部分中的样品的表面不包括在二次带电粒子中当在样品的研磨部分期间，通过二次带电粒子图像显示用于检测样品的研磨位置的标记的表面的二次带电粒子图像的图像，以及用于补偿样品的位置漂移的补偿装置根据用于检测铣削位置的标记在铣削期间聚焦的离子束。

7. 发明授权

US5086015A Method of etching a semiconductor device by an ion beam 失效
标题翻译：通过离子束蚀刻半导体器件的方法
公开(公告)号：US5086015A
公开(公告)日：1992-02-04
申请号：US394364
申请日：1989-08-15
申请人： Fumikazu Itoh , Akira Shimase , Satoshi Haraichi , Takahiko Takahashi , Mikio Hongo
发明人： Fumikazu Itoh , Akira Shimase , Satoshi Haraichi , Takahiko Takahashi , Mikio Hongo
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/3205 , H01L21/768
CPC分类号： H01L21/76802 , Y10S148/046
摘要： A method of etching a semiconductor device having multi-layered wiring by an ion beam is disclosed which method comprises the steps of: extracting a high-intensity ion beam from a high-density ion source; focusing the extracted ion beam; causing the focused ion beam to perform a scanning operation by a voltage applied to a deflection electrode; forming a first hole in the semiconductor device by the focused ion beam to a depth capable of reaching an insulating film formed between upper and lower wiring conductors so that the first hole has a curved bottom corresponding to the undulation of the upper wiring conductor, and the upper wiring conductor is absent at the bottom of the first hole; and scanning a portion of the bottom of the first hole with the focused ion beam to form a second hole in the insulating film to a depth capable of reaching the lower wiring conductor, thereby preventing the shorting between the upper and lower wiring conductors. Further, a method of forming a hole of a predetermined shape at a surface area having a step-like portion of a semiconductor device by an ion beam is disclosed which method comprises a pre-etching step of scanning the high-level region of the step-like portion with the ion beam so that the high-level region becomes equal in level to the low-level region of the step-like portion, and a main step of scanning the whole of the surface area with the ion beam till the hole of the predetermined shape is formed in the semiconductor device.
摘要翻译：公开了一种通过离子束蚀刻具有多层布线的半导体器件的方法，该方法包括以下步骤：从高密度离子源提取高强度离子束; 聚焦提取的离子束; 使聚焦离子束通过施加到偏转电极的电压进行扫描操作; 通过所述聚焦离子束在所述半导体器件中形成第一孔至能够到达形成在上部和下部布线导体之间的绝缘膜的深度，使得所述第一孔具有对应于所述上部布线导体的起伏的弯曲底部，并且上部布线导体在第一个孔的底部不存在; 并用聚焦离子束扫描第一孔的底部的一部分，以在绝缘膜中形成能够到达下布线导体的深度的第二孔，从而防止上布线导体和下布线导体之间的短路。此外，公开了一种通过离子束在具有半导体器件的阶梯状部分的表面区域形成预定形状的孔的方法，该方法包括：扫描步骤的高级区域的预蚀刻步骤具有离子束的部分，使得高级区域变得与阶梯状部分的低级区域相等，并且主要步骤是用离子束扫描整个表面积直到孔在半导体器件中形成预定形状。

8. 发明授权

US07517707B2 Manufacturing method of semiconductor integrated circuit device and probe card 有权
标题翻译：半导体集成电路器件和探针卡的制造方法
公开(公告)号：US07517707B2
公开(公告)日：2009-04-14
申请号：US11783778
申请日：2007-04-12
申请人： Masayoshi Okamoto , Hideyuki Matsumoto , Shingo Yorisaki , Akio Hasebe , Yasuhiro Motoyama , Akira Shimase
发明人： Masayoshi Okamoto , Hideyuki Matsumoto , Shingo Yorisaki , Akio Hasebe , Yasuhiro Motoyama , Akira Shimase
IPC分类号： H01L31/26
CPC分类号： G01R3/00 , G01R1/07307
摘要： Electrical testing is to be performed on a semiconductor integrated circuit device which the test pads formed. To facilitate such testing, the method of manufacture of the semiconductor integrated circuit device employs a probe card which has two or more contact terminals which can contact two or more electrodes. This probe card includes, in opposition to a wiring substrate of the semiconductor integrated circuit device in which a first wiring is formed, a first sheet having two or more contact terminals to contact the two or more electrodes; a second wiring electrically connected to the two or more contact terminals and the first wiring; and first dummy wirings which are near the region of formation of the two or more contact terminals, are arranged to a non-forming region of the second wiring, and do not participate in signal transfer.
摘要翻译：电测试将在形成测试焊盘的半导体集成电路器件上进行。为了便于这种测试，半导体集成电路器件的制造方法采用具有两个或更多个能够接触两个或更多个电极的接触端子的探针卡。该探针卡与形成有第一布线的半导体集成电路器件的布线基板相对应，具有接触两个以上的电极的两个以上的接触端子的第一片; 电连接到所述两个或更多个接触端子和所述第一布线的第二布线; 并且在两个或多个接触端子的形成区域附近的第一虚拟布线被布置到第二布线的非形成区域，并且不参与信号传递。

9. 发明授权

US07301146B2 Probe driving method, and probe apparatus 有权
标题翻译：探头驱动方法和探头装置
公开(公告)号：US07301146B2
公开(公告)日：2007-11-27
申请号：US11201222
申请日：2005-08-11
申请人： Satoshi Tomimatsu , Hidemi Koike , Junzo Azuma , Tohru Ishitani , Aritoshi Sugimoto , Yuichi Hamamura , Isamu Sekihara , Akira Shimase
发明人： Satoshi Tomimatsu , Hidemi Koike , Junzo Azuma , Tohru Ishitani , Aritoshi Sugimoto , Yuichi Hamamura , Isamu Sekihara , Akira Shimase
IPC分类号： G01N23/00 , G21K7/00
CPC分类号： G01Q10/06 , G01N23/04 , G01N23/225 , G01R31/2886 , G01R31/311 , H01J37/28
摘要： A probe driving method and a probe apparatus for bringing a probe into contact with the surface of a sample in a safe and efficient manner by monitoring the probe height. Information about the height of the probe from the sample surface is obtained by detecting a probe shadow (54) appearing immediately before the probe contacts the sample, or based on a change in relative positions of a probe image and a sample image that are formed as an ion beam is irradiated diagonally.
摘要翻译：探针驱动方法和探针装置，用于通过监测探针高度，以安全和有效的方式使探针与样品的表面接触。通过检测在探针接触样品之前出现的探针阴影（54），或者基于探针图像和样品图像的相对位置的变化，获得关于来自样品表面的探针的高度的信息，对角线照射离子束。

10. 发明申请

US20070190671A1 Manufacturing method of semiconductor integrated circuit device and probe card 有权
标题翻译：半导体集成电路器件和探针卡的制造方法
公开(公告)号：US20070190671A1
公开(公告)日：2007-08-16
申请号：US11783778
申请日：2007-04-12
申请人： Masayoshi Okamoto , Hideyuki Matsumoto , Shingo Yorisaki , Akio Hasebe , Yasuhiro Motoyama , Akira Shimase
发明人： Masayoshi Okamoto , Hideyuki Matsumoto , Shingo Yorisaki , Akio Hasebe , Yasuhiro Motoyama , Akira Shimase
IPC分类号： H01L21/66
CPC分类号： G01R3/00 , G01R1/07307
摘要： Electrical testing is to be performed on a semiconductor integrated circuit device which the test pads formed. To facilitate such testing, the method of manufacture of the semiconductor integrated circuit device employs a probe card which has two or more contact terminals which can contact two or more electrodes. This probe card includes, in opposition to a wiring substrate of the semiconductor integrated circuit device in which a first wiring is formed, a first sheet having two or more contact terminals to contact the two or more electrodes; a second wiring electrically connected to the two or more contact terminals and the first wiring; and first dummy wirings which are near the region of formation of the two or more contact terminals, are arranged to a non-forming region of the second wiring, and do not participate in signal transfer.
摘要翻译：电测试将在形成测试焊盘的半导体集成电路器件上进行。为了便于这种测试，半导体集成电路器件的制造方法采用具有两个或更多个能够接触两个或更多个电极的接触端子的探针卡。该探针卡与形成有第一布线的半导体集成电路器件的布线基板相对应，具有接触两个以上的电极的两个以上的接触端子的第一片; 电连接到所述两个或更多个接触端子和所述第一布线的第二布线; 并且在两个或多个接触端子的形成区域附近的第一虚拟布线被布置到第二布线的非形成区域，并且不参与信号传递。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式