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1. 发明授权

US08010875B2 Error correcting code with chip kill capability and power saving enhancement 有权
标题翻译：错误纠正代码具有芯片杀死能力和节能增强
公开(公告)号：US08010875B2
公开(公告)日：2011-08-30
申请号：US11768559
申请日：2007-06-26
申请人： Alan G. Gara , Dong Chen , Paul W. Coteus , William T. Flynn , James A. Marcella , Todd Takken , Barry M. Trager , Shmuel Winograd
发明人： Alan G. Gara , Dong Chen , Paul W. Coteus , William T. Flynn , James A. Marcella , Todd Takken , Barry M. Trager , Shmuel Winograd
IPC分类号： G06F11/10
CPC分类号： G06F11/1012
摘要： A method and system are disclosed for detecting memory chip failure in a computer memory system. The method comprises the steps of accessing user data from a set of user data chips, and testing the user data for errors using data from a set of system data chips. This testing is done by generating a sequence of check symbols from the user data, grouping the user data into a sequence of data symbols, and computing a specified sequence of syndromes. If all the syndromes are zero, the user data has no errors. If one of the syndromes is non-zero, then a set of discriminator expressions are computed, and used to determine whether a single or double symbol error has occurred. In the preferred embodiment, less than two full system data chips are used for testing and correcting the user data.
摘要翻译：公开了一种用于检测计算机存储器系统中的存储器芯片故障的方法和系统。该方法包括以下步骤：从一组用户数据芯片访问用户数据，以及使用来自一组系统数据芯片的数据来测试用户数据的错误。该测试通过从用户数据生成检查符号序列来完成，将用户数据分组成数据符号序列，并计算指定的综合征序列。如果所有的综合征为零，则用户数据没有错误。如果其中一个校正子不为零，则计算一组鉴别符表达式，并用于确定是否发生单个或双重符号错误。在优选实施例中，使用少于两个全系统数据芯片来测试和校正用户数据。

2. 发明申请

US20090006899A1 ERROR CORRECTING CODE WITH CHIP KILL CAPABILITY AND POWER SAVING ENHANCEMENT 有权
标题翻译：错误修正代码与芯片杀伤能力和省电增强
公开(公告)号：US20090006899A1
公开(公告)日：2009-01-01
申请号：US11768559
申请日：2007-06-26
申请人： Alan G. Gara , Dong Chen , Paul W. Coteus , William T. Flynn , James A. Marcella , Todd Takken , Barry M. Trager , Shmuel Winograd
发明人： Alan G. Gara , Dong Chen , Paul W. Coteus , William T. Flynn , James A. Marcella , Todd Takken , Barry M. Trager , Shmuel Winograd
IPC分类号： G06F11/26 , G06F11/16
CPC分类号： G06F11/1012
摘要： A method and system are disclosed for detecting memory chip failure in a computer memory system. The method comprises the steps of accessing user data from a set of user data chips, and testing the user data for errors using data from a set of system data chips. This testing is done by generating a sequence of check symbols from the user data, grouping the user data into a sequence of data symbols, and computing a specified sequence of syndromes. If all the syndromes are zero, the user data has no errors. If one of the syndromes is non-zero, then a set of discriminator expressions are computed, and used to determine whether a single or double symbol error has occurred. In the preferred embodiment, less than two full system data chips are used for testing and correcting the user data.
摘要翻译：公开了一种用于检测计算机存储器系统中的存储器芯片故障的方法和系统。该方法包括以下步骤：从一组用户数据芯片访问用户数据，以及使用来自一组系统数据芯片的数据来测试用户数据的错误。该测试通过从用户数据生成检查符号序列来完成，将用户数据分组成数据符号序列，并计算指定的综合征序列。如果所有的综合征为零，则用户数据没有错误。如果其中一个校正子不为零，则计算一组鉴别符表达式，并用于确定是否发生单个或双重符号错误。在优选实施例中，使用少于两个全系统数据芯片来测试和校正用户数据。

3. 发明申请

US20100293436A1 System for Error Control Coding for Memories of Different Types and Associated Methods 有权
标题翻译：用于不同类型和相关方法的记忆的错误控制编码系统
公开(公告)号：US20100293436A1
公开(公告)日：2010-11-18
申请号：US12023408
申请日：2008-01-31
申请人： Paul W. Coteus , Luis A. Lastras-Montano , Warren Edward Maule , Barry M. Trager , Shmuel Winograd
发明人： Paul W. Coteus , Luis A. Lastras-Montano , Warren Edward Maule , Barry M. Trager , Shmuel Winograd
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/1545 , G06F11/1048 , H03M13/1515 , H03M13/154 , H03M13/35 , H03M13/353 , H03M13/3707 , H03M13/6511 , H03M13/6516
摘要： A system to improve error control coding may include memory chips of at least two different kinds. The system may also include error control encoder circuitry to substantially encode data for storage in any memory rank. The system may further include error control decoder circuitry to substantially decode encoded data received from any memory rank. The error decoder circuitry is comprised of a slow decoder and a fast decoder.
摘要翻译：改进误差控制编码的系统可以包括至少两种不同种类的存储器芯片。该系统还可以包括错误控制编码器电路，用于基本上编码数据以存储在任何存储器等级中。系统还可以包括错误控制解码器电路，以基本上解码从任何存储器级接收的编码数据。错误解码器电路由慢解码器和快速解码器组成。

4. 发明授权

US08185800B2 System for error control coding for memories of different types and associated methods 有权
标题翻译：用于不同类型和相关方法的存储器的错误控制编码系统
公开(公告)号：US08185800B2
公开(公告)日：2012-05-22
申请号：US12023408
申请日：2008-01-31
申请人： Paul W. Coteus , Luis A. Lastras-Montano , Warren Edward Maule , Barry M. Trager , Shmuel Winograd
发明人： Paul W. Coteus , Luis A. Lastras-Montano , Warren Edward Maule , Barry M. Trager , Shmuel Winograd
IPC分类号： G11C29/00
CPC分类号： H03M13/1545 , G06F11/1048 , H03M13/1515 , H03M13/154 , H03M13/35 , H03M13/353 , H03M13/3707 , H03M13/6511 , H03M13/6516
摘要： A system to improve error control coding. An example system includes memory chips of at least two different kinds. The system also includes error control encoder circuitry to substantially encode data for storage in any memory rank. The system further includes error control decoder circuitry to substantially decode encoded data received from any memory rank. The error decoder circuitry is comprised of a slow decoder and a fast decoder.
摘要翻译：一种改进错误控制编码的系统。示例系统包括至少两种不同类型的存储器芯片。该系统还包括错误控制编码器电路，用于基本上编码数据以存储在任何存储器级中。该系统还包括错误控制解码器电路，以基本上解码从任何存储器等级接收的编码数据。错误解码器电路由慢解码器和快速解码器组成。

5. 发明授权

US09128868B2 System for error decoding with retries and associated methods 有权
标题翻译：用于通过重试和相关方法进行错误解码的系统
公开(公告)号：US09128868B2
公开(公告)日：2015-09-08
申请号：US12023356
申请日：2008-01-31
申请人： Luis A. Lastras-Montano , Piyush C. Patel , Eric E. Retter , Barry M. Trager , Michael R. Trombley , Shmuel Winograd
发明人： Luis A. Lastras-Montano , Piyush C. Patel , Eric E. Retter , Barry M. Trager , Michael R. Trombley , Shmuel Winograd
IPC分类号： G06F11/08 , G06F11/14 , H04W28/04 , H04W4/00 , G06F11/10
CPC分类号： G06F11/1044 , G06F11/08 , G06F11/14 , H04W4/00 , H04W28/04
摘要： A system to improve error code decoding with retries may include a processing unit that requests data packets, and a queue to hold the data packets for the processing unit. The system may also include a decoder to determine a processing time for each data packet in the queue based upon any errors in each data packet, and if the processing time for a particular data packet is greater than a threshold, then to renew any requests for the data packets that are in the queue.
摘要翻译：通过重试来改进错误代码解码的系统可以包括请求数据分组的处理单元和用于保存用于处理单元的数据分组的队列。系统还可以包括解码器，用于基于每个数据分组中的任何错误来确定队列中每个数据分组的处理时间，并且如果特定数据分组的处理时间大于阈值，则更新对于队列中的数据包。

6. 发明授权

US08615689B2 Correcting errors in longitudinal position (LPOS) words 有权
标题翻译：校正纵向位置误差（LPOS）词
公开(公告)号：US08615689B2
公开(公告)日：2013-12-24
申请号：US13612396
申请日：2012-09-12
申请人： William J. Kabelac , Barry M. Trager , Shmuel Winograd
发明人： William J. Kabelac , Barry M. Trager , Shmuel Winograd
IPC分类号： G11C29/00
CPC分类号： G11B27/107 , G11B27/24 , G11B27/36 , G11B2220/93
摘要： A method for longitudinal position (LPOS) detection in a magnetic tape storage system for storing data upon linear tape open (LTO) magnetic storage tape, which data includes odd and even 36-bit LPOS words with error correcting ability. The method includes first encoding positional information onto the tape within the 36-bit LPOS words using each LPOS word's 8-bit sync mark field, and six of each LPOS word's 4-bit symbol fields, wherein 6 of 24 total bits comprise the encoded 8-bit sync mark field: Sy, and six 4-bit symbol fields are utilized as parity bits. The magnetic tape storage system passes the LTO magnetic storage tape encoded with the odd and even LPOS words with error correcting ability longitudinally across a servo reader/writer at a known speed, decoding the encoded positional information and detecting and correcting both ambiguous bits and single erroneous bit errors.
摘要翻译：一种用于在线性磁带打开（LTO）磁存储磁带上存储数据的磁带存储系统中的纵向位置（LPOS）检测方法，该数据包括具有纠错能力的奇数和偶数36位LPOS字。该方法包括使用每个LPOS字的8位同步标记字段以及每个LPOS字的4位符号字段中的六个，在36位LPOS字中的位置信息之上编码位置信息，其中24个总比特中的6个包括编码的8 位同步标记字段：Sy和六个4位符号字段用作奇偶校验位。磁带存储系统以已知速度将穿过伺服读取器/写入器的具有纠错能力的奇数和偶数LPOS字编码的LTO磁存储带纵向跨越伺服读取器/写入器，对编码的位置信息进行解码，并检测和校正两个不明确的位和单个错误位错误。

7. 发明申请

US20130198705A1 CIRCUIT VERIFICATION USING COMPUTATIONAL ALGEBRAIC GEOMETRY 有权
标题翻译：使用计算代数几何的电路验证
公开(公告)号：US20130198705A1
公开(公告)日：2013-08-01
申请号：US13360083
申请日：2012-01-27
申请人： Gradus (Geert) Janssen , Luis Lastras-Montano , Alexey Y. Lvov , Viresh Paruthi , Robert Shadowen , Barry M. Trager , Shmuel Winograd , Ali El-Zein
发明人： Gradus (Geert) Janssen , Luis Lastras-Montano , Alexey Y. Lvov , Viresh Paruthi , Robert Shadowen , Barry M. Trager , Shmuel Winograd , Ali El-Zein
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： In one exemplary embodiment of the invention, a method includes: receiving a first description for a circuit whose operation over a plurality of inputs is to be verified; receiving a second description for expected behavior of the circuit, where the expected behavior in the second description is expressed as a set of algebraic systems of multivariable polynomials over at least one Galois field; applying at least one computational algebraic geometry technique to a combination of the first description and the second description to determine whether the circuit is verified, where verification of the circuit confirms that at least one output obtained based on the first description corresponds to at least one expected value based on the expected behavior expressed in the second description; and outputting an indication as to whether the circuit is verified.
摘要翻译：在本发明的一个示例性实施例中，一种方法包括：接收对要对其进行验证的多个输入的操作的电路的第一描述; 接收对所述电路的预期行为的第二描述，其中所述第二描述中的预期行为被表示为在至少一个伽罗瓦域上的多变量多项式的代数系统集合; 将至少一个计算代数几何技术应用于第一描述和第二描述的组合以确定电路是否被验证，其中电路的验证确认基于第一描述获得的至少一个输出对应于至少一个预期的基于在第二描述中表达的预期行为的价值; 并且输出关于电路是否被验证的指示。

8. 发明授权

US08352806B2 System to improve memory failure management and associated methods 失效
标题翻译：系统改善内存故障管理及相关方法
公开(公告)号：US08352806B2
公开(公告)日：2013-01-08
申请号：US12023498
申请日：2008-01-31
申请人： Marc A. Gollub , Luis A. Lastras-Montano , Piyush C. Patel , Eric E. Retter , Barry M. Trager , Shmuel Winograd , Kenneth L. Wright
发明人： Marc A. Gollub , Luis A. Lastras-Montano , Piyush C. Patel , Eric E. Retter , Barry M. Trager , Shmuel Winograd , Kenneth L. Wright
IPC分类号： G06F11/00
CPC分类号： H03M13/1545 , G06F11/1048 , H03M13/1515 , H03M13/154 , H03M13/353 , H03M13/3707 , H03M13/6511
摘要： A system to improve memory failure management may include memory, and an error control decoder to determine failures in the memory. The system may also include an agent that may monitor failures in the memory. The system may further include a table where the error control decoder may record the failures, and where the agent can read and write to.
摘要翻译：改善存储器故障管理的系统可以包括存储器和用于确定存储器中的故障的错误控制解码器。系统还可以包括可以监视存储器中的故障的代理。该系统还可以包括一个表，其中错误控制解码器可以记录故障，以及代理可以在哪里读写。

9. 发明授权

US08176391B2 System to improve miscorrection rates in error control code through buffering and associated methods 失效
标题翻译：系统通过缓冲和相关方法提高错误控制代码中的错误率
公开(公告)号：US08176391B2
公开(公告)日：2012-05-08
申请号：US12023516
申请日：2008-01-31
申请人： Irving G. Baysah , Timothy J. Dell , Luis A. Lastras-Montano , Warren E. Maule , Eric E. Retter , Barry M. Trager , Michael R. Trombley , Shmuel Winograd , Kenneth L. Wright
发明人： Irving G. Baysah , Timothy J. Dell , Luis A. Lastras-Montano , Warren E. Maule , Eric E. Retter , Barry M. Trager , Michael R. Trombley , Shmuel Winograd , Kenneth L. Wright
IPC分类号： H03M13/00
CPC分类号： G06F11/1044
摘要： A system to improve miscorrection rates in error control code may include an error control decoder with a safe decoding mode that processes at least two data packets. The system may also include a buffer to receive the processed at least two data packets from the error control decoder. The error control decoder may apply a logic OR operation to the uncorrectable error signal related to the processing of the at least two data packets to produce a global uncorrectable error signal. The system may further include a recipient to receive the at least two data packets and the global uncorrectable error signal.
摘要翻译：用于改善错误控制代码中的错误率的系统可以包括处理至少两个数据分组的具有安全解码模式的错误控制解码器。系统还可以包括缓冲器，以从误差控制解码器接收经处理的至少两个数据分组。误差控制解码器可以对与至少两个数据分组的处理相关的不可校正误差信号应用逻辑或运算，以产生全局不可校正的误差信号。系统还可以包括接收器以接收至少两个数据分组和全局不可校正的误差信号。

10. 发明授权

US08640065B2 Circuit verification using computational algebraic geometry 有权
标题翻译：使用计算代数几何的电路验证
公开(公告)号：US08640065B2
公开(公告)日：2014-01-28
申请号：US13360083
申请日：2012-01-27
申请人： Gradus (Geert) Janssen , Luis Lastras-Montano , Alexey Y. Lvov , Viresh Paruthi , Robert Shadowen , Barry M. Trager , Shmuel Winograd , Ali El-Zein
发明人： Gradus (Geert) Janssen , Luis Lastras-Montano , Alexey Y. Lvov , Viresh Paruthi , Robert Shadowen , Barry M. Trager , Shmuel Winograd , Ali El-Zein
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/504
摘要： In one exemplary embodiment of the invention, a method includes: receiving a first description for a circuit whose operation over a plurality of inputs is to be verified; receiving a second description for expected behavior of the circuit, where the expected behavior in the second description is expressed as a set of algebraic systems of multivariable polynomials over at least one Galois field; applying at least one computational algebraic geometry technique to a combination of the first description and the second description to determine whether the circuit is verified, where verification of the circuit confirms that at least one output obtained based on the first description corresponds to at least one expected value based on the expected behavior expressed in the second description; and outputting an indication as to whether the circuit is verified.
摘要翻译：在本发明的一个示例性实施例中，一种方法包括：接收对要对其进行验证的多个输入的操作的电路的第一描述; 接收对所述电路的预期行为的第二描述，其中所述第二描述中的预期行为被表示为在至少一个伽罗瓦域上的多变量多项式的代数系统集合; 将至少一个计算代数几何技术应用于第一描述和第二描述的组合以确定电路是否被验证，其中电路的验证确认基于第一描述获得的至少一个输出对应于至少一个预期的基于在第二描述中表达的预期行为的价值; 并且输出关于电路是否被验证的指示。

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