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1. 发明授权

US08010875B2 Error correcting code with chip kill capability and power saving enhancement 有权
标题翻译：错误纠正代码具有芯片杀死能力和节能增强
公开(公告)号：US08010875B2
公开(公告)日：2011-08-30
申请号：US11768559
申请日：2007-06-26
申请人： Alan G. Gara , Dong Chen , Paul W. Coteus , William T. Flynn , James A. Marcella , Todd Takken , Barry M. Trager , Shmuel Winograd
发明人： Alan G. Gara , Dong Chen , Paul W. Coteus , William T. Flynn , James A. Marcella , Todd Takken , Barry M. Trager , Shmuel Winograd
IPC分类号： G06F11/10
CPC分类号： G06F11/1012
摘要： A method and system are disclosed for detecting memory chip failure in a computer memory system. The method comprises the steps of accessing user data from a set of user data chips, and testing the user data for errors using data from a set of system data chips. This testing is done by generating a sequence of check symbols from the user data, grouping the user data into a sequence of data symbols, and computing a specified sequence of syndromes. If all the syndromes are zero, the user data has no errors. If one of the syndromes is non-zero, then a set of discriminator expressions are computed, and used to determine whether a single or double symbol error has occurred. In the preferred embodiment, less than two full system data chips are used for testing and correcting the user data.
摘要翻译：公开了一种用于检测计算机存储器系统中的存储器芯片故障的方法和系统。该方法包括以下步骤：从一组用户数据芯片访问用户数据，以及使用来自一组系统数据芯片的数据来测试用户数据的错误。该测试通过从用户数据生成检查符号序列来完成，将用户数据分组成数据符号序列，并计算指定的综合征序列。如果所有的综合征为零，则用户数据没有错误。如果其中一个校正子不为零，则计算一组鉴别符表达式，并用于确定是否发生单个或双重符号错误。在优选实施例中，使用少于两个全系统数据芯片来测试和校正用户数据。

2. 发明申请

US20090006899A1 ERROR CORRECTING CODE WITH CHIP KILL CAPABILITY AND POWER SAVING ENHANCEMENT 有权
标题翻译：错误修正代码与芯片杀伤能力和省电增强
公开(公告)号：US20090006899A1
公开(公告)日：2009-01-01
申请号：US11768559
申请日：2007-06-26
申请人： Alan G. Gara , Dong Chen , Paul W. Coteus , William T. Flynn , James A. Marcella , Todd Takken , Barry M. Trager , Shmuel Winograd
发明人： Alan G. Gara , Dong Chen , Paul W. Coteus , William T. Flynn , James A. Marcella , Todd Takken , Barry M. Trager , Shmuel Winograd
IPC分类号： G06F11/26 , G06F11/16
CPC分类号： G06F11/1012
摘要： A method and system are disclosed for detecting memory chip failure in a computer memory system. The method comprises the steps of accessing user data from a set of user data chips, and testing the user data for errors using data from a set of system data chips. This testing is done by generating a sequence of check symbols from the user data, grouping the user data into a sequence of data symbols, and computing a specified sequence of syndromes. If all the syndromes are zero, the user data has no errors. If one of the syndromes is non-zero, then a set of discriminator expressions are computed, and used to determine whether a single or double symbol error has occurred. In the preferred embodiment, less than two full system data chips are used for testing and correcting the user data.
摘要翻译：公开了一种用于检测计算机存储器系统中的存储器芯片故障的方法和系统。该方法包括以下步骤：从一组用户数据芯片访问用户数据，以及使用来自一组系统数据芯片的数据来测试用户数据的错误。该测试通过从用户数据生成检查符号序列来完成，将用户数据分组成数据符号序列，并计算指定的综合征序列。如果所有的综合征为零，则用户数据没有错误。如果其中一个校正子不为零，则计算一组鉴别符表达式，并用于确定是否发生单个或双重符号错误。在优选实施例中，使用少于两个全系统数据芯片来测试和校正用户数据。

3. 发明授权

US09081501B2 Multi-petascale highly efficient parallel supercomputer 有权
标题翻译：多千兆高效并行超级计算机
公开(公告)号：US09081501B2
公开(公告)日：2015-07-14
申请号：US13004007
申请日：2011-01-10
申请人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
发明人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
IPC分类号： G06F15/173 , G06F9/06 , G06F15/76
CPC分类号： G06F13/287 , G06F9/06 , G06F9/3004 , G06F9/30047 , G06F9/3885 , G06F12/0811 , G06F12/0831 , G06F12/0862 , G06F12/0864 , G06F12/1027 , G06F15/17381 , G06F15/17387 , G06F15/76 , G06F15/8069 , G06F2212/1016 , G06F2212/602 , G06F2212/6022 , G06F2212/6024 , G06F2212/6032 , Y02D10/13 , Y02D10/14
摘要： A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.
摘要翻译：具有100 petaOPS规模计算的多Petascale高效并行超级计算机，其成本，功耗和占地面积都在降低，并且允许从互连角度来看处理节点的最大封装密度。超级计算机利用了VLSI的技术进步，实现了许多处理器可以集成到单个专用集成电路（ASIC）中的计算模型。每个ASIC计算节点包括利用集成到一个管芯中的四个或更多个处理器的片上系统ASIC，每个处理器具有对所有系统资源的完全访问，并且使得处理器能够对诸如计算或消息传递I / O 并且优选地，根据应用内的各种算法阶段实现功能的自适应分割，或者如果I / O或其他处理器未被充分利用，则可以参与计算或通信节点通过五维环面网络互连使用DMA来最大限度地最大化节点之间的分组通信的吞吐量并最小化等待时间。

4. 发明申请

US20110219208A1 MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER 有权
标题翻译：多层高效平行超级计算机
公开(公告)号：US20110219208A1
公开(公告)日：2011-09-08
申请号：US13004007
申请日：2011-01-10
申请人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
发明人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
IPC分类号： G06F15/76 , G06F9/06
CPC分类号： G06F13/287 , G06F9/06 , G06F9/3004 , G06F9/30047 , G06F9/3885 , G06F12/0811 , G06F12/0831 , G06F12/0862 , G06F12/0864 , G06F12/1027 , G06F15/17381 , G06F15/17387 , G06F15/76 , G06F15/8069 , G06F2212/1016 , G06F2212/602 , G06F2212/6022 , G06F2212/6024 , G06F2212/6032 , Y02D10/13 , Y02D10/14
摘要： A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.
摘要翻译：具有100 petaOPS规模计算的多Petascale高效并行超级计算机，其成本，功耗和占地面积都在降低，并且允许从互连角度来看处理节点的最大封装密度。超级计算机利用了VLSI的技术进步，实现了许多处理器可以集成到单个专用集成电路（ASIC）中的计算模型。每个ASIC计算节点包括利用集成到一个管芯中的四个或更多个处理器的片上系统ASIC，每个处理器具有对所有系统资源的完全访问，并且使得处理器能够对诸如计算或消息传递I / O 并且优选地，根据应用内的各种算法阶段实现功能的自适应分割，或者如果I / O或其他处理器未被充分利用，则可以参与计算或通信节点通过五维环面网络互连使用DMA来最大限度地最大化节点之间的分组通信的吞吐量并最小化等待时间。

5. 发明申请

US20090006730A1 DATA EYE MONITOR METHOD AND APPARATUS 失效
标题翻译：数据眼观察方法和装置
公开(公告)号：US20090006730A1
公开(公告)日：2009-01-01
申请号：US11768810
申请日：2007-06-26
申请人： Alan G. Gara , James A. Marcella , Martin Ohmacht
发明人： Alan G. Gara , James A. Marcella , Martin Ohmacht
IPC分类号： G06F12/00
CPC分类号： G06F13/1689
摘要： An apparatus and method for providing a data eye monitor. The data eye monitor apparatus utilizes an inverter/latch string circuit and a set of latches to save the data eye for providing an infinite persistent data eye. In operation, incoming read data signals are adjusted in the first stage individually and latched to provide the read data to the requesting unit. The data is also simultaneously fed into a balanced XOR tree to combine the transitions of all incoming read data signals into a single signal. This signal is passed along a delay chain and tapped at constant intervals. The tap points are fed into latches, capturing the transitions at a delay element interval resolution. Using XORs, differences between adjacent taps and therefore transitions are detected. The eye is defined by segments that show no transitions over a series of samples. The eye size and position can be used to readjust the delay of incoming signals and/or to control environment parameters like voltage, clock speed and temperature.
摘要翻译：一种用于提供数据眼监护仪的装置和方法。数据眼监视装置利用逆变器/锁存器串电路和一组锁存器来保存数据，以提供无限持续数据眼。在操作中，输入的读数据信号在第一阶段被单独地调整并被锁存以将读取的数据提供给请求单元。数据也被同时馈送到平衡XOR树中，以将所有输入的读取数据信号的转换组合成单个信号。该信号沿着延迟链传递，并以恒定间隔敲击。抽头点被馈送到锁存器，以延迟元件间隔分辨率捕获转换。使用XOR，检测相邻抽头之间的差异，因此检测到转换之间的差异。眼睛由在一系列样本上没有显示转换的片段定义。眼睛大小和位置可用于重新调整输入信号的延迟和/或控制环境参数，如电压，时钟速度和温度。

6. 发明授权

US08108738B2 Data eye monitor method and apparatus 失效
标题翻译：数据眼监护仪方法及装置
公开(公告)号：US08108738B2
公开(公告)日：2012-01-31
申请号：US11768810
申请日：2007-06-26
申请人： Alan G. Gara , James A. Marcella , Martin Ohmacht
发明人： Alan G. Gara , James A. Marcella , Martin Ohmacht
IPC分类号： G06K5/04 , G11B5/00 , G11B20/20
CPC分类号： G06F13/1689
摘要： An apparatus and method for providing a data eye monitor. The data eye monitor apparatus utilizes an inverter/latch string circuit and a set of latches to save the data eye for providing an infinite persistent data eye. In operation, incoming read data signals are adjusted in the first stage individually and latched to provide the read data to the requesting unit. The data is also simultaneously fed into a balanced XOR tree to combine the transitions of all incoming read data signals into a single signal. This signal is passed along a delay chain and tapped at constant intervals. The tap points are fed into latches, capturing the transitions at a delay element interval resolution. Using XORs, differences between adjacent taps and therefore transitions are detected. The eye is defined by segments that show no transitions over a series of samples. The eye size and position can be used to readjust the delay of incoming signals and/or to control environment parameters like voltage, clock speed and temperature.
摘要翻译：一种用于提供数据眼监护仪的装置和方法。数据眼监视装置利用逆变器/锁存器串电路和一组锁存器来保存数据，以提供无限持续数据眼。在操作中，输入的读数据信号在第一阶段被单独地调整并被锁存以将读取的数据提供给请求单元。数据也被同时馈送到平衡XOR树中，以将所有输入的读取数据信号的转换组合成单个信号。该信号沿着延迟链传递，并以恒定间隔敲击。抽头点被馈送到锁存器，以延迟元件间隔分辨率捕获转换。使用XOR，检测相邻抽头之间的差异，因此检测到转换之间的差异。眼睛由在一系列样本上没有显示转换的片段定义。眼睛大小和位置可用于重新调整输入信号的延迟和/或控制环境参数，如电压，时钟速度和温度。

7. 发明授权

US08954683B2 Translation table and method for compressed data 有权
标题翻译：压缩数据的翻译表和方法
公开(公告)号：US08954683B2
公开(公告)日：2015-02-10
申请号：US13587246
申请日：2012-08-16
申请人： Bulent Abali , James A. Marcella , Michael Mi Tsao , Steven M. Wheeler
发明人： Bulent Abali , James A. Marcella , Michael Mi Tsao , Steven M. Wheeler
IPC分类号： G06F12/00
CPC分类号： G06F12/10 , G06F12/0292 , G06F2212/1044 , G06F2212/656
摘要： A translation table has entries that each include a share bit and a delta bit, with pointers that point to a memory block that includes reuse bits. When two translation table entries reference identical fragments in a memory block, one of the translation table entries is changed to refer to the same memory block referenced in the other translation table entry, which frees up a memory block. The share bit is set to indicate a translation table entry is sharing its memory block with another translation table entry. In addition, a translation table entry may include a private delta in the form of a pointer that references a memory fragment in the memory block that is not shared with other translation table entries. When a translation table has a private delta, its delta bit is set.
摘要翻译：转换表具有各自包括共享位和增量位的条目，指针指向包括重用位的存储器块。当两个转换表条目引用存储器块中的相同片段时，转换表条目中的一个被改变以引用在另一个转换表条目中引用的相同的存储器块，这释放了存储器块。共享位被设置为指示转换表条目与另一个转换表条目共享其存储器块。此外，转换表条目可以包括引用存储器块中不与其他转换表条目共享的存储器片段的指针形式的专用增量。当转换表具有专用增量时，其增量位被设置。

8. 发明申请

US20140047175A1 IMPLEMENTING EFFICIENT CACHE TAG LOOKUP IN VERY LARGE CACHE SYSTEMS 审中-公开
标题翻译：在非常大的高速缓存系统中实现高效的高速缓存标签
公开(公告)号：US20140047175A1
公开(公告)日：2014-02-13
申请号：US13570778
申请日：2012-08-09
申请人： Bulent Abali , Bruce L. Beukema , James A. Marcella , Paul G. Reuland , Michael M. Tsao
发明人： Bulent Abali , Bruce L. Beukema , James A. Marcella , Paul G. Reuland , Michael M. Tsao
IPC分类号： G06F12/00
CPC分类号： G06F12/0895 , G06F12/0802 , G06F12/0897 , G06F12/123 , G06F2212/304
摘要： A method and circuit for implementing a cache directory and efficient cache tag lookup in very large cache systems, and a design structure on which the subject circuit resides are provided. A tag cache includes a fast partial large (LX) cache directory maintained separately on chip apart from a main LX cache directory (LXDIR) stored off chip in dynamic random access memory (DRAM) with large cache data (LXDATA). The tag cache stores most frequently accessed LXDIR tags. The tag cache contains predefined information enabling access to LXDATA directly on tag cache hit with matching address and data present in the LX cache. Only on tag cache misses the LXDIR is accessed to reach LXDATA.
摘要翻译：一种用于在非常大的缓存系统中实现高速缓存目录和高效缓存标签查找的方法和电路，以及提供了主题电路所在的设计结构。标签高速缓存包括除了存储在具有大缓存数据（LXDATA）的动态随机存取存储器（DRAM）中的芯片外的主LX高速缓存目录（LXDIR）之外分开保存的快速部分大（LX）高速缓存目录。标签缓存存储最常访问的LXDIR标签。标签缓存包含预定义信息，可以直接在标签缓存命中上访问LXDATA，匹配地址和LX缓存中存在的数据。只有在标签缓存未命中时才能访问LXDIR以达到LXDATA。

9. 发明申请

US20140075152A1 METHOD FOR GENERATING A DELTA FOR COMPRESSED DATA 有权
公开(公告)号：US20140075152A1
公开(公告)日：2014-03-13
申请号：US13609437
申请日：2012-09-11
申请人： Bulent Abali , James A. Marcella
发明人： Bulent Abali , James A. Marcella
IPC分类号： G06F12/10
CPC分类号： G06F12/10 , G06F12/023 , G06F2212/401 , H03M7/3084
摘要： A translation table has entries that each include a share bit and a delta bit, with pointers that point to a memory block that includes reuse bits. The share bit is set to indicate a translation table entry is sharing its memory block with another translation table entry. In addition, a translation table entry may include a private delta in the form of a pointer that references a memory fragment in the memory block that is not shared with other translation table entries, wherein the private delta references previously-stored content. When a translation table has a private delta, its delta bit is set. The private delta is generated by analyzing a data buffer for content that is similar to previously-stored content.

10. 发明授权

US08904147B2 Method for generating a delta for compressed data 有权
公开(公告)号：US08904147B2
公开(公告)日：2014-12-02
申请号：US13609437
申请日：2012-09-11
申请人： Bulent Abali , James A. Marcella
发明人： Bulent Abali , James A. Marcella
IPC分类号： G06F12/00
CPC分类号： G06F12/10 , G06F12/023 , G06F2212/401 , H03M7/3084
摘要： A translation table has entries that each include a share bit and a delta bit, with pointers that point to a memory block that includes reuse bits. The share bit is set to indicate a translation table entry is sharing its memory block with another translation table entry. In addition, a translation table entry may include a private delta in the form of a pointer that references a memory fragment in the memory block that is not shared with other translation table entries, wherein the private delta references previously-stored content. When a translation table has a private delta, its delta bit is set. The private delta is generated by analyzing a data buffer for content that is similar to previously-stored content.

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