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1. 发明授权

US07919760B2 Operation stage for wafer edge inspection and review 失效
标题翻译：晶圆边缘检查和检查的操作阶段
公开(公告)号：US07919760B2
公开(公告)日：2011-04-05
申请号：US12331336
申请日：2008-12-09
申请人： Jack Jau , Hong Xiao , Joe Wang , Zhongwei Chen , Yi Xiang Wang , Edward Tseng
发明人： Jack Jau , Hong Xiao , Joe Wang , Zhongwei Chen , Yi Xiang Wang , Edward Tseng
IPC分类号： G21K5/10
CPC分类号： H01J37/28 , H01J37/20 , H01J2237/202 , H01J2237/2817 , H01L21/67288 , H01L21/6831
摘要： The present invention relates to an operation stage of a charged particle beam apparatus which is employed in a scanning electron microscope for substrate (wafer) edge and backside defect inspection or defect review. However, it would be recognized that the invention has a much broader range of applicability. A system and method in accordance with the present invention provides an operation stage for substrate edge inspection or review. The inspection region includes top near edge, to bevel, apex, and bottom bevel. The operation stage includes a supporting stand, a z-stage, an X-Y stage, an electrostatic chuck, a pendulum stage and a rotation track. The pendulum stage mount with the electrostatic chuck has the ability to swing from 0° to 180° while performing substrate top bevel, apex and bottom bevel inspection or review. In order to keep the substrate in focus and avoid a large position shift during altering the substrate observation angle by rotation the pendulum stage, one embodiment of the present invention discloses a method such that the rotation axis of the pendulum stage consist of the tangent of upper edge of the substrate to be inspected. The electrostatic chuck of the present invention has a diameter smaller than which of the substrate to be inspected. During the inspection process the substrate on the electrostatic chuck may be rotated about the central axis on the electrostatic chuck to a desired position, this design insures all position on the bevel and apex are able to be inspected.
摘要翻译：本发明涉及用于基板（晶片）边缘和背面缺陷检查或缺陷检查的扫描电子显微镜中的带电粒子束装置的操作阶段。然而，应当认识到，本发明具有更广泛的应用范围。根据本发明的系统和方法提供了用于衬底边缘检查或审查的操作阶段。检查区域包括顶部近边缘，斜面，顶点和底部斜面。操作台包括支撑台，z台，X-Y台，静电卡盘，摆台和旋转轨道。具有静电卡盘的摆台安装具有从0°摆动到180°的能力，同时执行基板顶部斜面，顶部和底部斜面检查或检查。为了将基板保持在对焦状态，并且通过旋转摆锤台来改变基板观察角度而避免大的位置偏移，本发明的一个实施例公开了一种方法，使得摆台的旋转轴线由上部的切线要检查的基板的边缘。本发明的静电卡盘的直径小于要检查的基板的直径。在检查过程中，静电卡盘上的基板可以围绕静电卡盘上的中心轴线旋转到期望的位置，该设计确保能够检查斜面上的所有位置和顶点。

2. 发明授权

US08791414B2 Dynamic focus adjustment with optical height detection apparatus in electron beam system 有权
标题翻译：电子束系统中光学高度检测装置的动态聚焦调整
公开(公告)号：US08791414B2
公开(公告)日：2014-07-29
申请号：US12764902
申请日：2010-04-21
申请人： Joe Wang , Van-Duc Nguyen , Yi-Xiang Wang , Jack Jau , Zhongwei Chen
发明人： Joe Wang , Van-Duc Nguyen , Yi-Xiang Wang , Jack Jau , Zhongwei Chen
IPC分类号： G01N23/00
CPC分类号： G01B11/22 , G01N23/04 , G01N23/20058 , G01N2223/32 , G01N2223/3301 , G01N2223/3302 , G01N2223/646 , H01J37/21 , H01J37/28 , H01J2237/216 , H01J2237/2482 , H01J2237/2487
摘要： The present invention generally relates to dynamic focus adjustment for an image system. With the assistance of a height detection sub-system, present invention provides an apparatus and methods for micro adjusting an image focusing according the specimen surface height variation by altering the field strength of an electrostatic lens between objective lens and sample stage/or a bias voltage applied to the sample surface. Merely by way of example, the invention has been applied to a scanning electron inspection system. But it would be recognized that the invention could apply to other system using charged particle beam as observation tool with a height detection apparatus.
摘要翻译：本发明一般涉及图像系统的动态聚焦调整。本发明借助于高度检测子系统，提供了一种用于通过改变物镜和样品台之间的静电透镜的场强/或偏置电压来根据样本表面高度变化来微调整图像聚焦的装置和方法应用于样品表面。仅作为示例，本发明已经应用于扫描电子检查系统。但是应当认识到，本发明可以应用于使用带有带电粒子束的其它系统作为具有高度检测装置的观察工具。

3. 发明授权

US08094924B2 E-beam defect review system 有权
标题翻译：电子束缺陷检查系统
公开(公告)号：US08094924B2
公开(公告)日：2012-01-10
申请号：US12335458
申请日：2008-12-15
申请人： Jack Jau , Zhongwei Chen , Yi Xiang Wang , Chung-Shih Pan , Joe Wang , Xuedong Liu , Weiming Ren , Wei Fang
发明人： Jack Jau , Zhongwei Chen , Yi Xiang Wang , Chung-Shih Pan , Joe Wang , Xuedong Liu , Weiming Ren , Wei Fang
IPC分类号： G06K9/00
CPC分类号： G06T7/001 , G01N23/04 , G01N2223/102 , G01N2223/426 , G01N2223/611 , G06T2207/10061 , G06T2207/30148
摘要： An apparatus comprises an imaging unit to image a wafer to be reviewed, wherein imaging unit is the modified SORIL column. The modified SORIL column includes a focusing sub-system to do micro-focusing due to a wafer surface topology, wherein the focusing sub-system verifies the position of a grating image reflecting from the wafer surface to adjust the focus; and a surface charge control to regulate the charge accumulation due to electron irradiation during the review process, wherein the gaseous molecules are injected under a flood gun beam rather than under a primary beam. The modified SORIL column further includes a storage unit for storing wafer design database; and a host computer to manage defect locating, defect sampling, and defect classifying, wherein the host computer and storage unit are linked by high speed network.
摘要翻译：一种装置包括成像单元以对待审查的晶片进行成像，其中成像单元是经修改的SORIL柱。改进的SORIL柱包括由于晶片表面拓扑而进行微聚焦的聚焦子系统，其中聚焦子系统验证从晶片表面反射的光栅图像的位置以调整焦点; 以及表面电荷控制，用于调节在复查过程期间由于电子辐射引起的电荷累积，其中气体分子在洪水枪光束下而不是在主光束下方注入。改进的SORIL列还包括用于存储晶片设计数据库的存储单元; 以及用于管理缺陷定位，缺陷采样和缺陷分类的主计算机，其中主计算机和存储单元通过高速网络链接。

4. 发明授权

US08294094B1 Method and apparatus for reducing substrate edge effect during inspection 有权
标题翻译：在检查过程中降低基板边缘效应的方法和装置
公开(公告)号：US08294094B1
公开(公告)日：2012-10-23
申请号：US13211206
申请日：2011-08-16
申请人： Yan Zhao , Jack Jau , Yi-Xiang Wang
发明人： Yan Zhao , Jack Jau , Yi-Xiang Wang
IPC分类号： G01N23/00 , G21K7/00
CPC分类号： G01N23/225 , G01N2223/611 , H01J2237/0048 , H01J2237/153 , H01J2237/2817
摘要： An apparatus and method are introduced in this invention to reduce the edge effect of a substrate that causes image variation or distortion due to applied substrate bias. An edge plate with an edge effect eliminator are provided such that substrate is inspected by a charged particle beam can capture images without distortion at substrate edge.
摘要翻译：在本发明中引入了一种装置和方法，以减少由于所施加的衬底偏压导致图像变化或失真的衬底的边缘效应。提供具有边缘效应消除器的边缘板，使得通过带电粒子束检查基板可以在基板边缘处捕获图像而不失真。

5. 发明授权

US06815345B2 Method for in-line monitoring of via/contact holes etch process based on test structures in semiconductor wafer manufacturing 失效
标题翻译：基于半导体晶片制造中的测试结构的通孔/接触孔蚀刻工艺的在线监测方法
公开(公告)号：US06815345B2
公开(公告)日：2004-11-09
申请号：US10302809
申请日：2002-11-21
申请人： Yan Zhao , Chang-Chun (Roland) Yeh , Zhongwei Chen , Jack Jau
发明人： Yan Zhao , Chang-Chun (Roland) Yeh , Zhongwei Chen , Jack Jau
IPC分类号： H01L2144
CPC分类号： H01L22/34 , H01L21/76802 , H01L22/24
摘要： A method for in-line monitoring of via/contact etching process based on a test structure is described. The test structure is comprised of via/contact holes of different sizes and densities in a layout such that, for a certain process, the microloading or RIE lag induced non-uniform etch rate produce under-etch in some regions and over-etch in others. A scanning electron microscope is used to distinguish these etching differences in voltage contrast images. Image processing and simple calibration convert these voltage contrast images into a “fingerprint” image characterizing the etching process in terms of thickness over-etched or under-etched. Tolerance of shifting or deformation of this image can be set for validating the process uniformity. This image can also be used as a measure to monitor long-term process parameter shifting, as well as wafer-to-wafer or lot-to-lot variations. Advanced process control (APC) can be performed in-line with the guidance of this image so that potential electrical defects are avoided and process yield ramp accelerated.
摘要翻译：描述了一种基于测试结构进行通孔/接触蚀刻工艺在线监测的方法。测试结构由布局不同尺寸和密度的通孔/接触孔组成，使得对于某些工艺，微加载或RIE滞后引起的不均匀蚀刻速率在一些区域产生蚀刻不良并且在其它区域中过度蚀刻。使用扫描电子显微镜来区分电压对比图像中的这些蚀刻差异。图像处理和简单校准将这些电压对比图像转换成表征蚀刻工艺的“指纹”图像，就厚度过蚀刻或欠蚀刻而言。该图像的偏移或变形的公差可以设置为验证过程的均匀性。该图像也可用作监视长期过程参数移位以及晶圆到晶圆或批次间变化的度量。先进的过程控制（APC）可以与该图像的引导一起进行，以便避免潜在的电气缺陷，加速产出斜率。

6. 发明授权

US08923601B2 Method for inspecting overlay shift defect during semiconductor manufacturing and apparatus thereof 有权
标题翻译：在半导体制造期间检查重叠移位缺陷的方法及其装置
公开(公告)号：US08923601B2
公开(公告)日：2014-12-30
申请号：US13240721
申请日：2011-09-22
申请人： Wei Fang , Hong Xiao , Jack Jau
发明人： Wei Fang , Hong Xiao , Jack Jau
IPC分类号： G06K9/00 , G01N23/00 , G03F7/20
CPC分类号： G03F7/70633
摘要： A method for inspecting overlay shift defect during semiconductor manufacturing is disclosed herein and includes a step for providing a charged particle microscopic image of a sample, a step for identifying an inspection pattern measure in the charged particle microscopic image, a step for averaging the charged particle microscopic image by using the inspection pattern measure to form an averaged inspection pattern measure, a step for estimating an average width from the averaged inspection pattern measure, and a step for comparing the average width with a predefined threshold value to determine the presence of the overlay shift defect.
摘要翻译：本文公开了一种用于在半导体制造期间检查覆盖偏移缺陷的方法，并且包括用于提供样品的带电粒子显微镜图像的步骤，用于识别带电粒子显微镜图像中的检查图案测量的步骤，用于使带电粒子平均的步骤通过使用检查图案测量形成平均检查图案测量的微观图像，从平均检查图案度量估计平均宽度的步骤，以及将平均宽度与预定阈值进行比较以确定覆盖层的存在的步骤移位缺陷。

7. 发明授权

US08432441B2 Method and system for measuring critical dimension and monitoring fabrication uniformity 有权
公开(公告)号：US08432441B2
公开(公告)日：2013-04-30
申请号：US13032105
申请日：2011-02-22
申请人： Wei Fang , Hong Xiao , Jack Jau
发明人： Wei Fang , Hong Xiao , Jack Jau
IPC分类号： H04N7/18
CPC分类号： H04N7/18 , G06T7/0004 , G06T7/001 , G06T2207/10061 , G06T2207/20016 , G06T2207/30148 , H04N7/183
摘要： A method for measuring critical dimension (CD) includes steps of: scanning at least one area of interest of a die to obtain at least one scanned image; aligning the scanned image to at least one designed layout pattern to identify a plurality of borders within the scanned image; and averaging distances each measured from the border or the plurality of borders of a pattern associated with a specific type of CD corresponding to the designed layout pattern to obtain a value of CD of the die. The value of critical dimensions of dies can be obtained from the scanned image with lower resolution which is obtained by relatively higher scanning speed, so the above-mentioned method can obtain value of CD for every die within entire wafer to monitor the uniformity of the semiconductor manufacturing process within an acceptable inspection time.

8. 发明申请

US20080267489A1 METHOD FOR DETERMINING ABNORMAL CHARACTERISTICS IN INTEGRATED CIRCUIT MANUFACTURING PROCESS 审中-公开
标题翻译：确定集成电路制造工艺中异常特性的方法
公开(公告)号：US20080267489A1
公开(公告)日：2008-10-30
申请号：US12109243
申请日：2008-04-24
申请人： Hong Xiao , Jack Jau
发明人： Hong Xiao , Jack Jau
IPC分类号： G06K9/00
CPC分类号： G06T7/001 , G06T2207/10056 , G06T2207/30148
摘要： A method for determining abnormal characteristics in integrated circuit manufacturing process is disclosed. The method comprises obtaining a charged particle microscope image of a sample test structure, wherein the sample including a reference pattern and a test pattern; measuring gray levels of the reference pattern and the test pattern; calculating a standard deviation from a distribution of the gray levels of the reference pattern measured; and determining the abnormal characteristics of the test pattern based on the gray levels measured and the standard deviation.
摘要翻译：公开了一种用于确定集成电路制造工艺中的异常特性的方法。该方法包括获得样品测试结构的带电粒子显微镜图像，其中样品包括参考图案和测试图案; 测量参考图案和测试图案的灰度级; 计算与测量的参考图案的灰度分布的标准偏差; 并基于所测量的灰度级和标准偏差确定测试图案的异常特性。

9. 发明申请

US20100278416A1 Method for Inspecting Overlay Shift Defect during Semiconductor Manufacturing and Apparatus Thereof 有权
标题翻译：半导体制造过程中检查覆盖偏移缺陷的方法及其设备
公开(公告)号：US20100278416A1
公开(公告)日：2010-11-04
申请号：US12433762
申请日：2009-04-30
申请人： Hong Xiao , Wei Fang , Jack Jau
发明人： Hong Xiao , Wei Fang , Jack Jau
IPC分类号： G06K9/00 , G01N23/00
CPC分类号： H01L21/67242 , G03F7/70633
摘要： A method of inspecting for overlay shift defects during semiconductor manufacturing is disclosed. The method can include the steps of providing a charged particle microscopic image of a sample, identifying an inspection pattern period in the charged particle microscopic image, averaging the charged particle microscopic image by using the inspection pattern period to form an averaged inspection pattern period, estimating an average width from the averaged inspection pattern period, and comparing the average width with a predefined threshold value to determine the presence of an overlay shift defect.
摘要翻译：公开了一种在半导体制造期间检查覆盖偏移缺陷的方法。该方法可以包括以下步骤：提供样品的带电粒子显微镜图像，识别带电粒子显微镜图像中的检查图案周期，通过使用检查图案周期平均化带电粒子显微镜图像以形成平均检查图案周期，估计从平均检查图案周期的平均宽度，以及将平均宽度与预定义的阈值进行比较，以确定覆盖位移缺陷的存在。

10. 发明授权

US08089297B2 Structure and method for determining a defect in integrated circuit manufacturing process 有权
标题翻译：用于确定集成电路制造过程中的缺陷的结构和方法
公开(公告)号：US08089297B2
公开(公告)日：2012-01-03
申请号：US12110147
申请日：2008-04-25
申请人： Hong Xiao , Jack Jau , Chang Chun Yeh
发明人： Hong Xiao , Jack Jau , Chang Chun Yeh
IPC分类号： G01R31/02 , G01R31/26
CPC分类号： H01L22/12 , H01L22/24
摘要： The present invention discloses a structure and method for determining a defect in integrated circuit manufacturing process, wherein the structure comprises a plurality of normal active areas formed in a plurality of first arrays and a plurality of defective active areas formed in a plurality of second arrays. The first arrays and second arrays are interlaced, and the defect is determined by monitoring a voltage contrast from a charged particle microscope image of the active areas.
摘要翻译：本发明公开了一种用于确定集成电路制造过程中的缺陷的结构和方法，其中该结构包括形成在多个第一阵列中的多个正常有源区和形成在多个第二阵列中的多个有缺陷的有源区。第一阵列和第二阵列是交错的，并且通过监视来自有源区域的带电粒子显微镜图像的电压对比来确定缺陷。

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