专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08166219B2 Method and apparatus for encoding/decoding bus signal 有权
标题翻译：总线信号编码/解码的方法和装置
公开(公告)号：US08166219B2
公开(公告)日：2012-04-24
申请号：US12566496
申请日：2009-09-24
申请人： Jae Sung Lee , Sung Nam Kim , Seong Woon Kim
发明人： Jae Sung Lee , Sung Nam Kim , Seong Woon Kim
IPC分类号： G06F13/38 , H03M9/00
CPC分类号： G06F13/4217 , Y02D10/14 , Y02D10/151
摘要： Provided is a bus signal encoding/decoding method and apparatus. The bus signal encoding method includes receiving a bus signal, XOR-operating all but the first byte sequence of the bus signal in a bitwise manner, inverting the even-numbered byte sequences of the XOR-operated bus signal in a bitwise manner, and serializing the inverted bus signal.
摘要翻译：提供一种总线信号编码/解码方法和装置。总线信号编码方法包括以比特的方式接收总线信号XOR-除了总线信号的第一字节序列以外的所有运算，将按异或运算的总线信号的偶数字节序列按顺序反转，并串行化反向总线信号。

2. 发明申请

US20100146364A1 METHOD AND APPARATUS FOR ENCODING/DECODING BUS SIGNAL 有权
标题翻译：编码/解码总线信号的方法和装置
公开(公告)号：US20100146364A1
公开(公告)日：2010-06-10
申请号：US12566496
申请日：2009-09-24
申请人： Jae Sung LEE , Sung Nam Kim , Seong Woon Kim
发明人： Jae Sung LEE , Sung Nam Kim , Seong Woon Kim
IPC分类号： H03M13/05 , G06F13/14 , G06F11/10
CPC分类号： G06F13/4217 , Y02D10/14 , Y02D10/151
摘要： Provided is a bus signal encoding/decoding method and apparatus. The bus signal encoding method includes receiving a bus signal, XOR-operating all but the first byte sequence of the bus signal in a bitwise manner, inverting the even-numbered byte sequences of the XOR-operated bus signal in a bitwise manner, and serializing the inverted bus signal.
摘要翻译：提供一种总线信号编码/解码方法和装置。总线信号编码方法包括以比特的方式接收总线信号XOR-除了总线信号的第一字节序列以外的所有运算，将按异或运算的总线信号的偶数字节序列按顺序反转，并串行化反向总线信号。

3. 发明授权

US09317295B2 Asynchronous pipeline system, stage, and data transfer mechanism 有权
标题翻译：异步管道系统，阶段和数据传输机制
公开(公告)号：US09317295B2
公开(公告)日：2016-04-19
申请号：US13278385
申请日：2011-10-21
申请人： Myeong Hoon Oh , Young Woo Kim , Sung Nam Kim , Seong Woon Kim
发明人： Myeong Hoon Oh , Young Woo Kim , Sung Nam Kim , Seong Woon Kim
IPC分类号： G06F9/38
CPC分类号： G06F9/3871 , G06F9/3869
摘要： Disclosed are an asynchronous pipeline system, a stage, and a data transfer mechanism. The asynchronous pipeline system having a plurality of stages based on a 4-phase protocol, includes: a first stage among the plurality of stages; and a second stage among the plurality of stages connected next to the first stage, wherein the first stage transmits and the second receives bundled data and control data through an always bundled data channel and on-demand data through an on-demand data channel according to need of the second stage.
摘要翻译：公开了异步管线系统，阶段和数据传输机制。具有基于四相协议的多级的异步管线系统包括：多级中的第一级; 以及与第一级相邻的多级中的第二级，其中第一级发送，第二级通过始终捆绑的数据信道和按需数据信道通过按需数据信道来接收捆绑数据和控制数据，根据需要第二阶段

4. 发明授权

US07941650B2 Microprocessor based on event-processing instruction set and event-processing method using the same 有权
标题翻译：基于事件处理指令集的微处理器和使用它的事件处理方法
公开(公告)号：US07941650B2
公开(公告)日：2011-05-10
申请号：US12155833
申请日：2008-06-10
申请人： Young Woo Kim , Myeong Hoon Oh , Chi Hoon Shin , Sung Nam Kim , Seong Woon Kim , Myung Joon Kim
发明人： Young Woo Kim , Myeong Hoon Oh , Chi Hoon Shin , Sung Nam Kim , Seong Woon Kim , Myung Joon Kim
IPC分类号： G06F9/30 , G06F9/46
CPC分类号： G06F9/30003
摘要： Provided are a microprocessor based on event-processing instruction set and an event-processing method using the same. The microprocessor includes an event register controlling an event according to an event-processing instruction set provided in an instruction set architecture (ISA) and an event controller transmitting externally generated events into the microprocessor. Therefore, the microprocessor may be useful to reduce its unnecessary power consumption by suspending the execution of its program when an instruction decoded to execute the program is an event-processing instruction, and also to cut off its unnecessary power consumption that is caused for an interrupt delay period since the program of the microprocessor may be executed again by immediately re-running the microprocessor with the operation of the event register and the event controller when external events are generated.
摘要翻译：提供了一种基于事件处理指令集的微处理器和使用其的事件处理方法。微处理器包括根据在指令集架构（ISA）中提供的事件处理指令集来控制事件的事件寄存器，以及将外部生成的事件发送到微处理器中的事件控制器。因此，当执行程序解码的指令是事件处理指令时，微处理器可能有助于通过暂停其程序的执行来减少其不必要的功耗，并且还可以切断其对于中断引起的不必要的功耗延迟时间，因为可以通过在产生外部事件时通过事件寄存器和事件控制器的操作立即重新运行微处理器来再次执行微处理器的程序。

5. 发明申请

US20100135430A1 DATA TRANSMITTING DEVICE, DATA RECEIVING DEVICE, DATA TRANSMITTING SYSTEM, AND DATA TRANSMITTING METHOD 有权
标题翻译：数据发送设备，数据接收设备，数据发送系统和数据传输方法
公开(公告)号：US20100135430A1
公开(公告)日：2010-06-03
申请号：US12487593
申请日：2009-06-18
申请人： Myeong Hoon OH , Chi Hoon Shin , Young Woo Kim , Sung Nam Kim , Seong Woon Kim , Han Namgoong
发明人： Myeong Hoon OH , Chi Hoon Shin , Young Woo Kim , Sung Nam Kim , Seong Woon Kim , Han Namgoong
IPC分类号： H04L27/00
CPC分类号： H04L25/4923
摘要： Provided are a data transmitting device transmitting data through a delay insensitive data transmitting method and a data transmitting method. The data transmitting device and the data transmitting method use the delay insensitive data transmitting method supporting a 2-phase hand shake protocol. During data transmission, data are encoded into three logic state having no space state through a ternary encoding method. According to the data transmitting device and the data transmitting method, data are stably transmitted to a receiver regardless of the length of a wire, and provides more excellent performance in an aspect of a data transmission rate, compared to a related art 4-phase delay data transmitting method.
摘要翻译：提供一种通过延迟不敏感数据发送方法和数据发送方法发送数据的数据发送装置。数据发送装置和数据发送方法使用支持2相手抖动协议的延迟不敏感数据发送方式。在数据传输期间，通过三进制编码方式将数据编码为没有空间状态的三个逻辑状态。根据数据发送装置和数据发送方式，与现有技术的4相延迟相比，无论线长度如何，都能够将数据稳定地发送到接收机，并且在数据传输速率方面提供更优异的性能数据传输方式。

6. 发明授权

US08199849B2 Data transmitting device, data receiving device, data transmitting system, and data transmitting method 有权
标题翻译：数据发送装置，数据接收装置，数据发送系统，数据发送方式
公开(公告)号：US08199849B2
公开(公告)日：2012-06-12
申请号：US12487593
申请日：2009-06-18
申请人： Myeong Hoon Oh , Chi Hoon Shin , Young Woo Kim , Sung Nam Kim , Seong Woon Kim , Han Namgoong
发明人： Myeong Hoon Oh , Chi Hoon Shin , Young Woo Kim , Sung Nam Kim , Seong Woon Kim , Han Namgoong
IPC分类号： H04L25/34
CPC分类号： H04L25/4923
摘要： Provided are a data transmitting device transmitting data through a delay insensitive data transmitting method and a data transmitting method. The data transmitting device and the data transmitting method use the delay insensitive data transmitting method supporting a 2-phase hand shake protocol. During data transmission, data are encoded into three logic state having no space state through a ternary encoding method. According to the data transmitting device and the data transmitting method, data are stably transmitted to a receiver regardless of the length of a wire, and provides more excellent performance in an aspect of a data transmission rate, compared to a related art 4-phase delay data transmitting method.
摘要翻译：提供一种通过延迟不敏感数据发送方法和数据发送方法发送数据的数据发送装置。数据发送装置和数据发送方法使用支持2相手抖动协议的延迟不敏感数据发送方式。在数据传输期间，通过三进制编码方式将数据编码为没有空间状态的三个逻辑状态。根据数据发送装置和数据发送方式，与现有技术的4相延迟相比，无论线长度如何，都能够将数据稳定地发送到接收机，并且在数据传输速率方面提供更优异的性能数据传输方式。

7. 发明授权

US07734903B2 Multi-processor system and method for controlling reset and processor ID thereof 失效
标题翻译：多处理器系统及其控制方法及其处理器ID
公开(公告)号：US07734903B2
公开(公告)日：2010-06-08
申请号：US11633811
申请日：2006-12-05
申请人： Young Woo Kim , Sung Nam Kim , Kyoung Park , Seong Woon Kim , Myung Joon Kim
发明人： Young Woo Kim , Sung Nam Kim , Kyoung Park , Seong Woon Kim , Myung Joon Kim
IPC分类号： G06F9/00
CPC分类号： G06F15/02 , G06F15/16
摘要： Provided are a microprocessor suitable for constructing a multi-processor system and a method for controlling the reset and processor ID of the microprocessor. The microprocessor includes decoder receiving a reset ID having a predetermined binary value and a reset signal and decoding the reset ID, an ID generator receiving the decoding result of the decoder and generating at least one microprocessor ID and a reset ID of a microprocessor serially connected to the microprocessor, and a reset vector unit selecting a reset vector according to the decoding result of the decoder. The multi-processor system is constructed such that independent microprocessors of the system respectively generate their own reset vectors and processor IDs when a reset signal is input to the multi-processor system to initialize it. Thus, all the microprocessors of the system can be simultaneously started up when the reset signal is disabled. Accordingly, a resetting process in the multi-processor system is simplified, a period of time required for starting up the microprocessor is reduced, and the multi-processor system is easily designed.
摘要翻译：提供了适用于构造多处理器系统的微处理器和用于控制微处理器的复位和处理器ID的方法。微处理器包括解码器，其接收具有预定二进制值的复位ID和复位信号，并对复位ID进行解码; ID生成器接收解码器的解码结果，并生成至少一个微处理器ID和与微处理器串行连接的微处理器的复位ID 微处理器和复位向量单元根据解码器的解码结果来选择复位向量。多处理器系统被构造成使得当复位信号被输入到多处理器系统以初始化时，系统的独立微处理器分别产生它们自己的复位向量和处理器ID。因此，当复位信号被禁止时，系统的所有微处理器都可以同时启动。因此，简化了多处理器系统中的复位处理，减少了启动微处理器所需的时间，容易地设计多处理器系统。

8. 发明申请

US20090113178A1 Microprocessor based on event-processing instruction set and event-processing method using the same 有权
标题翻译：基于事件处理指令集的微处理器和使用它的事件处理方法
公开(公告)号：US20090113178A1
公开(公告)日：2009-04-30
申请号：US12155833
申请日：2008-06-10
申请人： Young Woo Kim , Myeong Hoon Oh , Chi Hoon Shin , Sung Nam Kim , Seong Woon Kim , Myung Joon Kim
发明人： Young Woo Kim , Myeong Hoon Oh , Chi Hoon Shin , Sung Nam Kim , Seong Woon Kim , Myung Joon Kim
IPC分类号： G06F9/30
CPC分类号： G06F9/30003
摘要： Provided are a microprocessor based on event-processing instruction set and an event-processing method using the same. The microprocessor includes an event register controlling an event according to an event-processing instruction set provided in an instruction set architecture (ISA) and an event controller transmitting externally generated events into the microprocessor. Therefore, the microprocessor may be useful to reduce its unnecessary power consumption by suspending the execution of its program when an instruction decoded to execute the program is an event-processing instruction, and also to cut off its unnecessary power consumption that is caused for an interrupt delay period since the program of the microprocessor may be executed again by immediately re-running the microprocessor with the operation of the event register and the event controller when external events are generated.
摘要翻译：提供了一种基于事件处理指令集的微处理器和使用其的事件处理方法。微处理器包括根据在指令集架构（ISA）中提供的事件处理指令集来控制事件的事件寄存器，以及将外部生成的事件发送到微处理器中的事件控制器。因此，当执行程序解码的指令是事件处理指令时，微处理器可能有助于通过暂停其程序的执行来减少其不必要的功耗，并且还可以切断其对于中断引起的不必要的功耗延迟时间，因为可以通过在产生外部事件时通过事件寄存器和事件控制器的操作立即重新运行微处理器来再次执行微处理器的程序。

9. 发明申请

US20120117374A1 CENTRAL MANAGEMENT COMPUTING SYSTEM 审中-公开
标题翻译：中央管理计算系统
公开(公告)号：US20120117374A1
公开(公告)日：2012-05-10
申请号：US13384034
申请日：2009-10-08
申请人： Won Ok Kwon , Jae Sung Lee , Seong Woon Kim
发明人： Won Ok Kwon , Jae Sung Lee , Seong Woon Kim
IPC分类号： G06F1/26
CPC分类号： G06F3/0227 , G06F1/189 , G06F1/26 , H02J1/00
摘要： Provided is a central management computing system. The central management computing system includes a plurality of terminals, and a rack system. The rack system is connected to the plurality of terminals. The rack system includes a rack power supply unit, a plurality of computers, and a switch. The rack power supply unit is mounted in a rack and converts an AC power into a plurality of DC powers to output to a plurality of DC output ports. The plurality of computers are mounted in the rack and receive the DC powers from the DC output ports. The switch is mounted in the rack and dynamically connects the computers to the terminals, respectively.
摘要翻译：提供了一个中央管理计算系统。中央管理计算系统包括多个终端和机架系统。机架系统连接到多个终端。机架系统包括机架电源单元，多个计算机和开关。机架电源单元安装在机架中，并将AC电力转换成多个DC电力，以输出到多个DC输出端口。多个计算机安装在机架中并从DC输出端口接收直流电力。交换机安装在机架中，并分别动态地将计算机连接到终端。

10. 发明授权

US08055823B2 Bus data transmission apparatus, method for transmitting bus data and bus data communication apparatus 失效
标题翻译：总线数据传输装置，总线数据传输方法和总线数据通信装置
公开(公告)号：US08055823B2
公开(公告)日：2011-11-08
申请号：US12541846
申请日：2009-08-14
申请人： Jae Sung Lee , Seong Woon Kim
发明人： Jae Sung Lee , Seong Woon Kim
IPC分类号： G06F13/38
CPC分类号： G06F13/4217 , Y02D10/14 , Y02D10/151
摘要： Provided are a method and an apparatus for compression transmission of bus data including a plurality of bytes including upper bits and lower bits. The apparatus includes a comparator and an aligner. The comparator compares upper bits of a previous byte with upper bits of a current byte among the plurality of bytes. If the upper bits of the previous byte are identical to the upper bits of the current byte, the aligner compresses the bus data in a combination of a full-byte and a half-byte, by allowing the previous byte to be constituted with the full-byte having bits corresponding to the number of bits of the previous byte and allowing the current byte to be constituted with the half-byte excluding the upper bits of the current byte. Then, the aligner arrays the compressed bus data in a preset bus bandwidth to transmit to a slave device.
摘要翻译：提供了一种用于压缩传输包括高位和低位的多个字节的总线数据的方法和装置。该装置包括比较器和对准器。比较器将先前字节的高位与多个字节中的当前字节的高位进行比较。如果前一个字节的高位与当前字节的高位相同，则对齐器以全字节和半字节的组合来压缩总线数据，通过允许前一个字节由完整字节组成字节具有与先前字节的比特数相对应的比特，并允许当前字节由不包括当前字节的高位的半字节构成。然后，对准器将预设总线带宽中的压缩总线数据排列成从属设备。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式