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1. 发明授权

US08166219B2 Method and apparatus for encoding/decoding bus signal 有权
标题翻译：总线信号编码/解码的方法和装置
公开(公告)号：US08166219B2
公开(公告)日：2012-04-24
申请号：US12566496
申请日：2009-09-24
申请人： Jae Sung Lee , Sung Nam Kim , Seong Woon Kim
发明人： Jae Sung Lee , Sung Nam Kim , Seong Woon Kim
IPC分类号： G06F13/38 , H03M9/00
CPC分类号： G06F13/4217 , Y02D10/14 , Y02D10/151
摘要： Provided is a bus signal encoding/decoding method and apparatus. The bus signal encoding method includes receiving a bus signal, XOR-operating all but the first byte sequence of the bus signal in a bitwise manner, inverting the even-numbered byte sequences of the XOR-operated bus signal in a bitwise manner, and serializing the inverted bus signal.
摘要翻译：提供一种总线信号编码/解码方法和装置。总线信号编码方法包括以比特的方式接收总线信号XOR-除了总线信号的第一字节序列以外的所有运算，将按异或运算的总线信号的偶数字节序列按顺序反转，并串行化反向总线信号。

2. 发明申请

US20100146364A1 METHOD AND APPARATUS FOR ENCODING/DECODING BUS SIGNAL 有权
标题翻译：编码/解码总线信号的方法和装置
公开(公告)号：US20100146364A1
公开(公告)日：2010-06-10
申请号：US12566496
申请日：2009-09-24
申请人： Jae Sung LEE , Sung Nam Kim , Seong Woon Kim
发明人： Jae Sung LEE , Sung Nam Kim , Seong Woon Kim
IPC分类号： H03M13/05 , G06F13/14 , G06F11/10
CPC分类号： G06F13/4217 , Y02D10/14 , Y02D10/151
摘要： Provided is a bus signal encoding/decoding method and apparatus. The bus signal encoding method includes receiving a bus signal, XOR-operating all but the first byte sequence of the bus signal in a bitwise manner, inverting the even-numbered byte sequences of the XOR-operated bus signal in a bitwise manner, and serializing the inverted bus signal.
摘要翻译：提供一种总线信号编码/解码方法和装置。总线信号编码方法包括以比特的方式接收总线信号XOR-除了总线信号的第一字节序列以外的所有运算，将按异或运算的总线信号的偶数字节序列按顺序反转，并串行化反向总线信号。

3. 发明授权

US08199849B2 Data transmitting device, data receiving device, data transmitting system, and data transmitting method 有权
标题翻译：数据发送装置，数据接收装置，数据发送系统，数据发送方式
公开(公告)号：US08199849B2
公开(公告)日：2012-06-12
申请号：US12487593
申请日：2009-06-18
申请人： Myeong Hoon Oh , Chi Hoon Shin , Young Woo Kim , Sung Nam Kim , Seong Woon Kim , Han Namgoong
发明人： Myeong Hoon Oh , Chi Hoon Shin , Young Woo Kim , Sung Nam Kim , Seong Woon Kim , Han Namgoong
IPC分类号： H04L25/34
CPC分类号： H04L25/4923
摘要： Provided are a data transmitting device transmitting data through a delay insensitive data transmitting method and a data transmitting method. The data transmitting device and the data transmitting method use the delay insensitive data transmitting method supporting a 2-phase hand shake protocol. During data transmission, data are encoded into three logic state having no space state through a ternary encoding method. According to the data transmitting device and the data transmitting method, data are stably transmitted to a receiver regardless of the length of a wire, and provides more excellent performance in an aspect of a data transmission rate, compared to a related art 4-phase delay data transmitting method.
摘要翻译：提供一种通过延迟不敏感数据发送方法和数据发送方法发送数据的数据发送装置。数据发送装置和数据发送方法使用支持2相手抖动协议的延迟不敏感数据发送方式。在数据传输期间，通过三进制编码方式将数据编码为没有空间状态的三个逻辑状态。根据数据发送装置和数据发送方式，与现有技术的4相延迟相比，无论线长度如何，都能够将数据稳定地发送到接收机，并且在数据传输速率方面提供更优异的性能数据传输方式。

4. 发明授权

US07734903B2 Multi-processor system and method for controlling reset and processor ID thereof 失效
标题翻译：多处理器系统及其控制方法及其处理器ID
公开(公告)号：US07734903B2
公开(公告)日：2010-06-08
申请号：US11633811
申请日：2006-12-05
申请人： Young Woo Kim , Sung Nam Kim , Kyoung Park , Seong Woon Kim , Myung Joon Kim
发明人： Young Woo Kim , Sung Nam Kim , Kyoung Park , Seong Woon Kim , Myung Joon Kim
IPC分类号： G06F9/00
CPC分类号： G06F15/02 , G06F15/16
摘要： Provided are a microprocessor suitable for constructing a multi-processor system and a method for controlling the reset and processor ID of the microprocessor. The microprocessor includes decoder receiving a reset ID having a predetermined binary value and a reset signal and decoding the reset ID, an ID generator receiving the decoding result of the decoder and generating at least one microprocessor ID and a reset ID of a microprocessor serially connected to the microprocessor, and a reset vector unit selecting a reset vector according to the decoding result of the decoder. The multi-processor system is constructed such that independent microprocessors of the system respectively generate their own reset vectors and processor IDs when a reset signal is input to the multi-processor system to initialize it. Thus, all the microprocessors of the system can be simultaneously started up when the reset signal is disabled. Accordingly, a resetting process in the multi-processor system is simplified, a period of time required for starting up the microprocessor is reduced, and the multi-processor system is easily designed.
摘要翻译：提供了适用于构造多处理器系统的微处理器和用于控制微处理器的复位和处理器ID的方法。微处理器包括解码器，其接收具有预定二进制值的复位ID和复位信号，并对复位ID进行解码; ID生成器接收解码器的解码结果，并生成至少一个微处理器ID和与微处理器串行连接的微处理器的复位ID 微处理器和复位向量单元根据解码器的解码结果来选择复位向量。多处理器系统被构造成使得当复位信号被输入到多处理器系统以初始化时，系统的独立微处理器分别产生它们自己的复位向量和处理器ID。因此，当复位信号被禁止时，系统的所有微处理器都可以同时启动。因此，简化了多处理器系统中的复位处理，减少了启动微处理器所需的时间，容易地设计多处理器系统。

5. 发明授权

US07941650B2 Microprocessor based on event-processing instruction set and event-processing method using the same 有权
标题翻译：基于事件处理指令集的微处理器和使用它的事件处理方法
公开(公告)号：US07941650B2
公开(公告)日：2011-05-10
申请号：US12155833
申请日：2008-06-10
申请人： Young Woo Kim , Myeong Hoon Oh , Chi Hoon Shin , Sung Nam Kim , Seong Woon Kim , Myung Joon Kim
发明人： Young Woo Kim , Myeong Hoon Oh , Chi Hoon Shin , Sung Nam Kim , Seong Woon Kim , Myung Joon Kim
IPC分类号： G06F9/30 , G06F9/46
CPC分类号： G06F9/30003
摘要： Provided are a microprocessor based on event-processing instruction set and an event-processing method using the same. The microprocessor includes an event register controlling an event according to an event-processing instruction set provided in an instruction set architecture (ISA) and an event controller transmitting externally generated events into the microprocessor. Therefore, the microprocessor may be useful to reduce its unnecessary power consumption by suspending the execution of its program when an instruction decoded to execute the program is an event-processing instruction, and also to cut off its unnecessary power consumption that is caused for an interrupt delay period since the program of the microprocessor may be executed again by immediately re-running the microprocessor with the operation of the event register and the event controller when external events are generated.
摘要翻译：提供了一种基于事件处理指令集的微处理器和使用其的事件处理方法。微处理器包括根据在指令集架构（ISA）中提供的事件处理指令集来控制事件的事件寄存器，以及将外部生成的事件发送到微处理器中的事件控制器。因此，当执行程序解码的指令是事件处理指令时，微处理器可能有助于通过暂停其程序的执行来减少其不必要的功耗，并且还可以切断其对于中断引起的不必要的功耗延迟时间，因为可以通过在产生外部事件时通过事件寄存器和事件控制器的操作立即重新运行微处理器来再次执行微处理器的程序。

6. 发明申请

US20100135430A1 DATA TRANSMITTING DEVICE, DATA RECEIVING DEVICE, DATA TRANSMITTING SYSTEM, AND DATA TRANSMITTING METHOD 有权
标题翻译：数据发送设备，数据接收设备，数据发送系统和数据传输方法
公开(公告)号：US20100135430A1
公开(公告)日：2010-06-03
申请号：US12487593
申请日：2009-06-18
申请人： Myeong Hoon OH , Chi Hoon Shin , Young Woo Kim , Sung Nam Kim , Seong Woon Kim , Han Namgoong
发明人： Myeong Hoon OH , Chi Hoon Shin , Young Woo Kim , Sung Nam Kim , Seong Woon Kim , Han Namgoong
IPC分类号： H04L27/00
CPC分类号： H04L25/4923
摘要： Provided are a data transmitting device transmitting data through a delay insensitive data transmitting method and a data transmitting method. The data transmitting device and the data transmitting method use the delay insensitive data transmitting method supporting a 2-phase hand shake protocol. During data transmission, data are encoded into three logic state having no space state through a ternary encoding method. According to the data transmitting device and the data transmitting method, data are stably transmitted to a receiver regardless of the length of a wire, and provides more excellent performance in an aspect of a data transmission rate, compared to a related art 4-phase delay data transmitting method.
摘要翻译：提供一种通过延迟不敏感数据发送方法和数据发送方法发送数据的数据发送装置。数据发送装置和数据发送方法使用支持2相手抖动协议的延迟不敏感数据发送方式。在数据传输期间，通过三进制编码方式将数据编码为没有空间状态的三个逻辑状态。根据数据发送装置和数据发送方式，与现有技术的4相延迟相比，无论线长度如何，都能够将数据稳定地发送到接收机，并且在数据传输速率方面提供更优异的性能数据传输方式。

7. 发明申请

US20090113178A1 Microprocessor based on event-processing instruction set and event-processing method using the same 有权
标题翻译：基于事件处理指令集的微处理器和使用它的事件处理方法
公开(公告)号：US20090113178A1
公开(公告)日：2009-04-30
申请号：US12155833
申请日：2008-06-10
申请人： Young Woo Kim , Myeong Hoon Oh , Chi Hoon Shin , Sung Nam Kim , Seong Woon Kim , Myung Joon Kim
发明人： Young Woo Kim , Myeong Hoon Oh , Chi Hoon Shin , Sung Nam Kim , Seong Woon Kim , Myung Joon Kim
IPC分类号： G06F9/30
CPC分类号： G06F9/30003
摘要： Provided are a microprocessor based on event-processing instruction set and an event-processing method using the same. The microprocessor includes an event register controlling an event according to an event-processing instruction set provided in an instruction set architecture (ISA) and an event controller transmitting externally generated events into the microprocessor. Therefore, the microprocessor may be useful to reduce its unnecessary power consumption by suspending the execution of its program when an instruction decoded to execute the program is an event-processing instruction, and also to cut off its unnecessary power consumption that is caused for an interrupt delay period since the program of the microprocessor may be executed again by immediately re-running the microprocessor with the operation of the event register and the event controller when external events are generated.
摘要翻译：提供了一种基于事件处理指令集的微处理器和使用其的事件处理方法。微处理器包括根据在指令集架构（ISA）中提供的事件处理指令集来控制事件的事件寄存器，以及将外部生成的事件发送到微处理器中的事件控制器。因此，当执行程序解码的指令是事件处理指令时，微处理器可能有助于通过暂停其程序的执行来减少其不必要的功耗，并且还可以切断其对于中断引起的不必要的功耗延迟时间，因为可以通过在产生外部事件时通过事件寄存器和事件控制器的操作立即重新运行微处理器来再次执行微处理器的程序。

8. 发明授权

US09317295B2 Asynchronous pipeline system, stage, and data transfer mechanism 有权
标题翻译：异步管道系统，阶段和数据传输机制
公开(公告)号：US09317295B2
公开(公告)日：2016-04-19
申请号：US13278385
申请日：2011-10-21
申请人： Myeong Hoon Oh , Young Woo Kim , Sung Nam Kim , Seong Woon Kim
发明人： Myeong Hoon Oh , Young Woo Kim , Sung Nam Kim , Seong Woon Kim
IPC分类号： G06F9/38
CPC分类号： G06F9/3871 , G06F9/3869
摘要： Disclosed are an asynchronous pipeline system, a stage, and a data transfer mechanism. The asynchronous pipeline system having a plurality of stages based on a 4-phase protocol, includes: a first stage among the plurality of stages; and a second stage among the plurality of stages connected next to the first stage, wherein the first stage transmits and the second receives bundled data and control data through an always bundled data channel and on-demand data through an on-demand data channel according to need of the second stage.
摘要翻译：公开了异步管线系统，阶段和数据传输机制。具有基于四相协议的多级的异步管线系统包括：多级中的第一级; 以及与第一级相邻的多级中的第二级，其中第一级发送，第二级通过始终捆绑的数据信道和按需数据信道通过按需数据信道来接收捆绑数据和控制数据，根据需要第二阶段

9. 发明授权

US07024498B2 Apparatus for receiving data packet eliminating the need of a temporary memory and memory controller and method thereof 有权
标题翻译：用于接收数据分组而不需要临时存储器和存储器控制器的装置及其方法
公开(公告)号：US07024498B2
公开(公告)日：2006-04-04
申请号：US10460919
申请日：2003-06-13
申请人： Jae Sung Lee , Young Woo Kim , Sung Nam Kim , Sang Man Moh , Yong Youn Kim , Myung Joon Kim , Kee Wook Rim
发明人： Jae Sung Lee , Young Woo Kim , Sung Nam Kim , Sang Man Moh , Yong Youn Kim , Myung Joon Kim , Kee Wook Rim
IPC分类号： G06F3/00
CPC分类号： H04L1/0061 , H04L1/0045 , H04L49/90 , H04L49/9063
摘要： A device for effectively and economically receiving a packet by eliminating temporary memory and a memory controller. The apparatus includes an inspection logic circuit for inspecting data units as soon as they arrive in order to find an error included in the packet and generating control signals according to a result of inspecting a data unit; a multiplexer for receiving data units and distributing the received data units as soon as the data units have arrived; and FIFO memories for receiving the data unit, storing the data unit in a corresponding one of FIFO memories and either deleting or completing storing data units according to the control signals from the inspection logic circuit. The present invention can reduce manufacturing cost of the device by eliminating a temporary memory and a memory controller for the temporary memory and can also reduce processing time.
摘要翻译：一种用于通过消除临时存储器和存储器控制器来有效且经济地接收分组的装置。该装置包括检查逻辑电路，用于在数据单元到达时检查数据单元，以便找到分组中包含的错误，并根据检查数据单元的结果产生控制信号; 多路复用器，用于在数据单元到达之后接收数据单元并分发所接收的数据单元; 和FIFO存储器，用于接收数据单元，将数据单元存储在相应的一个FIFO存储器中，并根据来自检查逻辑电路的控制信号删除或完成存储数据单元。本发明可以通过消除用于临时存储器的临时存储器和存储器控制器来降低设备的制造成本，并且还可以减少处理时间。

10. 发明授权

US08390345B2 Apparatus and method for generating ramp waveform 失效
标题翻译：用于产生斜坡波形的装置和方法
公开(公告)号：US08390345B2
公开(公告)日：2013-03-05
申请号：US13049149
申请日：2011-03-16
申请人： Sung Nam Kim , Cha Kwang Kim , Young Sik Lee
发明人： Sung Nam Kim , Cha Kwang Kim , Young Sik Lee
IPC分类号： H03K4/06
CPC分类号： G09G3/296 , G09G2320/041 , G09G2330/028
摘要： A ramp waveform generating apparatus generates a reference waveform by using an input signal and generates a driving control signal for turning on and off a switch having a first terminal connected to a load and a second terminal connected to a power supply by comparing the voltage of the reference waveform with the voltage of the load. While the switch is repetitively turned on and off in accordance with the driving control signal, a ramp waveform may be generated.
摘要翻译：斜坡波形发生装置通过使用输入信号生成参考波形，并产生用于接通和断开具有连接到负载的第一端子的开关的驱动控制信号，以及连接到电源的第二端子，通过比较参考波形与负载电压。当根据驱动控制信号重复地打开和关闭开关时，可以产生斜坡波形。

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