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1. 发明授权

US5959883A Recording and playback integrated system for analog non-volatile flash memory 失效
标题翻译：用于模拟非易失性闪存的记录和回放集成系统
公开(公告)号：US5959883A
公开(公告)日：1999-09-28
申请号：US4798
申请日：1998-01-09
申请人： James Brennan, Jr. , Anthony Dunne , Peter Holzmann , Geoff Jackson , Albert Kordesch , Chun-Mai Liu , Kung-Yen Su , Hieu Van Tran
发明人： James Brennan, Jr. , Anthony Dunne , Peter Holzmann , Geoff Jackson , Albert Kordesch , Chun-Mai Liu , Kung-Yen Su , Hieu Van Tran
IPC分类号： G11C16/02 , G11C11/56 , G11C16/10 , G11C27/00 , G11C11/34
CPC分类号： G11C16/10 , G11C11/5621 , G11C11/5628 , G11C27/005 , G11C16/30 , G11C2207/16 , G11C2211/5623
摘要： An analog recording and playback system using non-volatile flash memory. An array of flash memory cells is used to store an analog signal and retrieve the stored analog signal on a real-time basis. A plurality of column driver circuits are coupled to the columns of flash memory cells for simultaneous programming and reading. A programming algorithm is used to write the analog signal within an operating range of the flash memory cells since the operating range may shift due to process variations. The system includes trimbit circuits to provide a trimmable initial programming voltage, programming step, programming current, read current, and select gate voltage. The system further includes a Serial Peripheral Interface ("SPI") that interfaces with a host microcontroller. The host microcontroller can send a number of commands to the system through the SPI for efficient message management. These commands include the basic commands to record or playback and various addressing and message cueing options. The system utilizes row and column redundancy to increase production yield.
摘要翻译：使用非易失性闪存的模拟录音和播放系统。闪存单元阵列用于存储模拟信号，并实时检索存储的模拟信号。多个列驱动器电路耦合到闪存单元的列，用于同时编程和读取。使用编程算法将模拟信号写入闪存单元的工作范围内，因为工作范围可能由于工艺变化而偏移。该系统包括三角电路，以提供可调整的初始编程电压，编程步骤，编程电流，读取电流和选择栅极电压。该系统还包括与主机微控制器连接的串行外设接口（“SPI”）。主机微控制器可以通过SPI向系统发送多个命令，以实现高效的消息管理。这些命令包括记录或回放的基本命令以及各种寻址和消息提示选项。该系统利用行和列冗余来提高产量。

2. 发明授权

US5995413A Trimbit circuit for flash memory integrated circuits 失效
公开(公告)号：US5995413A
公开(公告)日：1999-11-30
申请号：US245119
申请日：1999-02-04
申请人： Peter Holzmann , James Brennan, Jr. , Anthony Dunne , Hieu Van Tran
发明人： Peter Holzmann , James Brennan, Jr. , Anthony Dunne , Hieu Van Tran
IPC分类号： G11C16/06 , G11C29/00 , G11C29/04
CPC分类号： G11C29/789
摘要： A trimbit circuit for flash memory integrated circuits is described. The trimbit circuit is used to store the addresses of bad rows and/or columns in flash memory arrays. Furthermore the trimbit circuit is used to store the trimbits for trimable circuits in the integrated circuit, i.e. voltage references, precision oscillator, etc. The invention includes a row of flash memory trimcells and a trimcell differential amplifier circuit. The trimcell differential amplifier circuit can serially shift in trimbits into a latch and serially shift out trimbits without having to program the flash memory trimcells. The final settings of the trimbits can be programmed by means of a high voltage buffer. A non-overlapping clock generator and additional logic is also included to control the circuit.

3. 发明授权

US5933370A Trimbit circuit for flash memory 失效
标题翻译：闪存集成电路的Trimbit电路
公开(公告)号：US5933370A
公开(公告)日：1999-08-03
申请号：US5074
申请日：1998-01-09
申请人： Peter Holzmann , James Brennan, Jr. , Anthony Dunne , Hieu Van Tran
发明人： Peter Holzmann , James Brennan, Jr. , Anthony Dunne , Hieu Van Tran
IPC分类号： G11C16/06 , G11C29/00 , G11C29/04 , G11C16/04
CPC分类号： G11C29/789
摘要： A trimbit circuit for flash memory integrated circuits is described. The trimbit circuit is used to store the addresses of bad rows and/or columns in flash memory arrays. Furthermore the trimbit circuit is used to store the trimbits for trimable circuits in the integrated circuit, i.e. voltage references, precision oscillator, etc. The invention includes a row of flash memory trimcells and a trimcell differential amplifier circuit. The trimcell differential amplifier circuit can serially shift in trimbits into a latch and serially shift out trimbits without having to program the flash memory trimcells. The final settings of the trimbits can be programmed by means of a high voltage buffer. A non-overlapping clock generator and additional logic is also included to control the circuit.
摘要翻译：描述了闪存集成电路的三段电路。 trimbit电路用于存储闪存阵列中不良行和/或列的地址。此外，trimbit电路用于存储集成电路中的可修整电路的三角形，即电压基准，精密振荡器等。本发明包括一排闪存微调单元和微调单元差分放大器电路。微调单元差分放大器电路可以将三位组串行移位到锁存器中，并且串行地移出三位符，而不必对闪存微调单元进行编程。可以通过高电压缓冲区对三角形的最终设置进行编程。还包括不重叠的时钟发生器和附加逻辑来控制电路。

4. 发明授权

US5808938A Method and apparatus for reading analog values stored in floating gate nand structures 失效
标题翻译：用于读取存储在浮动栅极结构中的模拟值的方法和装置
公开(公告)号：US5808938A
公开(公告)日：1998-09-15
申请号：US887307
申请日：1997-07-02
申请人： Hieu Van Tran , James Brennan, Jr. , Trevor Blyth , Sukyoon Yoon
发明人： Hieu Van Tran , James Brennan, Jr. , Trevor Blyth , Sukyoon Yoon
IPC分类号： G11C16/02 , G11C11/56 , G11C16/04 , G11C27/00
CPC分类号： G11C27/005 , G11C11/5621 , G11C11/5642 , G11C16/0483 , G11C16/32 , G11C7/16
摘要： This invention utilizes the small cell size of the NAND storage cell structure in an analog storage and playback device. This is achieved, in part, by using a special, zero current storage cell, in which in the read mode, the cell loading current is waveshaped to attain an optimal dynamic range and to avoid the resistive effects of series parasitic resistances of other transistors in the source node or drain node, and to avoid the transistor conductance variations of all the transistors in the read path. The loading current is waveshaped to reduce possible overshoot and settling effects to achieve the fine output voltage resolution in an optimal sensing time. Details of the method and alternate embodiments are disclosed.
摘要翻译：本发明在模拟存储和重放设备中利用NAND存储单元结构的小单元大小。这部分地通过使用特殊的零电流存储单元实现，其中在读取模式下，电池负载电流被波形化以获得最佳动态范围并且避免其他晶体管的串联寄生电阻的电阻效应源节点或漏极节点，并且避免读取路径中所有晶体管的晶体管电导变化。负载电流是波形的，以减少可能的过冲和稳定效应，以在最佳感测时间内实现精细的输出电压分辨率。公开了该方法和替代实施例的细节。

5. 发明授权

US6002620A Method and apparatus of column redundancy for non-volatile analog and multilevel memory 失效
标题翻译：用于非易失性模拟和多电平存储器集成电路的列冗余的方法和装置
公开(公告)号：US6002620A
公开(公告)日：1999-12-14
申请号：US5098
申请日：1998-01-09
申请人： Hieu Van Tran , James Brennan, Jr.
发明人： Hieu Van Tran , James Brennan, Jr.
IPC分类号： G11C16/06 , G11C11/56 , G11C16/02 , G11C27/00 , G11C29/00 , G11C29/04 , G11C7/00
CPC分类号： G11C29/76 , G11C11/5621 , G11C29/789 , G11C29/80
摘要： This invention provides column redundancy circuits in a storage array, which circuits are used in a non-volatile memory chip to increase the production yield due to manufacturing defects. The invention includes a scheme to latch and transfer the redundancy information, a redundancy logic circuit, a redundancy column driver, an array architecture with column redundancy, a scheme to program and read the column redundancy memory cells, a scheme to multiplex the fuses, and circuits to use an out-of-bound address as a column redundancy enable/disable signal.
摘要翻译：本发明提供了存储阵列中的列冗余电路，这些电路用于非易失性存储器芯片中，以增加由于制造缺陷导致的产量。本发明包括锁存和传送冗余信息的方案，冗余逻辑电路，冗余列驱动器，具有列冗余的阵列结构，编程和读取列冗余存储单元的方案，多路复用保险丝的方案，以及电路使用外接地址作为列冗余使能/禁止信号。

6. 发明授权

US5726934A Method and apparatus for analog reading values stored in floating gate structures 失效
标题翻译：存储在浮动门结构中的模拟读取值的方法和装置
公开(公告)号：US5726934A
公开(公告)日：1998-03-10
申请号：US629729
申请日：1996-04-09
申请人： Hieu Van Tran , James Brennan, Jr. , Trevor Blyth , Sukyoon Yoon
发明人： Hieu Van Tran , James Brennan, Jr. , Trevor Blyth , Sukyoon Yoon
IPC分类号： G11C16/02 , G11C11/56 , G11C16/04 , G11C27/00 , G11C29/00
CPC分类号： G11C27/005 , G11C11/5621 , G11C11/5642 , G11C16/0483 , G11C16/32 , G11C7/16
摘要： This invention utilizes the small cell size of the NAND storage cell structure in an analog storage and playback device. This is achieved, in part, by using a special, zero current storage cell, in which in the read mode, the cell loading current is waveshaped to attain an optimal dynamic range and to avoid the resistive effects of series parasitic resistances of other transistors in the source node or drain node, and to avoid the transistor conductance variations of all the transistors in the read path. The loading current is waveshaped to reduce possible overshoot and settling effects to achieve the fine output voltage resolution in an optimal sensing time. Details of the method and alternate embodiments are disclosed.
摘要翻译：本发明在模拟存储和重放设备中利用NAND存储单元结构的小单元大小。这部分地通过使用特殊的零电流存储单元实现，其中在读取模式下，单元负载电流被波形化以获得最佳动态范围并且避免其他晶体管的串联寄生电阻的电阻效应源节点或漏极节点，并且避免读取路径中所有晶体管的晶体管电导变化。负载电流是波形的，以减少可能的过冲和稳定效应，以在最佳感测时间内实现精细的输出电压分辨率。公开了该方法和替代实施例的细节。

7. 发明授权

US5909393A Method and apparatus for reading analog values stored in floating gate NAND structures 失效
标题翻译：用于读取存储在浮动栅极NAND结构中的模拟值的方法和装置
公开(公告)号：US5909393A
公开(公告)日：1999-06-01
申请号：US887108
申请日：1997-07-01
申请人： Hieu Van Tran , James Brennan, Jr. , Trevor Blyth , Sukyoon Yoon
发明人： Hieu Van Tran , James Brennan, Jr. , Trevor Blyth , Sukyoon Yoon
IPC分类号： G11C16/02 , G11C11/56 , G11C16/04 , G11C27/00
CPC分类号： G11C27/005 , G11C11/5621 , G11C11/5642 , G11C16/0483 , G11C16/32 , G11C7/16
摘要： This invention utilizes the small cell size of the NAND storage cell structure in an analog storage and playback device. This is achieved, in part, by using a special, zero current storage cell, in which in the read mode, the cell loading current is waveshaped to attain an optimal dynamic range and to avoid the resistive effects of series parasitic resistances of other transistors in the source node or drain node, and to avoid the transistor conductance variations of all the transistors in the read path. The loading current is waveshaped to reduce possible overshoot and settling effects to achieve the fine output voltage resolution in an optimal sensing time. Details of the method and alternate embodiments are disclosed.
摘要翻译：本发明在模拟存储和重放设备中利用NAND存储单元结构的小单元大小。这部分地通过使用特殊的零电流存储单元实现，其中在读取模式下，电池负载电流被波形化以获得最佳动态范围并且避免其他晶体管的串联寄生电阻的电阻效应源节点或漏极节点，并且避免读取路径中所有晶体管的晶体管电导变化。负载电流是波形的，以减少可能的过冲和稳定效应，以在最佳感测时间内实现精细的输出电压分辨率。公开了该方法和替代实施例的细节。

8. 发明授权

US6018267A High output swing operational amplifier using low voltage devices 失效
标题翻译：高输出摆幅运算放大器采用低压器件
公开(公告)号：US6018267A
公开(公告)日：2000-01-25
申请号：US37233
申请日：1998-03-10
申请人： Hieu Van Tran , Anthony Dunne
发明人： Hieu Van Tran , Anthony Dunne
IPC分类号： H03F3/30 , H03F3/45
CPC分类号： H03F3/3023 , H03F3/45192 , H03F2200/153 , H03F2203/30009 , H03F2203/30015 , H03F2203/30033 , H03F2203/30036 , H03F2203/30084 , H03F2203/30117 , H03F2203/45396 , H03F2203/45398 , H03F2203/45508 , H03F2203/45626
摘要： A power efficient high output swing operational ("HOOP") amplifier for integrated circuit analog signal processing is described. The operational amplifier includes a differential input stage and an output stage. The differential input stage is powered by a regular power supply while the output stage is powered by a voltage multiplier which results in a high voltage output swing without sinking significant power from the voltage multiplier. The high output voltage (e.g., 23 volts) is achieved using low voltage MOS devices. An output isolation technique is utilized to prevent possible latchup and contention. The operational amplifier also features a bias boot scheme to achieve a faster settling time from power up. In addition, the present invention provides realization of frequency compensation with highest possible breakdown and reduced noise coupling. A bias arrangement between input and output stages of the operational amplifier is used to further help reduce the power drawn from the voltage multiplier and decrease the settling time.
摘要翻译：描述了用于集成电路模拟信号处理的功率有效的高输出摆幅操作（“HOOP”）放大器。运算放大器包括差分输入级和输出级。差分输入级由常规电源供电，而输出级由电压倍增器供电，导致高电压输出摆幅，而不会从电压倍增器吸收大量功率。使用低电压MOS器件实现高输出电压（例如，23伏特）。使用输出隔离技术来防止可能的闭锁和争用。运算放大器还具有偏置引导方案，以实现从上电更快的建立时间。此外，本发明提供了具有最高可能击穿和降低的噪声耦合的频率补偿的实现。使用运算放大器的输入和输出级之间的偏置布置来进一步帮助降低从电压倍增器引出的功率并降低建立时间。

9. 发明授权

US5828592A Analog signal recording and playback integrated circuit and message management system 失效
标题翻译：模拟信号记录和回放集成电路和消息管理系统
公开(公告)号：US5828592A
公开(公告)日：1998-10-27
申请号：US819665
申请日：1997-03-12
申请人： Hieu Van Tran , Nataraj S. Bindiganavale , Anthony Dunne , Boyce W. Jarrett
发明人： Hieu Van Tran , Nataraj S. Bindiganavale , Anthony Dunne , Boyce W. Jarrett
IPC分类号： G11C27/00 , G11C29/44 , G11C11/34
CPC分类号： G11C27/005 , G11C29/44
摘要： An apparatus and method for message management using nonvolatile analog signal recording and playback is disclosed. The device is an integrated circuit with interface circuitry for use as a peripheral device to a microcontroller or a microprocessor-based system. The integrated circuit is complete with differential analog inputs, auto attenuation to improve signal quality, filter, fixed references including a band gap reference, trimming, memory array, multiple closed loop sample and hold circuits, column device, row decoder, address counters, master oscillator, chip function timing circuits, and a serial peripheral interface (SPI) and circuits on a single chip. The integrated circuit is interfaced with a host microcontroller through the SPI. The host microcontroller can send a number of commands to the integrated circuit through the SPI for efficient message management. These commands include the basic commands to record or playback and various addressing and message cueing options. The system utilizes redundancy to increase production yield. It also utilizes a high speed test mode to reduce production testing time.
摘要翻译：公开了一种使用非易失性模拟信号记录和重放的消息管理的装置和方法。该器件是具有接口电路的集成电路，用作微控制器或基于微处理器的系统的外围设备。集成电路配有差分模拟输入，自动衰减以提高信号质量，滤波器，固定参考，包括带隙参考，微调，存储阵列，多个闭环采样和保持电路，列设备，行解码器，地址计数器，主器件振荡器，芯片功能定时电路，以及串行外设接口（SPI）和单芯片上的电路。集成电路通过SPI与主机微控制器连接。主机微控制器可以通过SPI向集成电路发送多个命令，以实现高效的消息管理。这些命令包括记录或回放的基本命令以及各种寻址和消息提示选项。该系统利用冗余来提高产量。它还利用高速测试模式来减少生产测试时间。

10. 发明授权

US08811093B2 Non-volatile memory device and a method of operating same 有权
标题翻译：非易失性存储器件及其操作方法
公开(公告)号：US08811093B2
公开(公告)日：2014-08-19
申请号：US13419269
申请日：2012-03-13
申请人： Hieu Van Tran , Hung Quoc Nguyen , Nhan Do
发明人： Hieu Van Tran , Hung Quoc Nguyen , Nhan Do
IPC分类号： G11C16/04
CPC分类号： G11C16/04 , G11C16/0425 , G11C16/06 , G11C16/12 , G11C16/30 , G11C16/3418
摘要： An array of non-volatile memory cells in a semiconductor substrate of a first conductivity type. Each memory cell comprises first and second regions of a second conductivity type on a surface of the substrate, with a channel region therebetween. A word line overlies one portion of the channel region, is adjacent to the first region, and has little or no overlap with the first region. A floating gate overlies another portion of the channel region, and is adjacent to the first portion and the second region. A coupling gate overlies the floating gate. An erase gate overlies the second region. A bit line is connected to the first region. A negative charge pump circuit generates a negative voltage. A control circuit generates a plurality of control signals in response to receiving a command signal, and applies the negative voltage to the word line of unselected memory cells.
摘要翻译：在第一导电类型的半导体衬底中的非易失性存储单元阵列。每个存储单元包括在衬底的表面上的第二导电类型的第一和第二区域，其间具有沟道区域。字线重叠在通道区域的一部分上，与第一区域相邻，并且与第一区域几乎没有或没有重叠。浮动栅极覆盖沟道区域的另一部分，并且与第一部分和第二区域相邻。耦合栅极覆盖浮栅。擦除门覆盖第二区域。位线连接到第一区域。负电荷泵电路产生负电压。控制电路响应于接收到命令信号而产生多个控制信号，并将负电压施加到未选择存储单元的字线。

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