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1. 发明授权

US5959883A Recording and playback integrated system for analog non-volatile flash memory 失效
标题翻译：用于模拟非易失性闪存的记录和回放集成系统
公开(公告)号：US5959883A
公开(公告)日：1999-09-28
申请号：US4798
申请日：1998-01-09
申请人： James Brennan, Jr. , Anthony Dunne , Peter Holzmann , Geoff Jackson , Albert Kordesch , Chun-Mai Liu , Kung-Yen Su , Hieu Van Tran
发明人： James Brennan, Jr. , Anthony Dunne , Peter Holzmann , Geoff Jackson , Albert Kordesch , Chun-Mai Liu , Kung-Yen Su , Hieu Van Tran
IPC分类号： G11C16/02 , G11C11/56 , G11C16/10 , G11C27/00 , G11C11/34
CPC分类号： G11C16/10 , G11C11/5621 , G11C11/5628 , G11C27/005 , G11C16/30 , G11C2207/16 , G11C2211/5623
摘要： An analog recording and playback system using non-volatile flash memory. An array of flash memory cells is used to store an analog signal and retrieve the stored analog signal on a real-time basis. A plurality of column driver circuits are coupled to the columns of flash memory cells for simultaneous programming and reading. A programming algorithm is used to write the analog signal within an operating range of the flash memory cells since the operating range may shift due to process variations. The system includes trimbit circuits to provide a trimmable initial programming voltage, programming step, programming current, read current, and select gate voltage. The system further includes a Serial Peripheral Interface ("SPI") that interfaces with a host microcontroller. The host microcontroller can send a number of commands to the system through the SPI for efficient message management. These commands include the basic commands to record or playback and various addressing and message cueing options. The system utilizes row and column redundancy to increase production yield.
摘要翻译：使用非易失性闪存的模拟录音和播放系统。闪存单元阵列用于存储模拟信号，并实时检索存储的模拟信号。多个列驱动器电路耦合到闪存单元的列，用于同时编程和读取。使用编程算法将模拟信号写入闪存单元的工作范围内，因为工作范围可能由于工艺变化而偏移。该系统包括三角电路，以提供可调整的初始编程电压，编程步骤，编程电流，读取电流和选择栅极电压。该系统还包括与主机微控制器连接的串行外设接口（“SPI”）。主机微控制器可以通过SPI向系统发送多个命令，以实现高效的消息管理。这些命令包括记录或回放的基本命令以及各种寻址和消息提示选项。该系统利用行和列冗余来提高产量。

2. 发明授权

US5995413A Trimbit circuit for flash memory integrated circuits 失效
公开(公告)号：US5995413A
公开(公告)日：1999-11-30
申请号：US245119
申请日：1999-02-04
申请人： Peter Holzmann , James Brennan, Jr. , Anthony Dunne , Hieu Van Tran
发明人： Peter Holzmann , James Brennan, Jr. , Anthony Dunne , Hieu Van Tran
IPC分类号： G11C16/06 , G11C29/00 , G11C29/04
CPC分类号： G11C29/789
摘要： A trimbit circuit for flash memory integrated circuits is described. The trimbit circuit is used to store the addresses of bad rows and/or columns in flash memory arrays. Furthermore the trimbit circuit is used to store the trimbits for trimable circuits in the integrated circuit, i.e. voltage references, precision oscillator, etc. The invention includes a row of flash memory trimcells and a trimcell differential amplifier circuit. The trimcell differential amplifier circuit can serially shift in trimbits into a latch and serially shift out trimbits without having to program the flash memory trimcells. The final settings of the trimbits can be programmed by means of a high voltage buffer. A non-overlapping clock generator and additional logic is also included to control the circuit.

3. 发明授权

US5933370A Trimbit circuit for flash memory 失效
标题翻译：闪存集成电路的Trimbit电路
公开(公告)号：US5933370A
公开(公告)日：1999-08-03
申请号：US5074
申请日：1998-01-09
申请人： Peter Holzmann , James Brennan, Jr. , Anthony Dunne , Hieu Van Tran
发明人： Peter Holzmann , James Brennan, Jr. , Anthony Dunne , Hieu Van Tran
IPC分类号： G11C16/06 , G11C29/00 , G11C29/04 , G11C16/04
CPC分类号： G11C29/789
摘要： A trimbit circuit for flash memory integrated circuits is described. The trimbit circuit is used to store the addresses of bad rows and/or columns in flash memory arrays. Furthermore the trimbit circuit is used to store the trimbits for trimable circuits in the integrated circuit, i.e. voltage references, precision oscillator, etc. The invention includes a row of flash memory trimcells and a trimcell differential amplifier circuit. The trimcell differential amplifier circuit can serially shift in trimbits into a latch and serially shift out trimbits without having to program the flash memory trimcells. The final settings of the trimbits can be programmed by means of a high voltage buffer. A non-overlapping clock generator and additional logic is also included to control the circuit.
摘要翻译：描述了闪存集成电路的三段电路。 trimbit电路用于存储闪存阵列中不良行和/或列的地址。此外，trimbit电路用于存储集成电路中的可修整电路的三角形，即电压基准，精密振荡器等。本发明包括一排闪存微调单元和微调单元差分放大器电路。微调单元差分放大器电路可以将三位组串行移位到锁存器中，并且串行地移出三位符，而不必对闪存微调单元进行编程。可以通过高电压缓冲区对三角形的最终设置进行编程。还包括不重叠的时钟发生器和附加逻辑来控制电路。

4. 发明授权

US5808938A Method and apparatus for reading analog values stored in floating gate nand structures 失效
标题翻译：用于读取存储在浮动栅极结构中的模拟值的方法和装置
公开(公告)号：US5808938A
公开(公告)日：1998-09-15
申请号：US887307
申请日：1997-07-02
申请人： Hieu Van Tran , James Brennan, Jr. , Trevor Blyth , Sukyoon Yoon
发明人： Hieu Van Tran , James Brennan, Jr. , Trevor Blyth , Sukyoon Yoon
IPC分类号： G11C16/02 , G11C11/56 , G11C16/04 , G11C27/00
CPC分类号： G11C27/005 , G11C11/5621 , G11C11/5642 , G11C16/0483 , G11C16/32 , G11C7/16
摘要： This invention utilizes the small cell size of the NAND storage cell structure in an analog storage and playback device. This is achieved, in part, by using a special, zero current storage cell, in which in the read mode, the cell loading current is waveshaped to attain an optimal dynamic range and to avoid the resistive effects of series parasitic resistances of other transistors in the source node or drain node, and to avoid the transistor conductance variations of all the transistors in the read path. The loading current is waveshaped to reduce possible overshoot and settling effects to achieve the fine output voltage resolution in an optimal sensing time. Details of the method and alternate embodiments are disclosed.
摘要翻译：本发明在模拟存储和重放设备中利用NAND存储单元结构的小单元大小。这部分地通过使用特殊的零电流存储单元实现，其中在读取模式下，电池负载电流被波形化以获得最佳动态范围并且避免其他晶体管的串联寄生电阻的电阻效应源节点或漏极节点，并且避免读取路径中所有晶体管的晶体管电导变化。负载电流是波形的，以减少可能的过冲和稳定效应，以在最佳感测时间内实现精细的输出电压分辨率。公开了该方法和替代实施例的细节。

5. 发明授权

US6002620A Method and apparatus of column redundancy for non-volatile analog and multilevel memory 失效
标题翻译：用于非易失性模拟和多电平存储器集成电路的列冗余的方法和装置
公开(公告)号：US6002620A
公开(公告)日：1999-12-14
申请号：US5098
申请日：1998-01-09
申请人： Hieu Van Tran , James Brennan, Jr.
发明人： Hieu Van Tran , James Brennan, Jr.
IPC分类号： G11C16/06 , G11C11/56 , G11C16/02 , G11C27/00 , G11C29/00 , G11C29/04 , G11C7/00
CPC分类号： G11C29/76 , G11C11/5621 , G11C29/789 , G11C29/80
摘要： This invention provides column redundancy circuits in a storage array, which circuits are used in a non-volatile memory chip to increase the production yield due to manufacturing defects. The invention includes a scheme to latch and transfer the redundancy information, a redundancy logic circuit, a redundancy column driver, an array architecture with column redundancy, a scheme to program and read the column redundancy memory cells, a scheme to multiplex the fuses, and circuits to use an out-of-bound address as a column redundancy enable/disable signal.
摘要翻译：本发明提供了存储阵列中的列冗余电路，这些电路用于非易失性存储器芯片中，以增加由于制造缺陷导致的产量。本发明包括锁存和传送冗余信息的方案，冗余逻辑电路，冗余列驱动器，具有列冗余的阵列结构，编程和读取列冗余存储单元的方案，多路复用保险丝的方案，以及电路使用外接地址作为列冗余使能/禁止信号。

6. 发明授权

US5726934A Method and apparatus for analog reading values stored in floating gate structures 失效
标题翻译：存储在浮动门结构中的模拟读取值的方法和装置
公开(公告)号：US5726934A
公开(公告)日：1998-03-10
申请号：US629729
申请日：1996-04-09
申请人： Hieu Van Tran , James Brennan, Jr. , Trevor Blyth , Sukyoon Yoon
发明人： Hieu Van Tran , James Brennan, Jr. , Trevor Blyth , Sukyoon Yoon
IPC分类号： G11C16/02 , G11C11/56 , G11C16/04 , G11C27/00 , G11C29/00
CPC分类号： G11C27/005 , G11C11/5621 , G11C11/5642 , G11C16/0483 , G11C16/32 , G11C7/16
摘要： This invention utilizes the small cell size of the NAND storage cell structure in an analog storage and playback device. This is achieved, in part, by using a special, zero current storage cell, in which in the read mode, the cell loading current is waveshaped to attain an optimal dynamic range and to avoid the resistive effects of series parasitic resistances of other transistors in the source node or drain node, and to avoid the transistor conductance variations of all the transistors in the read path. The loading current is waveshaped to reduce possible overshoot and settling effects to achieve the fine output voltage resolution in an optimal sensing time. Details of the method and alternate embodiments are disclosed.
摘要翻译：本发明在模拟存储和重放设备中利用NAND存储单元结构的小单元大小。这部分地通过使用特殊的零电流存储单元实现，其中在读取模式下，单元负载电流被波形化以获得最佳动态范围并且避免其他晶体管的串联寄生电阻的电阻效应源节点或漏极节点，并且避免读取路径中所有晶体管的晶体管电导变化。负载电流是波形的，以减少可能的过冲和稳定效应，以在最佳感测时间内实现精细的输出电压分辨率。公开了该方法和替代实施例的细节。

7. 发明授权

US5909393A Method and apparatus for reading analog values stored in floating gate NAND structures 失效
标题翻译：用于读取存储在浮动栅极NAND结构中的模拟值的方法和装置
公开(公告)号：US5909393A
公开(公告)日：1999-06-01
申请号：US887108
申请日：1997-07-01
申请人： Hieu Van Tran , James Brennan, Jr. , Trevor Blyth , Sukyoon Yoon
发明人： Hieu Van Tran , James Brennan, Jr. , Trevor Blyth , Sukyoon Yoon
IPC分类号： G11C16/02 , G11C11/56 , G11C16/04 , G11C27/00
CPC分类号： G11C27/005 , G11C11/5621 , G11C11/5642 , G11C16/0483 , G11C16/32 , G11C7/16
摘要： This invention utilizes the small cell size of the NAND storage cell structure in an analog storage and playback device. This is achieved, in part, by using a special, zero current storage cell, in which in the read mode, the cell loading current is waveshaped to attain an optimal dynamic range and to avoid the resistive effects of series parasitic resistances of other transistors in the source node or drain node, and to avoid the transistor conductance variations of all the transistors in the read path. The loading current is waveshaped to reduce possible overshoot and settling effects to achieve the fine output voltage resolution in an optimal sensing time. Details of the method and alternate embodiments are disclosed.
摘要翻译：本发明在模拟存储和重放设备中利用NAND存储单元结构的小单元大小。这部分地通过使用特殊的零电流存储单元实现，其中在读取模式下，电池负载电流被波形化以获得最佳动态范围并且避免其他晶体管的串联寄生电阻的电阻效应源节点或漏极节点，并且避免读取路径中所有晶体管的晶体管电导变化。负载电流是波形的，以减少可能的过冲和稳定效应，以在最佳感测时间内实现精细的输出电压分辨率。公开了该方法和替代实施例的细节。

8. 发明授权

US5701272A Negative voltage switching circuit 失效
标题翻译：负电压开关电路
公开(公告)号：US5701272A
公开(公告)日：1997-12-23
申请号：US723666
申请日：1996-09-30
申请人： James Brennan, Jr.
发明人： James Brennan, Jr.
IPC分类号： G11C16/04 , G11C5/14 , G11C16/06 , G11C16/30 , H01L21/8234 , H01L27/088 , G11C7/00
CPC分类号： G11C5/143 , G11C16/30
摘要： A voltage switching circuit is described that includes a switching circuit for selectively coupling a first voltage to an output of the switching circuit. The first voltage has a voltage level substantially lower than zero volts. A control circuit is coupled to the switching circuit for controlling the switching circuit to couple the first voltage to the output by generating a second voltage having a voltage level lower than that of the first voltage from a third voltage having a voltage level substantially higher than zero volts.
摘要翻译：描述了一种电压切换电路，其包括用于选择性地将第一电压耦合到开关电路的输出的开关电路。第一电压具有基本上低于零伏特的电压电平。控制电路耦合到开关电路，用于控制开关电路以将第一电压耦合到输出，通过从具有基本上高于零的电压电平的第三电压产生具有低于第一电压的电压电平的第二电压伏。

9. 发明授权

US06301161B1 Programming flash memory analog storage using coarse-and-fine sequence 失效
标题翻译：使用粗略和精细序列编程闪存模拟存储
公开(公告)号：US06301161B1
公开(公告)日：2001-10-09
申请号：US09558432
申请日：2000-04-25
申请人： Peter J. Holzmann , James Brennan, Jr. , Albert Kordesch
发明人： Peter J. Holzmann , James Brennan, Jr. , Albert Kordesch
IPC分类号： G11C1604
CPC分类号： G11C16/10 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/3459 , G11C27/005
摘要： The present invention is a method and apparatus to program a flash memory cell in an analog storage array. A read circuit reads a cell voltage of a flash memory cell. A comparator compares the read cell voltage with an input voltage representing an analog signal. The comparator generates first and second comparison results. A programming circuit generates a first program pulse corresponding to a first amplitude to iteratively program the flash memory cell based on the first comparison result. The programming circuit generates a second program pulse corresponding to a second amplitude less than the first amplitude to iteratively program the flash memory cell based on the first and second comparison results.
摘要翻译：本发明是一种对模拟存储阵列中的闪存单元进行编程的方法和装置。读取电路读取闪存单元的单元电压。比较器将读取的单元电压与表示模拟信号的输入电压进行比较。比较器产生第一和第二比较结果。编程电路产生对应于第一幅度的第一编程脉冲，以基于第一比较结果迭代地编程闪存单元。编程电路产生对应于小于第一幅度的第二幅度的第二编程脉冲，以基于第一和第二比较结果迭代地编程闪存单元。

10. 发明授权

US5293328A Electrically reprogrammable EPROM cell with merged transistor and optiumum area 失效
标题翻译：具有合并晶体管和光电面积的电可重编程EPROM单元
公开(公告)号：US5293328A
公开(公告)日：1994-03-08
申请号：US821165
申请日：1992-01-15
申请人： Alaaeldin A. M. Amin , James Brennan, Jr.
发明人： Alaaeldin A. M. Amin , James Brennan, Jr.
IPC分类号： H01L21/8247 , G11C16/04 , H01L29/788 , H01L29/792 , G11C11/40 , H01L29/68
CPC分类号： H01L29/7886 , G11C16/0425
摘要： A novel nonvolatile memory cell structure is provided using a non-self aligned CMOS process with two independent N+ implants using a two or a three polysilicon layer technology that allows in-circuit electrical erase and reprogramming together with reduction in cell size requirement. The novel memory cell is implemented with a merged transistor structure having an access transistor and a programmable transistor. The memory cell is constructed by having the control gate, formed of a first polysilicon layer, covering a portion of the channel length between drain and source to form the access portion of the merged transistors, and a floating gate formed of a second polysilicon layer overlapping a second portion of the channel length to form the programmable transistor portion of the merged transistor. Such merged transistor structure is equivalent to two transistors in series, a programmable transistor in series with an access transistor. A memory cell structure described in accordance with this invention allows a reduction of the portion of the floating gate covering the programmable transistor portion of the channel length. This results in a reduction in the floating gate to substrate capacitance (C.sub.FB) thereby improving the programming coupling ratio and reducing the overall cell size.
摘要翻译：使用具有两个或三个多晶硅层技术的具有两个独立N +注入的非自对准CMOS工艺提供了一种新颖的非易失性存储单元结构，其允许在电池电擦除和重新编程以及减小单元尺寸要求。新颖的存储器单元由具有存取晶体管和可编程晶体管的合并晶体管结构来实现。存储单元通过具有由第一多晶硅层形成的控制栅极构成，该第一多晶硅层覆盖漏极和源极之间的沟道长度的一部分以形成合并晶体管的存取部分，以及由第二多晶硅层重叠形成的浮置栅极沟道长度的第二部分，以形成合并晶体管的可编程晶体管部分。这种合并的晶体管结构相当于串联的两个晶体管，一个与存取晶体管串联的可编程晶体管。根据本发明描述的存储单元结构允许减少覆盖通道长度的可编程晶体管部分的浮动栅极的部分。这导致浮栅对基极电容（CFB）的降低，从而提高编程耦合比并降低整体单元尺寸。

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