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1. 发明授权

US5959883A Recording and playback integrated system for analog non-volatile flash memory 失效
标题翻译：用于模拟非易失性闪存的记录和回放集成系统
公开(公告)号：US5959883A
公开(公告)日：1999-09-28
申请号：US4798
申请日：1998-01-09
申请人： James Brennan, Jr. , Anthony Dunne , Peter Holzmann , Geoff Jackson , Albert Kordesch , Chun-Mai Liu , Kung-Yen Su , Hieu Van Tran
发明人： James Brennan, Jr. , Anthony Dunne , Peter Holzmann , Geoff Jackson , Albert Kordesch , Chun-Mai Liu , Kung-Yen Su , Hieu Van Tran
IPC分类号： G11C16/02 , G11C11/56 , G11C16/10 , G11C27/00 , G11C11/34
CPC分类号： G11C16/10 , G11C11/5621 , G11C11/5628 , G11C27/005 , G11C16/30 , G11C2207/16 , G11C2211/5623
摘要： An analog recording and playback system using non-volatile flash memory. An array of flash memory cells is used to store an analog signal and retrieve the stored analog signal on a real-time basis. A plurality of column driver circuits are coupled to the columns of flash memory cells for simultaneous programming and reading. A programming algorithm is used to write the analog signal within an operating range of the flash memory cells since the operating range may shift due to process variations. The system includes trimbit circuits to provide a trimmable initial programming voltage, programming step, programming current, read current, and select gate voltage. The system further includes a Serial Peripheral Interface ("SPI") that interfaces with a host microcontroller. The host microcontroller can send a number of commands to the system through the SPI for efficient message management. These commands include the basic commands to record or playback and various addressing and message cueing options. The system utilizes row and column redundancy to increase production yield.
摘要翻译：使用非易失性闪存的模拟录音和播放系统。闪存单元阵列用于存储模拟信号，并实时检索存储的模拟信号。多个列驱动器电路耦合到闪存单元的列，用于同时编程和读取。使用编程算法将模拟信号写入闪存单元的工作范围内，因为工作范围可能由于工艺变化而偏移。该系统包括三角电路，以提供可调整的初始编程电压，编程步骤，编程电流，读取电流和选择栅极电压。该系统还包括与主机微控制器连接的串行外设接口（“SPI”）。主机微控制器可以通过SPI向系统发送多个命令，以实现高效的消息管理。这些命令包括记录或回放的基本命令以及各种寻址和消息提示选项。该系统利用行和列冗余来提高产量。

2. 发明授权

US5995413A Trimbit circuit for flash memory integrated circuits 失效
公开(公告)号：US5995413A
公开(公告)日：1999-11-30
申请号：US245119
申请日：1999-02-04
申请人： Peter Holzmann , James Brennan, Jr. , Anthony Dunne , Hieu Van Tran
发明人： Peter Holzmann , James Brennan, Jr. , Anthony Dunne , Hieu Van Tran
IPC分类号： G11C16/06 , G11C29/00 , G11C29/04
CPC分类号： G11C29/789
摘要： A trimbit circuit for flash memory integrated circuits is described. The trimbit circuit is used to store the addresses of bad rows and/or columns in flash memory arrays. Furthermore the trimbit circuit is used to store the trimbits for trimable circuits in the integrated circuit, i.e. voltage references, precision oscillator, etc. The invention includes a row of flash memory trimcells and a trimcell differential amplifier circuit. The trimcell differential amplifier circuit can serially shift in trimbits into a latch and serially shift out trimbits without having to program the flash memory trimcells. The final settings of the trimbits can be programmed by means of a high voltage buffer. A non-overlapping clock generator and additional logic is also included to control the circuit.

3. 发明授权

US5933370A Trimbit circuit for flash memory 失效
标题翻译：闪存集成电路的Trimbit电路
公开(公告)号：US5933370A
公开(公告)日：1999-08-03
申请号：US5074
申请日：1998-01-09
申请人： Peter Holzmann , James Brennan, Jr. , Anthony Dunne , Hieu Van Tran
发明人： Peter Holzmann , James Brennan, Jr. , Anthony Dunne , Hieu Van Tran
IPC分类号： G11C16/06 , G11C29/00 , G11C29/04 , G11C16/04
CPC分类号： G11C29/789
摘要： A trimbit circuit for flash memory integrated circuits is described. The trimbit circuit is used to store the addresses of bad rows and/or columns in flash memory arrays. Furthermore the trimbit circuit is used to store the trimbits for trimable circuits in the integrated circuit, i.e. voltage references, precision oscillator, etc. The invention includes a row of flash memory trimcells and a trimcell differential amplifier circuit. The trimcell differential amplifier circuit can serially shift in trimbits into a latch and serially shift out trimbits without having to program the flash memory trimcells. The final settings of the trimbits can be programmed by means of a high voltage buffer. A non-overlapping clock generator and additional logic is also included to control the circuit.
摘要翻译：描述了闪存集成电路的三段电路。 trimbit电路用于存储闪存阵列中不良行和/或列的地址。此外，trimbit电路用于存储集成电路中的可修整电路的三角形，即电压基准，精密振荡器等。本发明包括一排闪存微调单元和微调单元差分放大器电路。微调单元差分放大器电路可以将三位组串行移位到锁存器中，并且串行地移出三位符，而不必对闪存微调单元进行编程。可以通过高电压缓冲区对三角形的最终设置进行编程。还包括不重叠的时钟发生器和附加逻辑来控制电路。

4. 发明授权

US6018267A High output swing operational amplifier using low voltage devices 失效
标题翻译：高输出摆幅运算放大器采用低压器件
公开(公告)号：US6018267A
公开(公告)日：2000-01-25
申请号：US37233
申请日：1998-03-10
申请人： Hieu Van Tran , Anthony Dunne
发明人： Hieu Van Tran , Anthony Dunne
IPC分类号： H03F3/30 , H03F3/45
CPC分类号： H03F3/3023 , H03F3/45192 , H03F2200/153 , H03F2203/30009 , H03F2203/30015 , H03F2203/30033 , H03F2203/30036 , H03F2203/30084 , H03F2203/30117 , H03F2203/45396 , H03F2203/45398 , H03F2203/45508 , H03F2203/45626
摘要： A power efficient high output swing operational ("HOOP") amplifier for integrated circuit analog signal processing is described. The operational amplifier includes a differential input stage and an output stage. The differential input stage is powered by a regular power supply while the output stage is powered by a voltage multiplier which results in a high voltage output swing without sinking significant power from the voltage multiplier. The high output voltage (e.g., 23 volts) is achieved using low voltage MOS devices. An output isolation technique is utilized to prevent possible latchup and contention. The operational amplifier also features a bias boot scheme to achieve a faster settling time from power up. In addition, the present invention provides realization of frequency compensation with highest possible breakdown and reduced noise coupling. A bias arrangement between input and output stages of the operational amplifier is used to further help reduce the power drawn from the voltage multiplier and decrease the settling time.
摘要翻译：描述了用于集成电路模拟信号处理的功率有效的高输出摆幅操作（“HOOP”）放大器。运算放大器包括差分输入级和输出级。差分输入级由常规电源供电，而输出级由电压倍增器供电，导致高电压输出摆幅，而不会从电压倍增器吸收大量功率。使用低电压MOS器件实现高输出电压（例如，23伏特）。使用输出隔离技术来防止可能的闭锁和争用。运算放大器还具有偏置引导方案，以实现从上电更快的建立时间。此外，本发明提供了具有最高可能击穿和降低的噪声耦合的频率补偿的实现。使用运算放大器的输入和输出级之间的偏置布置来进一步帮助降低从电压倍增器引出的功率并降低建立时间。

5. 发明授权

US5828592A Analog signal recording and playback integrated circuit and message management system 失效
标题翻译：模拟信号记录和回放集成电路和消息管理系统
公开(公告)号：US5828592A
公开(公告)日：1998-10-27
申请号：US819665
申请日：1997-03-12
申请人： Hieu Van Tran , Nataraj S. Bindiganavale , Anthony Dunne , Boyce W. Jarrett
发明人： Hieu Van Tran , Nataraj S. Bindiganavale , Anthony Dunne , Boyce W. Jarrett
IPC分类号： G11C27/00 , G11C29/44 , G11C11/34
CPC分类号： G11C27/005 , G11C29/44
摘要： An apparatus and method for message management using nonvolatile analog signal recording and playback is disclosed. The device is an integrated circuit with interface circuitry for use as a peripheral device to a microcontroller or a microprocessor-based system. The integrated circuit is complete with differential analog inputs, auto attenuation to improve signal quality, filter, fixed references including a band gap reference, trimming, memory array, multiple closed loop sample and hold circuits, column device, row decoder, address counters, master oscillator, chip function timing circuits, and a serial peripheral interface (SPI) and circuits on a single chip. The integrated circuit is interfaced with a host microcontroller through the SPI. The host microcontroller can send a number of commands to the integrated circuit through the SPI for efficient message management. These commands include the basic commands to record or playback and various addressing and message cueing options. The system utilizes redundancy to increase production yield. It also utilizes a high speed test mode to reduce production testing time.
摘要翻译：公开了一种使用非易失性模拟信号记录和重放的消息管理的装置和方法。该器件是具有接口电路的集成电路，用作微控制器或基于微处理器的系统的外围设备。集成电路配有差分模拟输入，自动衰减以提高信号质量，滤波器，固定参考，包括带隙参考，微调，存储阵列，多个闭环采样和保持电路，列设备，行解码器，地址计数器，主器件振荡器，芯片功能定时电路，以及串行外设接口（SPI）和单芯片上的电路。集成电路通过SPI与主机微控制器连接。主机微控制器可以通过SPI向集成电路发送多个命令，以实现高效的消息管理。这些命令包括记录或回放的基本命令以及各种寻址和消息提示选项。该系统利用冗余来提高产量。它还利用高速测试模式来减少生产测试时间。

6. 发明授权

US07956781B2 Analogue-to-digital converter apparatus and method of reusing an analogue-to-digital converter circuit 有权
标题翻译：模数转换器装置和重新使用模数转换器电路的方法
公开(公告)号：US07956781B2
公开(公告)日：2011-06-07
申请号：US12445029
申请日：2006-10-13
申请人： Omid Oliaei , Alan Bannon , Anthony Dunne , Matthew R. Miller , Daniel O'Hare
发明人： Omid Oliaei , Alan Bannon , Anthony Dunne , Matthew R. Miller , Daniel O'Hare
IPC分类号： H03M3/00
CPC分类号： H03M3/392 , H03M3/40
摘要： An analogue-to-digital converter apparatus comprises a first integrator coupled to a second integrator. The first and second integrators are coupled so as to provide a complex pole. The first integrator is selectively electrically decoupleable from the second integrator, thereby removing the complex pole.
摘要翻译：模数转换器装置包括耦合到第二积分器的第一积分器。第一和第二积分器耦合以提供复极。第一积分器选择性地与第二积分器电可去耦，从而去除复极。

7. 发明授权

US08126101B2 Method and apparatus for varying a dynamic range 有权
标题翻译：改变动态范围的方法和装置
公开(公告)号：US08126101B2
公开(公告)日：2012-02-28
申请号：US12532784
申请日：2007-03-27
申请人： Norman Beamish , Alan Bannon , Anthony Dunne , Conor O'Keeffe
发明人： Norman Beamish , Alan Bannon , Anthony Dunne , Conor O'Keeffe
IPC分类号： H04L7/00
CPC分类号： H03M3/49
摘要： A communications device comprises a receiver for receiving an input signal operably coupled to analogue to digital converter logic. The analogue to digital converter logic is operably coupled to control logic via a signal analyzer arranged to analyze a converted received input signal, output from the analogue to digital converter logic to determine at least one characteristic of the received signal. The control logic is arranged to vary a dynamic range of the analogue to digital converter logic depending on the at least one determined characteristic of the received input signal.
摘要翻译：通信设备包括用于接收可操作地耦合到模数转换器逻辑的输入信号的接收器。模拟到数字转换器逻辑经由信号分析器可操作地耦合到控制逻辑器，信号分析器被布置成分析经转换的接收输入信号，从模数转换器逻辑输出以确定接收信号的至少一个特性。控制逻辑被布置成根据所接收的输入信号的至少一个确定的特性来改变模数转换器逻辑的动态范围。

8. 发明申请

US20090050070A1 Apparatus for Use with a Slatted Floor 有权
标题翻译：用于板条地板的设备
公开(公告)号：US20090050070A1
公开(公告)日：2009-02-26
申请号：US11887523
申请日：2006-03-29
申请人： Patrick Roy Mooney , Anthony Dunne , Martin McElligott , Edward Howlin aka Eamonn Howlin , Stuart O'Hare , Murtagh Logan
发明人： Patrick Roy Mooney , Anthony Dunne , Martin McElligott , Edward Howlin aka Eamonn Howlin , Stuart O'Hare , Murtagh Logan
IPC分类号： A01K1/015
CPC分类号： A01K1/0151
摘要： Apparatus for use with a slatted floor comprises a floor covering apparatus for placement on the individual slats of a slatted floor. Each floor covering apparatus includes an elongated elastomeric mat (410) adapted to be fitted to a floor slat. The mat has a rigid fixing base (411), a flexible core (11) and an outer skin (415). The rigid fixing base (411), the flexible core (11) and the outer skin (415) are integrally formed together. The mat has a longitudinal leg (413) at each side to locate the mat. Also a flap valve (412) is mounted on each leg and protrudes into the gap between adjacent slats.
摘要翻译：用于板条地板的装置包括用于放置在板条地板的各个板条上的地板覆盖装置。每个地板覆盖装置包括适于装配到地板条板的细长弹性垫（410）。垫具有刚性固定底座（411），柔性芯（11）和外皮（415）。刚性固定基座（411），柔性芯（11）和外皮（415）一体地形成在一起。垫子在每一侧具有纵向腿部（413）以定位垫子。此外，每个腿上安装有瓣阀（412）并且突出到相邻板条之间的间隙中。

9. 发明授权

US06556048B1 High speed low skew LVTTL output buffer with invert capability 有权
标题翻译：具有反转能力的高速低偏差LVTTL输出缓冲器
公开(公告)号：US06556048B1
公开(公告)日：2003-04-29
申请号：US09597099
申请日：2000-06-20
申请人： Anthony Dunne
发明人： Anthony Dunne
IPC分类号： H03K190175
CPC分类号： H03K17/163
摘要： A prebuffer circuit configured to generate one or more output control signals in response to one or more current sources and an input signal. The one or more output control signals may reduce a process dependent charge to discharge skew.
摘要翻译：一个预缓冲器电路，被配置为响应于一个或多个电流源和输入信号产生一个或多个输出控制信号。一个或多个输出控制信号可以将处理相关的电荷减少到放电偏移。

10. 发明授权

US06542004B1 Output buffer method and apparatus with on resistance and skew control 有权
标题翻译：输出缓冲方法和具有导通电阻和偏斜控制的装置
公开(公告)号：US06542004B1
公开(公告)日：2003-04-01
申请号：US09808488
申请日：2001-03-13
申请人： Anthony Dunne
发明人： Anthony Dunne
IPC分类号： H03K190175
CPC分类号： H03K17/163
摘要： A pre-buffer circuit configured to generate one or more output control signals in response to a bandgap reference based control circuit. The one or more output control signals control output ON resistance and slew rate so as to limit variations in ringing and skew.
摘要翻译：配置为响应于基于带隙参考的控制电路产生一个或多个输出控制信号的预缓冲器电路。一个或多个输出控制信号控制输出导通电阻和转换速率，以限制振铃和偏斜的变化。

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