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1. 发明授权

US06501407B2 Digital to analog converter 失效
标题翻译：数模转换器
公开(公告)号：US06501407B2
公开(公告)日：2002-12-31
申请号：US09962652
申请日：2001-09-25
申请人： Jan Roelof Westra , Anne Johan Annema , Jeroen Michiel Van Den Boom , Eise Carel Dijkmans
发明人： Jan Roelof Westra , Anne Johan Annema , Jeroen Michiel Van Den Boom , Eise Carel Dijkmans
IPC分类号： H03M166
CPC分类号： H03M1/808
摘要： A digital to analog converter (DAC) for converting a digital signal (DS) having a maximum voltage range which corresponds to a first supply voltage (UL) into an analog signal (Uout) having a maximum voltage range which corresponds to a second supply voltage (UH). The first supply voltage (UL) is offered between a first supply terminal (VSS) and a second supply terminal (VDDL). The second supply voltage (UH) is offered between the first supply terminal (VSS) and a third supply terminal (VDDH). The digital to analog converter (DAC) comprises conversion resistors (RCNV0-RCNVn) and coupling means (CPL) for coupling a number of said conversion resistors (RCNV2-RCNVn) in between the first supply terminal (VSS) and an output terminal (OUT), and for coupling the remainder of said conversion resistors (RCNV0-RCNV1) in between the third supply terminal (VDDH) and the output terminal (OUT). The value of said number depends on the data content of the digital signal (DS). Digital to analog converters are generally implemented in ICs. For modern ICs there is a trend toward ever decreasing supply voltages. Often circuits implemented in new IC processes have to be able to interface with ICs processed in less modern processes which are generally operated on higher supply voltages. In the modern process, therefore, circuits designed in modern ICs have to cope with voltages which are above the maximum specification for their transistors or other components. The DA-converter (DAC) mentioned above fulfils this requirement by the fact that material, such as polycrystalline silicon, is used for the conversion resistors (RCNV2-RCNVn), which material can cope with relatively high voltages, and furthermore by the fact that only the coupling means (CPL) have to be designed to cope with relatively high voltages.
摘要翻译：一种用于将具有对应于第一电源电压（UL）的最大电压范围的数字信号（DS）转换为具有对应于第二电源电压的最大电压范围的模拟信号（Uout）的数模转换器（DAC）（UH）。在第一电源端子（VSS）和第二电源端子（VDDL）之间提供第一电源电压（UL）。在第一电源端子（VSS）和第三电源端子（VDDH）之间提供第二电源电压（UH）。数模转换器（DAC）包括转换电阻（RCNV0-RCNVn）和耦合装置（CPL），用于将第一电源端（VSS）和输出端（OUT）之间的多个所述转换电阻（RCNV2-RCNVn）），并且用于将第三电源端子（VDDH）和输出端子（OUT）之间的所述转换电阻器（RCNV0-RCNV1）中的其余部分耦合。所述数字的值取决于数字信号（DS）的数据内容。数字到模拟转换器通常在IC中实现。对于现代IC来说，电源电压不断下降的趋势。通常在新IC工艺中实现的电路必须能够与通常以更高电源电压工作的较不现代的工艺中处理的IC相连接。因此，在现代流程中，在现代IC中设计的电路必须处理高于其晶体管或其他部件的最大规格的电压。上述DA转换器（DAC）通过以下事实满足了这一要求：诸如多晶硅的材料用于转换电阻器（RCNV2-RCNVn），该材料可以处理相对高的电压，此外，由于只有耦合装置（CPL）必须被设计成能够处理相对较高的电压。

2. 发明授权

US06426715B1 Digital to analog converter 有权
标题翻译：数模转换器
公开(公告)号：US06426715B1
公开(公告)日：2002-07-30
申请号：US09698762
申请日：2000-10-27
申请人： Jan Roelof Westra , Anne Johan Annema
发明人： Jan Roelof Westra , Anne Johan Annema
IPC分类号： H03M106
CPC分类号： H03M1/0665 , H03M1/1205 , H03M1/747
摘要： A digital to analog converter for a multibit digital input signal has a set of conversion elements for the positive signal excursions and a set of conversion elements for the negative signal excursions. In each set the conversion elements are selected according to a dynamic element matching algorithm. To improve the mismatch-noise shaping of these algorithms, excess conversion elements may be additionally selected.
摘要翻译：用于多位数字输入信号的数模转换器具有用于正信号偏移的一组转换元件和用于负信号偏移的一组转换元件。在每个集合中，根据动态元素匹配算法选择转换元素。为了改善这些算法的失配噪声整形，可以另外选择多余的转换元件。

3. 发明授权

US06320414B1 High-voltage level tolerant transistor circuit 有权
标题翻译：高电压电容式晶体管电路
公开(公告)号：US06320414B1
公开(公告)日：2001-11-20
申请号：US09571671
申请日：2000-05-15
申请人： Anne Johan Annema , Godefridus Johannes Gertrudis Maria Geelen
发明人： Anne Johan Annema , Godefridus Johannes Gertrudis Maria Geelen
IPC分类号： H03K190185
CPC分类号： H03K17/102 , H03K17/08142
摘要： A high-voltage level tolerant transistor circuit, comprising a plurality of cascoded transistors, including a first transistor (T1) operatively connected to a high-voltage level node (3) and a second transistor (T2) operatively connected to a low-voltage level node (2). The first transistor (T1) connects to a biasing circuit (8), such as a voltage level shifter, providing a variable biasing level (V1) relative to a voltage level (VH) at the high-voltage level node (3).
摘要翻译：一种高电压电平容限晶体管电路，包括多个级联晶体管，包括可操作地连接到高压电平节点（3）的第一晶体管（T1）和可操作地连接到低压电平的第二晶体管（T2）节点（2）。第一晶体管（T1）连接到诸如电压电平移位器的偏置电路（8），相对于高电压电平节点（3）处的电压电平（VH）提供可变偏置电平（V1）。

4. 发明授权

US06559711B2 Circuit for providing a constant current 有权
公开(公告)号：US06559711B2
公开(公告)日：2003-05-06
申请号：US09902219
申请日：2001-07-10
申请人： Franciscus Petrus Widdershoven , Anne Johan Annema
发明人： Franciscus Petrus Widdershoven , Anne Johan Annema
IPC分类号： G05F110
CPC分类号： G05F3/30
摘要： Two substantially identical currents (I1,a, I1,b) are subtracted from each other, while being generated by elements (10, 11) in such a way that noise in the current value of said two currents (I1,a, I1,b) is determined by shot noise. The differential current, determined only by shot noise, is supplied to a capacitor (13). A second current (I2) is used to charge a second capacitor (22, 29). It is periodically determined whether the value of a voltage across the first capacitor (13) is within or outside a range bounded by the (negative and positive values of the) voltage of the second capacitor (22, 29) which has been charged over the same period of time. The currents (I1,b, Ib) are set in dependence on the result of the comparison. The signal to set the currents (I1,b, Ib) also serves as control signal for an element (43) connected as a constant current source. The setting signal and thus the constant current (I0) delivered by the element (43) connected as a current source is to a high degree independent of the temperature sensitivity of different components of the circuit and is determined essentially solely by the ratio of values of similar components (10, 11, 20, 27, 43) of the circuit. By choosing components whose ratio appears in a value of the constant current (I0) delivered by the circuit and which have the same temperature dependence, it is achieved that the temperature dependence disappears completely or substantially completely from the constant current (I0) delivered by the circuit.

5. 发明授权

US06304112B1 Integrated circuit provided with a fail-safe mode 失效
标题翻译：集成电路配有故障安全模式
公开(公告)号：US06304112B1
公开(公告)日：2001-10-16
申请号：US09635115
申请日：2000-08-09
申请人： Anne Johan Annema , Godefridus Johannes Gertrudis Maria Geelen
发明人： Anne Johan Annema , Godefridus Johannes Gertrudis Maria Geelen
IPC分类号： H03K300
CPC分类号： H03K19/00315
摘要： An integrated circuit provided with an improved fail-safe mode.
摘要翻译：具有改进的故障安全模式的集成电路

6. 发明授权

US06380761B1 Level converter provided with slew-rate controlling means 失效
标题翻译：电平转换器配有压摆率控制装置
公开(公告)号：US06380761B1
公开(公告)日：2002-04-30
申请号：US09744554
申请日：2001-01-26
申请人： Anne Johan Annema
发明人： Anne Johan Annema
IPC分类号： H03K190175
CPC分类号： H03K19/00361 , H03K17/166
摘要： A level converter for the converting of a first digital signal (U1) having a first voltage range into a second digital signal (U2) having a second voltage range comprising an amplifier (T0) having an input for receiving the first digital signal (U1) and an output for supplying the second digital signal (U2), a series arrangement for controlling the slew-rate of the second digital signal (U2) which comprises at least a first capacitor (C1) and a second capacitor (C2) and which is coupled between the output and the input of the amplifier (T0), and voltage controlling means for controlling the voltages (VC1, VC2) across the at least first and second capacitors (C1, C2). The voltage controlling means comprises at least one voltage source (Vls1, Vls2) for supplying a separate bias voltage to each internal node (N1, N2) of the series arrangement. The value of the separate bias voltage or the values of the separate bias voltages is/are dependent on the values of the first (U1) and the second (U2) digital signals.
摘要翻译：一种用于将具有第一电压范围的第一数字信号（U1）转换成具有包括具有用于接收第一数字信号（U1）的输入的放大器（T0）的第二电压范围的第二数字信号（U2）的电平转换器，以及用于提供第二数字信号（U2）的输出，用于控制包括至少第一电容器（C1）和第二电容器（C2）的第二数字信号（U2）的转换速率的串联装置，耦合在放大器（T0）的输出和输入之间;以及电压控制装置，用于控制跨越至少第一和第二电容器（C1，C2）的电压（VC1，VC2）。电压控制装置包括用于向串联装置的每个内部节点（N1，N2）提供单独的偏置电压的至少一个电压源（Vls1，Vls2）。单独偏置电压的值或单独偏置电压的值取决于第一（U1）和第二（U2）数字信号的值。

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