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1. 发明申请

US20100192117A1 ARCHITECTURE AND METHOD FOR COMPENSATING FOR DISPARATE SIGNAL RISE AND FALL TIMES BY USING POLARITY SELECTION TO IMPROVE TIMING AND POWER IN AN INTEGRATED CIRCUIT 有权
标题翻译：通过使用极性选择来增强集成电路中的时序和功率来补偿异常信号上升和下降时间的架构和方法
公开(公告)号：US20100192117A1
公开(公告)日：2010-07-29
申请号：US12753247
申请日：2010-04-02
申请人： Kai Zhu , Volker Hecht
发明人： Kai Zhu , Volker Hecht
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/78 , G06F2217/84
摘要： A method for reducing delay in an integrated circuit by compensating for differences in rise and fall delay times comprises creating a timing graph; computing minimum delay tuples for nodes in the timing graph; if there is not at least one feasible delay tuple, determining a longest path and computing minimum delay tuples for the longest path; changing polarities on the longest path to reduce delays; updating the timing graph by transferring new polarity and delay values; performing timing analysis to determine a new longest path if the new longest path is shorter than the prior longest path, accepting a resulting polarity selection and computing minimum delay tuples for the longest path; if the new longest path is not shorter than the prior longest path, accepting a resulting polarity selection and implementing changes in a user-program bitstream.
摘要翻译：通过补偿上升和下降延迟时间的差异来减少集成电路中的延迟的方法包括创建时序图; 计算定时图中节点的最小延迟元组; 如果不存在至少一个可行延迟元组，则确定最长路径并计算最长路径的最小延迟元组; 在最长的路径上改变极性以减少延误; 通过传递新的极性和延迟值来更新时序图; 执行定时分析以确定新的最长路径，如果新的最长路径短于先前的最长路径，则接受所得极性选择并计算最长路径的最小延迟元组; 如果新的最长路径不比先前最长路径短，则接受所得到的极性选择并实现用户节目比特流中的改变。

2. 发明授权

US08255854B2 Architecture and method for compensating for disparate signal rise and fall times by using polarity selection to improve timing and power in an integrated circuit 有权
标题翻译：通过使用极性选择来提高集成电路中的时序和功率来补偿不同信号上升和下降时间的架构和方法
公开(公告)号：US08255854B2
公开(公告)日：2012-08-28
申请号：US12753247
申请日：2010-04-02
申请人： Kai Zhu , Volker Hecht
发明人： Kai Zhu , Volker Hecht
IPC分类号： G06F17/50 , G06F9/455 , G06F7/38
CPC分类号： G06F17/5031 , G06F2217/78 , G06F2217/84
摘要： A method for reducing delay in an integrated circuit by compensating for differences in rise and fall delay times comprises creating a timing graph; computing minimum delay tuples for nodes in the timing graph; if there is not at least one feasible delay tuple, determining a longest path and computing minimum delay tuples for the longest path; changing polarities on the longest path to reduce delays; updating the timing graph by transferring new polarity and delay values; performing timing analysis to determine a new longest path if the new longest path is shorter than the prior longest path, accepting a resulting polarity selection and computing minimum delay tuples for the longest path; if the new longest path is not shorter than the prior longest path, accepting a resulting polarity selection and implementing changes in a user-program bitstream.
摘要翻译：通过补偿上升和下降延迟时间的差异来减少集成电路中的延迟的方法包括创建时序图; 计算定时图中节点的最小延迟元组; 如果不存在至少一个可行延迟元组，则确定最长路径并计算最长路径的最小延迟元组; 在最长的路径上改变极性以减少延误; 通过传递新的极性和延迟值来更新时序图; 执行定时分析以确定新的最长路径，如果新的最长路径短于先前的最长路径，则接受所得极性选择并计算最长路径的最小延迟元组; 如果新的最长路径不比先前最长的路径短，则接受所得到的极性选择并实现用户节目比特流中的改变。

3. 发明授权

US08244791B1 Fast carry lookahead circuits 有权
标题翻译：快速携带查找电路
公开(公告)号：US08244791B1
公开(公告)日：2012-08-14
申请号：US12022721
申请日：2008-01-30
申请人： Volker Hecht , Marcel Derevlean , Jonathan Greene
发明人： Volker Hecht , Marcel Derevlean , Jonathan Greene
IPC分类号： G06F7/50
CPC分类号： G06F7/508
摘要： A fast lookahead carry adder includes adder logic and lookahead carry-path logic coupled to the adder logic. The carry path logic has a main carry path, a carry entrance path and a carry exit path, the carry entrance path separate from the carry exit path.
摘要翻译：快速前瞻进位加法器包括耦合到加法器逻辑的加法器逻辑和先行进位逻辑逻辑。进位路径逻辑具有主进位路径，进位入口路径和进位出口路径，进位路径与进位出口路径分离。

4. 发明授权

US07919977B2 Circuits and methods for testing FPGA routing switches 有权
标题翻译： FPGA路由交换机的电路和方法
公开(公告)号：US07919977B2
公开(公告)日：2011-04-05
申请号：US12860004
申请日：2010-08-20
申请人： Jonathan W. Greene , John McCollum , Volker Hecht
发明人： Jonathan W. Greene , John McCollum , Volker Hecht
IPC分类号： H03K19/00 , H01L25/00
CPC分类号： H03K19/17764 , G01R31/318519 , H03K19/17736
摘要： An FPGA architecture includes multiplexers having non-volatile switches having control gates coupled to word lines W, each word line associated with a row, the switches connecting to wiring tracks through buffers having a controllable ground connection NGND, at least some of the switches being a tie-off switch coupleable to one of a plurality of bitlines B, each bitline associated with column.
摘要翻译： FPGA架构包括具有非易失性开关的多路复用器，其具有耦合到字线W的控制栅极，与行相关联的每个字线，所述开关通过具有可控接地连接NGND的缓冲器连接到布线轨道，至少一些开关是连接开关可耦合到多个位线B中的一个，每个位线与列相关联。

5. 发明申请

US20060244485A1 THREE INPUT FIELD PROGRAMMABLE GATE ARRAY LOGIC CIRCUIT CONFIGURABLE AS A THREE INPUT LOOK UP TABLE, A D-LATCH OR A D FLIP-FLOP 失效
标题翻译：三个输入现场可编程门阵列逻辑电路可配置为三个输入查看表，D-LATCH或A D FLIP FLOP
公开(公告)号：US20060244485A1
公开(公告)日：2006-11-02
申请号：US11426158
申请日：2006-06-23
申请人： Alan Reynolds , Andrew Reynolds , Volker Hecht
发明人： Alan Reynolds , Andrew Reynolds , Volker Hecht
IPC分类号： H03K19/177
CPC分类号： H03K19/1733 , H03K19/17728
摘要： A field programmable gate array logic cell includes a logic circuit having three inputs and at least one output and a plurality of multiplexers having inputs and outputs. The logic circuit also includes a plurality of programmable elements coupled between the three inputs and at least one output of the logic circuit and the inputs and outputs of the plurality of multiplexers such that a plurality of sequential logic units and combinatorial units can be realized by programming selected ones of the programmable elements, the sequential logic units may include a flip-flop.
摘要翻译：现场可编程门阵列逻辑单元包括具有三个输入的逻辑电路和至少一个具有输入和输出的输出和多个复用器。逻辑电路还包括耦合在三个输入之间的多个可编程元件和逻辑电路的至少一个输出以及多个多路复用器的输入和输出，使得可以通过编程实现多个顺序逻辑单元和组合单元可选择的可编程元件，顺序逻辑单元可以包括触发器。

6. 发明授权

US07106100B1 Three input field programmable gate array logic circuit configurable as a three input look up table, a D-latch or a D flip-flop 失效
公开(公告)号：US07106100B1
公开(公告)日：2006-09-12
申请号：US10877872
申请日：2004-06-24
申请人： Alan B. Reynolds , Andrew W. Reynolds , Volker Hecht
发明人： Alan B. Reynolds , Andrew W. Reynolds , Volker Hecht
IPC分类号： G06F7/38
CPC分类号： H03K19/1733 , H03K19/17728
摘要： A field programmable gate array logic cell includes a logic circuit having three inputs and at least one output and a plurality of multiplexers having inputs and outputs. The logic circuit also includes a plurality of programmable elements coupled between the three inputs and at least one output of the logic circuit and the inputs and outputs of the plurality of multiplexers such that a plurality of sequential logic units and combinatorial units can be realized by programming selected ones of the programmable elements, the sequential logic units may include a flip-flop.

7. 发明授权

US07884640B2 PLD providing soft wakeup logic 有权
标题翻译： PLD提供软唤醒逻辑
公开(公告)号：US07884640B2
公开(公告)日：2011-02-08
申请号：US12340358
申请日：2008-12-19
申请人： Jonathan W Greene , Gregory Bakker , Vidyadhara Bellippady , Volker Hecht , Theodore Speers
发明人： Jonathan W Greene , Gregory Bakker , Vidyadhara Bellippady , Volker Hecht , Theodore Speers
IPC分类号： H03K19/173
CPC分类号： H03K19/17784
摘要： A programmable logic device (PLD) with a plurality of programmable regions is disclosed. Some of the programmable regions have switch power or ground supplies to allow them to be put into a low-power state in one or more low-power modes. At least one of the programmable regions always remains on during the low-power modes to enable the user to design custom PLD power management logic that may be placed in the always-on programmable region.
摘要翻译：公开了具有多个可编程区域的可编程逻辑器件（PLD）。一些可编程区域具有开关电源或接地电源，以允许它们在一个或多个低功率模式下进入低功率状态。在低功率模式期间，至少一个可编程区域始终保持接通状态，以使用户能够设计定制的PLD功率管理逻辑，该逻辑可以放置在永久可编程区域中。

8. 发明授权

US07804321B2 Circuits and methods for testing FPGA routing switches 有权
标题翻译： FPGA路由交换机的电路和方法
公开(公告)号：US07804321B2
公开(公告)日：2010-09-28
申请号：US12205656
申请日：2008-09-05
申请人： Jonathan W. Greene , John McCollum , Volker Hecht
发明人： Jonathan W. Greene , John McCollum , Volker Hecht
IPC分类号： H03K19/00 , H01L25/00
CPC分类号： H03K19/17764 , G01R31/318519 , H03K19/17736
摘要： An FPGA architecture includes multiplexers having non-volatile switches having control gates coupled to word lines W, each word line associated with a row, the switches connecting to wiring tracks through buffers having a controllable ground connection NGND, at least some of the switches being a tie-off switch coupleable to one of a plurality of bitlines B, each bitline associated with column.
摘要翻译： FPGA架构包括具有非易失性开关的多路复用器，其具有耦合到字线W的控制栅极，与行相关联的每个字线，所述开关通过具有可控接地连接NGND的缓冲器连接到布线轨道，至少一些开关是连接开关可耦合到多个位线B中的一个，每个位线与列相关联。

9. 发明申请

US20080218206A1 FIELD PROGRAMMABLE GATE ARRAY LONG LINE ROUTING NETWORK 审中-公开
标题翻译：现场可编程门阵列长路径路由网络
公开(公告)号：US20080218206A1
公开(公告)日：2008-09-11
申请号：US12127516
申请日：2008-05-27
申请人： Volker Hecht
发明人： Volker Hecht
IPC分类号： H03K19/177 , H04B3/36
CPC分类号： H03K19/17736
摘要： A multi-directional routing repeater has a plurality of buffers, each of the plurality of buffers has an input and an output. The output of each of the plurality of buffers is connected to a separate routing line for transmitting a signal in a separate direction of a first set of routing lines, and the input of each of the plurality of buffers is connected to one of a first set of programmable switches, one of a second set of programmable switches, one of a third set of programmable switches, and one of a fourth set of programmable switches, and each one of the first set of programmable switches is connected to a separate one of the second set of programmable switches and a separate one of the second set of programmable switches, none of which are connected to an input of a same one of the plurality of buffers. Each one of the first set of programmable switches is connected to a separate routing line for transmitting a signal in a separate direction of a second set of routing lines.
摘要翻译：多方向路由中继器具有多个缓冲器，多个缓冲器中的每一个具有输入和输出。多个缓冲器中的每一个的输出被连接到单独的路由线路，用于在第一组路由线路的单独方向上发送信号，并且多个缓冲器中的每一个的输入连接到第一组的可编程开关，第二组可编程开关之一，第三组可编程开关之一和第四组可编程开关之一，并且第一组可编程开关中的每一个连接到第二组可编程开关和第二组可编程开关中的单独一个，其中没有一个连接到多个缓冲器中的相同的一个缓冲器的输入端。第一组可编程开关中的每一个连接到用于在第二组路由线的单独方向上发送信号的分离的路线。

10. 发明申请

US20080150580A1 THREE INPUT FIELD PROGRAMMABLE GATE ARRAY LOGIC CIRCUIT CONFIGURABLE AS A THREE INPUT LOOK UP TABLE, A D-LATCH OR A D FLIP- FLOP 有权
标题翻译：三个输入现场可编程门阵列逻辑电路可配置为三个输入查看表，D-LATCH或A D FLIP FLOP
公开(公告)号：US20080150580A1
公开(公告)日：2008-06-26
申请号：US12046160
申请日：2008-03-11
申请人： Alan B. Reynolds , Andrew W. Reynolds , Volker Hecht
发明人： Alan B. Reynolds , Andrew W. Reynolds , Volker Hecht
IPC分类号： H03K19/177
CPC分类号： H03K19/1733 , H03K19/17728
摘要： A field programmable gate array logic cell includes a logic circuit having three inputs and at least one output and a plurality of multiplexers having inputs and outputs. The logic circuit also includes a plurality of programmable elements coupled between the three inputs and at least one output of the logic circuit and the inputs and outputs of the plurality of multiplexers such that a plurality of sequential logic units and combinatorial units can be realized by programming selected ones of the programmable elements, the sequential logic units may include a flip-flop.
摘要翻译：现场可编程门阵列逻辑单元包括具有三个输入的逻辑电路和至少一个具有输入和输出的输出和多个复用器。逻辑电路还包括耦合在三个输入之间的多个可编程元件和逻辑电路的至少一个输出以及多个多路复用器的输入和输出，使得可以通过编程实现多个顺序逻辑单元和组合单元可选择的可编程元件，顺序逻辑单元可以包括触发器。

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