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1. 发明授权

US06613690B1 Approach for forming a buried stack capacitor structure featuring reduced polysilicon stringers 有权
标题翻译：用于形成具有减少的多晶硅桁架的掩埋堆叠电容器结构的方法
公开(公告)号：US06613690B1
公开(公告)日：2003-09-02
申请号：US10197318
申请日：2002-07-17
申请人： Chung-Wei Chang , Kuo-Chyuan Tzeng , Chen-Jong Wang , Min-Hsiang Chiang , Chi-Hsing Lo
发明人： Chung-Wei Chang , Kuo-Chyuan Tzeng , Chen-Jong Wang , Min-Hsiang Chiang , Chi-Hsing Lo
IPC分类号： H01L21302
CPC分类号： H01L27/1087 , H01L21/32139 , H01L27/10835 , H01L28/91
摘要： A process for forming a buried stack capacitor structure in a recessed region of a shallow trench isolation (STI) region, has been developed. The process features a unique sequence of procedures eliminating possible polysilicon stringers or residuals which if left remaining would result in leakage or shorts between conductive elements. The unique sequence of procedures include: deposition of a silicon oxide layer on the polysilicon layer from which the storage node structure will be defined from; photoresist plugs used to protect the portions of the silicon oxide and the underlying polysilicon layer located in the recessed region, during definition of the polysilicon storage node structure; and definition of the polysilicon storage node structure via a wet etch procedure, using the silicon oxide layer for protection of the underlying polysilicon storage node structure.
摘要翻译：已经开发了在浅沟槽隔离（STI）区域的凹陷区域中形成掩埋堆叠电容器结构的工艺。该方法具有唯一的程序序列，可以消除可能的多晶硅桁条或残余物，如果留下剩余物会导致导电元件之间的泄漏或短路。独特的程序顺序包括：在多晶硅层上沉积氧化硅层，从其上定义存储节点结构; 用于在多晶硅存储节点结构的定义期间用于保护位于凹陷区域中的氧化硅部分和下面的多晶硅层的光阻胶塞; 以及通过湿蚀刻程序定义多晶硅存储节点结构，使用氧化硅层来保护下面的多晶硅存储节点结构。

2. 发明授权

US06661050B2 Memory cell structure with trench capacitor and method for fabrication thereof 有权
标题翻译：具有沟槽电容器的存储单元结构及其制造方法
公开(公告)号：US06661050B2
公开(公告)日：2003-12-09
申请号：US10102280
申请日：2002-03-20
申请人： Kuo-Chyuan Tzeng , Chen-Jong Wang , Chung-Wei Chang
发明人： Kuo-Chyuan Tzeng , Chen-Jong Wang , Chung-Wei Chang
IPC分类号： H01L27108
CPC分类号： H01L27/10861 , H01L27/10829 , H01L27/11 , H01L29/66181 , Y10S257/906
摘要： Within both a memory cell structure and a method for fabricating the memory cell structure there is employed a storage capacitor formed within a trench adjoining an active region of a semiconductor substrate. Within the memory cell structure and the method for fabrication thereof, both the active region of the semiconductor substrate and the trench are contained within a doped well within the semiconductor substrate.
摘要翻译：在存储单元结构和用于制造存储单元结构的方法中，采用在与半导体衬底的有源区相邻的沟槽内形成的存储电容器。在存储单元结构及其制造方法中，半导体衬底的有源区和沟槽都包含在半导体衬底内的掺杂阱中。

3. 发明授权

US06661049B2 Microelectronic capacitor structure embedded within microelectronic isolation region 有权
公开(公告)号：US06661049B2
公开(公告)日：2003-12-09
申请号：US09947793
申请日：2001-09-06
申请人： Kuo-Chyuan Tzeng , Chen-Jong Wang , Chung-Wei Chang
发明人： Kuo-Chyuan Tzeng , Chen-Jong Wang , Chung-Wei Chang
IPC分类号： H01L29772
CPC分类号： H01L27/10861 , H01L27/10829 , H01L27/10867 , H01L28/91 , H01L29/945
摘要： Within a method for fabricating a capacitor structure, and a capacitor structure fabricated employing the method, there is formed within an isolation region adjoining an active region of a semiconductor substrate a laterally asymmetric trench which leaves exposed an upper sidewall portion of the active region of the semiconductor substrate. There is then formed within the laterally asymmetric trench a capacitor node layer which contacts the exposed upper sidewall portion of the active region of the semiconductor substrate and extends above the active region of the semiconductor substrate. The capacitor may be a storage capacitor with increased capacitance fabricated within a memory cell structure of decreased dimensions.

4. 发明授权

US06638813B1 Method of forming a composite spacer to eliminate polysilicon stringers between elements in a pseudo SRAM cell 有权
标题翻译：形成复合间隔物以消除伪SRAM单元中的元件之间的多晶硅桁条的方法
公开(公告)号：US06638813B1
公开(公告)日：2003-10-28
申请号：US10059825
申请日：2002-01-29
申请人： Kuo-Chyuan Tzeng , Chen-Jong Wang , Chung-Wei Chang , Wen-Chuan Chiang , Wen-Cheng Chen , Kuo-Ching Huang
发明人： Kuo-Chyuan Tzeng , Chen-Jong Wang , Chung-Wei Chang , Wen-Chuan Chiang , Wen-Cheng Chen , Kuo-Ching Huang
IPC分类号： H01L218242
CPC分类号： H01L28/60 , H01L21/31111 , H01L21/31116 , H01L21/32137 , H01L21/76232 , H01L27/11
摘要： A process for forming a composite insulator spacer on the sides of a buried stack capacitor structure, wherein the buried stack capacitor structure is located overlying a portion of an insulator filled, shallow trench isolation (STI) region, has been developed. A thin silicon nitride spacer is first formed on the sides of the completed buried stack capacitor structure, followed by deposition of a silicon oxide layer. An anisotropic dry etch procedure is next employed removing a top portion of the silicon oxide layer, and resulting in a partially defined silicon oxide spacer. A critical wet etch procedure is next used to remove the bottom portion of the silicon oxide layer, defining the final silicon oxide spacer of the composite insulator spacer, now comprised of a silicon oxide spacer on an underlying silicon nitride spacer. The wet etch procedure allows a gradual slope to be created at the composite insulator spacer—STI region interface, reducing the risk of leaving, or forming polysilicon residuals or stringers on the underlying surface, which can occur during definition of a MOSFET gate structure. The elimination of the polysilicon stringers reduces the risk of leakage between SRAM cell elements, such as buried stack capacitor structures, and MOSFET devices.
摘要翻译：已经开发了一种用于在掩埋叠层电容器结构的侧面上形成复合绝缘体间隔物的方法，其中埋层叠层电容器结构位于绝缘体填充的浅沟槽隔离（STI）区域的一部分上方。首先在完成的掩埋堆叠电容器结构的侧面上形成薄的氮化硅间隔物，然后沉积氧化硅层。接下来，使用各向异性干蚀刻工艺去除氧化硅层的顶部，并产生部分限定的氧化硅间隔物。接下来使用关键的湿法蚀刻工艺来去除氧化硅层的底部，限定复合绝缘垫片的最终氧化硅隔离物，现在由下面的氮化硅间隔物上的氧化硅间隔物构成。湿蚀刻工艺允许在复合绝缘体间隔件-ST区域界面处产生逐渐的斜率，从而降低在MOSFET栅极结构的定义期间可能发生的在下表面上的离开风险或形成多晶硅残余物或桁条。多晶硅桁架的消除降低了诸如掩埋堆叠电容器结构的SRAM单元元件和MOSFET器件之间的泄漏的风险。

5. 发明授权

US08748284B2 Method of manufacturing decoupling MIM capacitor designs for interposers 有权
标题翻译：制造用于插入件的解耦MIM电容器设计的方法
公开(公告)号：US08748284B2
公开(公告)日：2014-06-10
申请号：US13209195
申请日：2011-08-12
申请人： Kuo-Chyuan Tzeng , Kuo-Chi Tu , Chen-Jong Wang , Hsiang-Fan Lee
发明人： Kuo-Chyuan Tzeng , Kuo-Chi Tu , Chen-Jong Wang , Hsiang-Fan Lee
IPC分类号： H01L21/20
CPC分类号： H01L28/40 , H01L23/147 , H01L23/3114 , H01L23/49822 , H01L23/5223 , H01L24/83 , H01L27/06 , H01L27/0805 , H01L2224/131 , H01L2224/13144 , H01L2224/16235 , H01L2224/16238 , H01L2924/0002 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2924/00 , H01L2924/014 , H01L2924/00014
摘要： Decoupling metal-insulator-metal (MIM) capacitor designs for interposers and methods of manufacture thereof are disclosed. In one embodiment, a method of forming a decoupling capacitor includes providing a packaging device, and forming a decoupling MIM capacitor in at least two metallization layers of the packaging device.
摘要翻译：公开了用于插入件的去耦金属绝缘体金属（MIM）电容器设计及其制造方法。在一个实施例中，形成去耦电容器的方法包括提供封装装置，以及在包装装置的至少两个金属化层中形成去耦MIM电容器。

6. 发明授权

US08716100B2 Method of fabricating metal-insulator-metal (MIM) capacitor within topmost thick inter-metal dielectric layers 有权
标题翻译：在最厚的金属间介电层内制造金属绝缘体金属（MIM）电容器的方法
公开(公告)号：US08716100B2
公开(公告)日：2014-05-06
申请号：US13212922
申请日：2011-08-18
申请人： Kuo-Chyuan Tzeng , Luan C. Tran , Chen-Jong Wang , Kuo-Chi Tu , Hsiang-Fan Lee
发明人： Kuo-Chyuan Tzeng , Luan C. Tran , Chen-Jong Wang , Kuo-Chi Tu , Hsiang-Fan Lee
IPC分类号： H01L21/20
CPC分类号： H01L28/86 , H01L23/5223 , H01L28/40 , H01L28/90 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of MIM capacitors may be embedded into a thick IMD layer with enough thickness (e.g., 10 KÅ˜30 KÅ) to get high capacitance, which may be on top of a thinner IMD layer. MIM capacitors may be formed among three adjacent metal layers which have two thick IMD layers separating the three adjacent metal layers. Materials such as TaN or TiN are used as bottom/top electrodes & Cu barrier. The metal layer above the thick IMD layer may act as the top electrode connection. The metal layer under the thick IMD layer may act as the bottom electrode connection. The capacitor may be of different shapes such as cylindrical shape, or a concave shape. Many kinds of materials (Si3N4, ZrO2, HfO2, BST . . . etc) can be used as the dielectric material. The MIM capacitors are formed by one or two extra masks while forming other non-capacitor logic of the circuit.
摘要翻译： MIM电容器的实施例可以嵌入到具有足够厚度（例如，10K〜30K）的厚IMD层中以获得高电容，其可以在更薄的IMD层之上。可以在三个相邻的金属层之间形成MIM电容器，这两个相邻的金属层具有两个分开三个相邻金属层的厚的IMD层。诸如TaN或TiN的材料用作底部/顶部电极和Cu屏障。厚IMD层上方的金属层可以用作顶部电极连接。厚IMD层下面的金属层可以用作底部电极连接。电容器可以是不同的形状，例如圆柱形或凹形。可以使用多种材料（Si3N4，ZrO2，HfO2，BST等）作为介电材料。 MIM电容器由一个或两个额外的掩模形成，同时形成电路的其他非电容器逻辑。

7. 发明申请

US20130043560A1 Metal-Insulator-Metal Capacitor and Method of Fabricating 有权
标题翻译：金属绝缘体 - 金属电容器和制造方法
公开(公告)号：US20130043560A1
公开(公告)日：2013-02-21
申请号：US13212922
申请日：2011-08-18
申请人： Kuo-Chyuan Tzeng , Luan C. Tran , Chen-Jong Wang , Kuo-Chi Tu , Hsiang-Fan Lee
发明人： Kuo-Chyuan Tzeng , Luan C. Tran , Chen-Jong Wang , Kuo-Chi Tu , Hsiang-Fan Lee
IPC分类号： H01L27/06 , H01L21/02
CPC分类号： H01L28/86 , H01L23/5223 , H01L28/40 , H01L28/90 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of MIM capacitors may be embedded into a thick IMD layer with enough thickness (e.g., 10 KÅ˜30 KÅ) to get high capacitance, which may be on top of a thinner IMD layer. MIM capacitors may be formed among three adjacent metal layers which have two thick IMD layers separating the three adjacent metal layers. Materials such as TaN or TiN are used as bottom/top electrodes & Cu barrier. The metal layer above the thick IMD layer may act as the top electrode connection. The metal layer under the thick IMD layer may act as the bottom electrode connection. The capacitor may be of different shapes such as cylindrical shape, or a concave shape. Many kinds of materials (Si3N4, ZrO2, HfO2, BST . . . etc) can be used as the dielectric material. The MIM capacitors are formed by one or two extra masks while forming other non-capacitor logic of the circuit.
摘要翻译： MIM电容器的实施例可以嵌入到具有足够厚度（例如，10K〜30K）的厚IMD层中以获得高电容，其可以在更薄的IMD层之上。可以在三个相邻的金属层之间形成MIM电容器，这两个相邻的金属层具有两个分开三个相邻金属层的厚的IMD层。诸如TaN或TiN的材料用作底部/顶部电极和Cu屏障。厚IMD层上方的金属层可以用作顶部电极连接。厚IMD层下面的金属层可以用作底部电极连接。电容器可以是不同的形状，例如圆柱形或凹形。可以使用多种材料（Si3N4，ZrO2，HfO2，BST等）作为介电材料。 MIM电容器由一个或两个额外的掩模形成，同时形成电路的其他非电容器逻辑。

8. 发明申请

US20080116496A1 Integrating a DRAM with an SRAM having butted contacts and resulting devices 审中-公开
标题翻译：将DRAM与具有对接触点和所产生的器件的SRAM集成
公开(公告)号：US20080116496A1
公开(公告)日：2008-05-22
申请号：US11809642
申请日：2007-06-01
申请人： Kuo-Chyuan Tzeng , Kuo-Chiang Ting , Chen-Jong Wang , Min-Hsiung Chiang , Chih-Yang Pai
发明人： Kuo-Chyuan Tzeng , Kuo-Chiang Ting , Chen-Jong Wang , Min-Hsiung Chiang , Chih-Yang Pai
IPC分类号： H01L27/108
CPC分类号： H01L27/105 , H01L27/10894 , H01L27/11 , H01L27/1116
摘要： A novel SOC structure and method of making the same are provided. An SOC comprises a logic region, an SRRM and a DRAM region. The storage capacitor in a DRAM cell is formed in the first dielectric layer in an MIM (metal-insulator-metal) configuration, having a large vertical surface area. A butted contact, formed in said first dielectric layer, comprises a bottom portion abutting a first and second conductive region in an SRAM cell, and a vertically aligned top portion coupled to a first metal layer. The top portion has a substantially larger depth than that of the bottom portion, while substantially smaller in size. Forming this SOC structure does not require adding complex, error-prone additional processing steps on an existing CMOS manufacturing process, thus having little impact on the overall SOC product yield.
摘要翻译：提供了一种新颖的SOC结构及其制造方法。 SOC包括逻辑区域，SRRM和DRAM区域。金属 - 绝缘体 - 金属）构造中的DRAM单元中的存储电容器形成在第一介电层中，具有大的垂直表面积。形成在所述第一电介质层中的对接触点包括邻接SRAM单元中的第一和第二导电区域的底部以及耦合到第一金属层的垂直对齐的顶部。顶部具有比底部大的深度大得多的深度，而其尺寸基本上更小。形成这种SOC结构不需要在现有的CMOS制造工艺上增加复杂的，容易出错的附加处理步骤，因此对整个SOC产品产量几乎没有影响。

9. 发明授权

US06670664B1 Single transistor random access memory (1T-RAM) cell with dual threshold voltages 有权
标题翻译：具有双阈值电压的单晶体管随机存取存储器（1T-RAM）单元
公开(公告)号：US06670664B1
公开(公告)日：2003-12-30
申请号：US10279809
申请日：2002-10-22
申请人： Kuo-Chyuan Tzeng , Dennis J. Sinitsky , Chen-Jong Wang , Wen-Chaun Chiang
发明人： Kuo-Chyuan Tzeng , Dennis J. Sinitsky , Chen-Jong Wang , Wen-Chaun Chiang
IPC分类号： H01L27108
CPC分类号： H01L27/10805 , H01L27/10873
摘要： A random access memory cell and a method for fabrication thereof provide a field effect transistor device laterally adjoining a metal oxide semiconductor capacitor device, each formed within an active region of a semiconductor substrate. Within the random access memory cell and method: (1) a single fluorinated silicon oxide layer of a single thickness serves as both a gate dielectric layer within the field effect transistor device and a capacitor dielectric layer within the metal oxide semiconductor capacitor device; and (2) a channel region within the field effect transistor device has a different threshold voltage adjusting dopant concentration in comparison with a semiconductor plate region within the metal oxide semiconductor capacitor device. The random access memory cell is fabricated with enhanced performance.
摘要翻译：随机存取存储单元及其制造方法提供横向邻接金属氧化物半导体电容器器件的场效应晶体管器件，每个形成在半导体衬底的有源区内。在随机存取存储器单元和方法中：（1）单个厚度的单个氟化硅氧化物层用作场效应晶体管器件内的栅极电介质层和金属氧化物半导体电容器器件内的电容器电介质层; 和（2）场效应晶体管器件内的沟道区域与金属氧化物半导体电容器件内的半导体板区域相比具有不同的阈值电压调整掺杂剂浓度。该随机存取存储器单元以增强的性能制造。

10. 发明授权

US08659121B2 Semiconductor devices with orientation-free decoupling capacitors and methods of manufacture thereof 有权
标题翻译：具有无取向去耦电容器的半导体器件及其制造方法
公开(公告)号：US08659121B2
公开(公告)日：2014-02-25
申请号：US13188343
申请日：2011-07-21
申请人： Kuo-Chi Tu , Kuo-Chyuan Tzeng , Wen-Chuan Chiang , Chen-Jong Wang
发明人： Kuo-Chi Tu , Kuo-Chyuan Tzeng , Wen-Chuan Chiang , Chen-Jong Wang
IPC分类号： H01L23/62
CPC分类号： H01L27/0207 , H01L28/40
摘要： Semiconductor devices with orientation-free decoupling capacitors and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes at least one integrated circuit and at least one decoupling capacitor. The at least one decoupling capacitor is oriented in a different direction than the at least one integrated circuit is oriented.
摘要翻译：公开了具有无取向去耦电容器的半导体器件及其制造方法。在一个实施例中，半导体器件包括至少一个集成电路和至少一个去耦电容器。至少一个去耦电容器被定向在与至少一个集成电路取向的方向不同的方向上。

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