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1. 发明申请

US20120250424A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20120250424A1
公开(公告)日：2012-10-04
申请号：US13432465
申请日：2012-03-28
申请人： Masahiro YOSHIHARA , Naofumi Abiko , Katsumi Abe
发明人： Masahiro YOSHIHARA , Naofumi Abiko , Katsumi Abe
IPC分类号： G11C7/06
CPC分类号： G11C7/1006 , G11C7/106 , G11C7/1087 , G11C16/0483 , G11C16/26
摘要： A sense amplifier circuit is connected to a bit-line and senses and amplifies a signal read from a memory cell. A first data latch is connected to a sense amplifier via a first bus. A second data latch is connected to a second bus. A plurality of circuit groups are repeatedly provided in a first direction, each circuit group comprising one sense amplifier circuit and one first data latch. The second data latch is provided between the circuit groups and an input/output buffer.
摘要翻译：感测放大器电路连接到位线，并感测并放大从存储单元读取的信号。第一数据锁存器通过第一总线连接到读出放大器。第二数据锁存器连接到第二总线。在第一方向重复提供多个电路组，每个电路组包括一个读出放大器电路和一个第一数据锁存器。第二数据锁存器设置在电路组和输入/输出缓冲器之间。

2. 发明授权

US08923074B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08923074B2
公开(公告)日：2014-12-30
申请号：US13432465
申请日：2012-03-28
申请人： Masahiro Yoshihara , Naofumi Abiko , Katsumi Abe
发明人： Masahiro Yoshihara , Naofumi Abiko , Katsumi Abe
IPC分类号： G11C7/10
CPC分类号： G11C7/1006 , G11C7/106 , G11C7/1087 , G11C16/0483 , G11C16/26
摘要： A sense amplifier circuit is connected to a bit-line and senses and amplifies a signal read from a memory cell. A first data latch is connected to a sense amplifier via a first bus. A second data latch is connected to a second bus. A plurality of circuit groups are repeatedly provided in a first direction, each circuit group including one sense amplifier circuit and one first data latch. The second data latch is provided between the circuit groups and an input/output buffer.
摘要翻译：感测放大器电路连接到位线，并感测并放大从存储器单元读取的信号。第一数据锁存器通过第一总线连接到读出放大器。第二数据锁存器连接到第二总线。多个电路组在第一方向上重复设置，每个电路组包括一个读出放大器电路和一个第一数据锁存器。第二数据锁存器设置在电路组和输入/输出缓冲器之间。

3. 发明授权

US08274845B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08274845B2
公开(公告)日：2012-09-25
申请号：US12793062
申请日：2010-06-03
申请人： Katsumi Abe , Masahiro Yoshihara , Masaru Koyanagi
发明人： Katsumi Abe , Masahiro Yoshihara , Masaru Koyanagi
IPC分类号： G11C7/00 , G11C16/00
CPC分类号： G11C7/1078 , G11C7/1084 , G11C16/04 , G11C16/20 , G11C29/02 , G11C29/028 , G11C2207/2254
摘要： A nonvolatile semiconductor memory device is provided, which includes an input buffer provided with a first inverter that can electrically adjust circuit threshold values, a circuit: threshold value monitor provided with a second inverter having the same circuit configuration as the first inverter to detect the circuit threshold values of the first inverter when the input and output of the second inverter are short-circuited, respectively, a memory storing parameter values that correspond to the circuit threshold values detected by the circuit threshold value monitor, and a data-reader circuit reading the parameter values given to the first inverter from the memory.
摘要翻译：提供了一种非易失性半导体存储器件，其包括：输入缓冲器，其具有能够电调节电路阈值的第一反相器;电路：具有与第一反相器相同电路结构的第二反相器的阈值监视器，用于检测电路分别在第二反相器的输入和输出短路时第一反相器的阈值，存储与由电路阈值监视器检测的电路阈值对应的参数值的存储器，读取数据读取器电路的数据读取器电路从存储器给予第一反相器的参数值。

4. 发明授权

US08228744B2 Semiconductor memory device having sense amplifier 有权
标题翻译：具有读出放大器的半导体存储器件
公开(公告)号：US08228744B2
公开(公告)日：2012-07-24
申请号：US12693798
申请日：2010-01-26
申请人： Masahiro Yoshihara , Katsumi Abe
发明人： Masahiro Yoshihara , Katsumi Abe
IPC分类号： G11C7/10
CPC分类号： G11C7/12 , G11C7/08 , G11C2207/005
摘要： A semiconductor memory device includes a memory cell array, a page buffer, a data line pair, a differential amplifier and a precharger. The memory cell array includes a plurality of pages in which a plurality of memory cells are arranged. The page buffer is formed adjacent to the memory cell array, and includes a plurality of sense amplifiers configured to temporarily hold page data read from the memory cells in the page. The data line pair is arranged in the page buffer and is connected to the sense amplifiers. The differential amplifier is configured to amplify a potential difference between lines of the data line pair. The precharger is configured to precharge the data line pair to a predetermined potential. At least one of the differential amplifier and the precharger is formed in the page buffer, and the at least one circuit is electrically connected to the data line pair.
摘要翻译：半导体存储器件包括存储单元阵列，页缓冲器，数据线对，差分放大器和预充电器。存储单元阵列包括多个存储单元布置在其中的多个页面。页面缓冲器形成在与存储单元阵列相邻的位置，并且包括多个读出放大器，被配置为临时保持从页面中的存储器单元读取的页面数据。数据线对被布置在页缓冲器中并连接到读出放大器。差分放大器被配置为放大数据线对的线之间的电位差。预充电器被配置为将数据线对预充电到预定电位。差分放大器和预充电器中的至少一个形成在页面缓冲器中，并且至少一个电路电连接到数据线对。

5. 发明申请

US20110205806A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20110205806A1
公开(公告)日：2011-08-25
申请号：US12884721
申请日：2010-09-17
申请人： Masahiro Yoshihara , Teruo Takagiwa , Katsumi Abe
发明人： Masahiro Yoshihara , Teruo Takagiwa , Katsumi Abe
IPC分类号： G11C16/34
CPC分类号： G11C16/3436
摘要： According to one embodiment, a semiconductor memory device includes memory cells, holding circuits, and a logical gate chain. The memory cells are associated with columns. The holding circuits are associated with the columns and capable of holding first information indicating whether associated one of the columns is a verify-failed column or not. The logical gate chain includes a plurality of first logical gates associated with the columns and connected in series. Each of the first logical gates outputs a logical level to a next-stage first logical gate in a series connection. The logical level indicates whether the verify-failed column exists or not based on the first information in associated one of the holding circuit. The content indicated by the logical level output from each of the first logical gates is inverted using one of the first logical gates associated with the verify-failed column as a border.
摘要翻译：根据一个实施例，半导体存储器件包括存储单元，保持电路和逻辑门极链。存储单元与列相关联。保持电路与列相关联，并且能够保存指示相关联的一个列是否为验证失败列的第一信息。逻辑门链包括与列相关联并且串联连接的多个第一逻辑门。第一逻辑门中的每一个在串联连接中将逻辑电平输出到下一级第一逻辑门。逻辑电平基于保持电路中相关联的一个中的第一信息指示验证失败列是否存在。使用与验证失败列相关联的第一逻辑门之一作为边界来反转从每个第一逻辑门输出的逻辑电平指示的内容。

6. 发明授权

US08797807B2 Semiconductor memory and semiconductor memory control method 有权
标题翻译：半导体存储器和半导体存储器控制方法
公开(公告)号：US08797807B2
公开(公告)日：2014-08-05
申请号：US13432708
申请日：2012-03-28
申请人： Masahiro Yoshihara , Katsumi Abe
发明人： Masahiro Yoshihara , Katsumi Abe
IPC分类号： G11C7/10 , G11C16/10 , G11C16/26
CPC分类号： G11C7/1078 , G11C7/08 , G11C7/1051 , G11C7/106 , G11C7/1087 , G11C7/12 , G11C7/22 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/3418 , G11C2207/2227 , G11C2207/2245
摘要： According to one embodiment, the semiconductor memory includes a memory cell array which includes memory cells to store data, a buffer circuit which includes latches, each of the latches including transistors as control elements and a flip-flop, and a control circuit which turns off the transistors to deactivate one or more of the latches.
摘要翻译：根据一个实施例，半导体存储器包括存储单元阵列，其包括用于存储数据的存储单元，包括锁存器的缓冲电路，每个锁存器包括作为控制元件的晶体管和触发器，以及控制电路，晶体管去激活一个或多个锁存器。

7. 发明授权

US08559226B2 Threshold detecting method and verify method of memory cells 有权
标题翻译：存储单元的阈值检测方法和验证方法
公开(公告)号：US08559226B2
公开(公告)日：2013-10-15
申请号：US13052148
申请日：2011-03-21
申请人： Katsumi Abe , Masahiro Yoshihara , Toshiaki Edahiro
发明人： Katsumi Abe , Masahiro Yoshihara , Toshiaki Edahiro
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/12 , G11C16/32 , G11C16/3468
摘要： According to one embodiment, a threshold detecting method for detecting threshold values of nonvolatile semiconductor memory cells comprises applying a preset voltage to a word line connected to the memory cells, and performing bit-line sense at two different timings during discharging of one of a bit line connected to the memory cells and a node corresponding to the bit line, while a potential of the word line is kept constant.
摘要翻译：根据一个实施例，用于检测非易失性半导体存储单元的阈值的阈值检测方法包括：将预设电压施加到连接到存储单元的字线，以及在放电期间的两个不同定时执行位线检测线连接到存储器单元和对应于位线的节点，而字线的电位保持恒定。

8. 发明申请

US20110305089A1 THRESHOLD DETECTING METHOD AND VERIFY METHOD OF MEMORY CELLS 有权
标题翻译：记忆细胞的阈值检测方法和验证方法
公开(公告)号：US20110305089A1
公开(公告)日：2011-12-15
申请号：US13052148
申请日：2011-03-21
申请人： Katsumi Abe , Masahiro Yoshihara , Toshiaki Edahiro
发明人： Katsumi Abe , Masahiro Yoshihara , Toshiaki Edahiro
IPC分类号： G11C16/34 , G11C16/26 , G11C16/12 , G11C16/04
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/12 , G11C16/32 , G11C16/3468
摘要： According to one embodiment, a threshold detecting method for detecting threshold values of nonvolatile semiconductor memory cells comprises applying a preset voltage to a word line connected to the memory cells, and performing bit-line sense at two different timings during discharging of one of a bit line connected to the memory cells and a node corresponding to the bit line, while a potential of the word line is kept constant.
摘要翻译：根据一个实施例，用于检测非易失性半导体存储单元的阈值的阈值检测方法包括：将预设电压施加到连接到存储单元的字线，以及在放电期间的两个不同定时执行位线检测线连接到存储器单元和对应于位线的节点，而字线的电位保持恒定。

9. 发明授权

US08284612B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08284612B2
公开(公告)日：2012-10-09
申请号：US12884721
申请日：2010-09-17
申请人： Masahiro Yoshihara , Teruo Takagiwa , Katsumi Abe
发明人： Masahiro Yoshihara , Teruo Takagiwa , Katsumi Abe
IPC分类号： G11C16/06
CPC分类号： G11C16/3436
摘要： According to one embodiment, a semiconductor memory device includes memory cells, holding circuits, and a logical gate chain. The memory cells are associated with columns. The holding circuits are associated with the columns and capable of holding first information indicating whether associated one of the columns is a verify-failed column or not. The logical gate chain includes a plurality of first logical gates associated with the columns and connected in series. Each of the first logical gates outputs a logical level to a next-stage first logical gate in a series connection. The logical level indicates whether the verify-failed column exists or not based on the first information in associated one of the holding circuit. The content indicated by the logical level output from each of the first logical gates is inverted using one of the first logical gates associated with the verify-failed column as a border.
摘要翻译：根据一个实施例，半导体存储器件包括存储单元，保持电路和逻辑门极链。存储单元与列相关联。保持电路与列相关联，并且能够保存指示相关联的一个列是否为验证失败列的第一信息。逻辑门链包括与列相关联并且串联连接的多个第一逻辑门。第一逻辑门中的每一个在串联连接中将逻辑电平输出到下一级第一逻辑门。逻辑电平基于保持电路中相关联的一个中的第一信息指示验证失败列是否存在。使用与验证失败列相关联的第一逻辑门之一作为边界来反转从每个第一逻辑门输出的逻辑电平指示的内容。

10. 发明申请

US20100309733A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20100309733A1
公开(公告)日：2010-12-09
申请号：US12793062
申请日：2010-06-03
申请人： Katsumi Abe , Masahiro Yoshihara , Masaru Koyanagi
发明人： Katsumi Abe , Masahiro Yoshihara , Masaru Koyanagi
IPC分类号： G11C7/10 , G11C7/00
CPC分类号： G11C7/1078 , G11C7/1084 , G11C16/04 , G11C16/20 , G11C29/02 , G11C29/028 , G11C2207/2254
摘要： A nonvolatile semiconductor memory device is provided, which includes an input buffer provided with a first inverter that can electrically adjust circuit threshold values, a circuit: threshold value monitor provided with a second inverter having the same circuit configuration as the first inverter to detect the circuit threshold values of the first inverter when the input and output of the second inverter are short-circuited, respectively, a memory storing parameter values that correspond to the circuit threshold values detected by the circuit threshold value monitor, and a data-reader circuit reading the parameter values given to the first inverter from the memory.
摘要翻译：提供了一种非易失性半导体存储器件，其包括：输入缓冲器，其具有能够电调节电路阈值的第一反相器;电路：具有与第一反相器相同电路结构的第二反相器的阈值监视器，用于检测电路分别在第二反相器的输入和输出短路时第一反相器的阈值，存储与由电路阈值监视器检测的电路阈值对应的参数值的存储器，读取数据读取器电路的数据读取器电路从存储器给予第一反相器的参数值。

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