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1. 发明授权

US08036021B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08036021B2
公开(公告)日：2011-10-11
申请号：US12620822
申请日：2009-11-18
申请人： Ryo Fukuda , Daisaburo Takashima
发明人： Ryo Fukuda , Daisaburo Takashima
IPC分类号： G11C11/14
CPC分类号： G11C11/405 , G11C5/063 , G11C7/18 , G11C8/14 , G11C11/4097 , H01L27/0207 , H01L27/10897
摘要： A memory cell array includes a plurality of memory cells arranged at intersections of bit line pairs and word lines. Each memory cell includes a first transistor having one main electrode connected to a first bit line, a second transistor having one main electrode connected to a second bit line, a first node electrode for data-storage connected to the other main electrode of the first transistor, a second node electrode for data-storage connected to the other main electrode of the second transistor, and a shield electrode formed surrounding the first and second node electrodes. The first and second transistors have respective gates both connected to an identical word line, and the first and second bit lines are connected to an identical sense amp. The first and second node electrodes, the first and second bit lines, the word line and the shield electrode are isolated from each other using insulating films.
摘要翻译：存储单元阵列包括布置在位线对和字线的交点处的多个存储单元。每个存储单元包括具有连接到第一位线的一个主电极的第一晶体管，具有连接到第二位线的一个主电极的第二晶体管，用于数据存储的第一节点电极连接到第一晶体管的另一个主电极，连接到第二晶体管的另一个主电极的用于数据存储的第二节点电极和围绕第一和第二节点电极形成的屏蔽电极。第一和第二晶体管具有连接到相同字线的相应门，并且第一和第二位线连接到相同的感测放大器。第一和第二节点电极，第一和第二位线，字线和屏蔽电极使用绝缘膜彼此隔离。

2. 发明授权

US07697318B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07697318B2
公开(公告)日：2010-04-13
申请号：US11964260
申请日：2007-12-26
申请人： Ryo Fukuda , Daisaburo Takashima
发明人： Ryo Fukuda , Daisaburo Takashima
IPC分类号： G11C11/24
CPC分类号： G11C11/405 , G11C5/063 , G11C7/18 , G11C8/14 , G11C11/4097 , H01L27/0207 , H01L27/10897
摘要： A memory cell array includes a plurality of memory cells arranged at intersections of bit line pairs and word lines. Each memory cell includes a first transistor having one main electrode connected to a first bit line, a second transistor having one main electrode connected to a second bit line, a first node electrode for data-storage connected to the other main electrode of the first transistor, a second node electrode for data-storage connected to the other main electrode of the second transistor, and a shield electrode formed surrounding the first and second node electrodes. The first and second transistors have respective gates both connected to an identical word line, and the first and second bit lines are connected to an identical sense amp. The first and second node electrodes, the first and second bit lines, the word line and the shield electrode are isolated from each other using insulating films.
摘要翻译：存储单元阵列包括布置在位线对和字线的交点处的多个存储单元。每个存储单元包括具有连接到第一位线的一个主电极的第一晶体管，具有连接到第二位线的一个主电极的第二晶体管，用于数据存储的第一节点电极连接到第一晶体管的另一个主电极，连接到第二晶体管的另一个主电极的用于数据存储的第二节点电极和围绕第一和第二节点电极形成的屏蔽电极。第一和第二晶体管具有连接到相同字线的相应门，并且第一和第二位线连接到相同的感测放大器。第一和第二节点电极，第一和第二位线，字线和屏蔽电极使用绝缘膜彼此隔离。

3. 发明授权

US5418750A Semiconductor memory device for suppressing noises occurring on bit and word lines 失效
标题翻译：用于抑制位和字线上发生的噪声的半导体存储器件
公开(公告)号：US5418750A
公开(公告)日：1995-05-23
申请号：US200107
申请日：1994-02-22
申请人： Shinichiro Shiratake , Takehiro Hasegawa , Daisaburo Takashima , Ryu Ogiwara , Ryo Fukuda
发明人： Shinichiro Shiratake , Takehiro Hasegawa , Daisaburo Takashima , Ryu Ogiwara , Ryo Fukuda
IPC分类号： G11C11/407 , G11C11/405 , G11C11/4091 , G11C11/4096 , G11C11/4097 , G11C7/00
CPC分类号： G11C11/4096 , G11C11/4091 , G11C11/4097
摘要： A semiconductor memory device includes a series of memory cells, a series of bit lines respectively connected to the memory cells, a series of sense amplifiers, connected to corresponding bit line groups including predetermined number of bit lines of the series of bit lines, for reading out data of memory cells connected to bit lines of the bit line group, the bit line groups including at least adjacent first and second bit line groups, at least first and second transistors allocated between the bit lines and the sense amplifiers and having gates, for selectively connecting the bit lines and the sense amplifiers, and a series of control signal lines commonly connected to the first transistors connected to the first bit line groups and the second transistors connected to the second bit line groups, such that the first transistors connected to the first bit line groups are regularly arranged in one direction, and second transistors connected to the second bit line groups adjacent to the first bit line groups are regularly arranged in an opposite direction.
摘要翻译：半导体存储器件包括一系列存储器单元，分别连接到存储器单元的一系列位线，一系列读出放大器，连接到包括一系列位线的预定数量位线的相应位线组，用于读取连接到位线组的位线的存储器单元的输出数据，位线组包括至少相邻的第一和第二位线组，分配在位线和读出放大器之间并具有门的至少第一和第二晶体管，用于选择性地连接位线和读出放大器，以及一系列控制信号线，共同连接到连接到第一位线组的第一晶体管和连接到第二位线组的第二晶体管，使得连接到第一位线组的第一晶体管第一位线组在一个方向上规则地排列，第二晶体管连接到第二位线组第一位线组以相反的方向规则地布置。

4. 发明申请

US20120068256A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US20120068256A1
公开(公告)日：2012-03-22
申请号：US13232492
申请日：2011-09-14
申请人： Ryo Fukuda , Yoshihisa Iwata
发明人： Ryo Fukuda , Yoshihisa Iwata
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/11578 , G11C16/0416 , H01L27/11565 , H01L27/11582 , H01L29/66833 , H01L29/7926
摘要： An dielectric film is formed above the semiconductor substrate. A first conductive layer is formed in the dielectric film and extending in a first direction. The first conductive layer is connected to a first select transistor. A second conductive layer formed in the dielectric film and extending in the first direction. The second conductive layer is connected to a second select transistor. A semiconductor layer is connected to both the first and second conductive layers and functioning as a channel layer of a memory transistor. A gate-insulating film is formed on the semiconductor layer. The gate-insulating film includes a charge accumulation film as a portion thereof. A third conductive layer is surrounded by the gate-insulating film.
摘要翻译：在半导体衬底上方形成绝缘膜。第一导电层形成在电介质膜中并沿第一方向延伸。第一导电层连接到第一选择晶体管。形成在电介质膜中并沿第一方向延伸的第二导电层。第二导电层连接到第二选择晶体管。半导体层连接到第一和第二导电层两者并用作存储晶体管的沟道层。在半导体层上形成栅极绝缘膜。栅极绝缘膜包括作为其一部分的电荷累积膜。第三导电层被栅极绝缘膜包围。

5. 发明授权

US07958279B2 Asynchronous serial data apparatus for transferring data between one transmitter and a plurality of shift registers, avoiding skew during transmission 失效
标题翻译：用于在一个发射机和多个移位寄存器之间传送数据的异步串行数据装置，避免传输期间的偏斜
公开(公告)号：US07958279B2
公开(公告)日：2011-06-07
申请号：US12405953
申请日：2009-03-17
申请人： Tomohisa Takai , Ryo Fukuda
发明人： Tomohisa Takai , Ryo Fukuda
IPC分类号： G06F13/00 , G06F13/12
CPC分类号： G06F13/4282
摘要： A semiconductor integrated circuit apparatus, comprising a data transmitter circuit, and a plurality of data receiver circuits each having a data converter circuit which restores each of bits of identification number data and transfer data from a shift register of the data transmitter circuit to 2-bit complementary data transmitted via first and second transmission lines, a reception control circuit which, when a transfer completion signal has been received via a third transmission line, compares an allocated identification number with the restored identification number data, and a shift register provided in association with the reception control circuit, wherein each reception control circuit feeds transfer data transmitted from the data transmitter circuit corresponding to the identification number data to the associated shift register in accordance with a result of comparison between the identification number data and the allocated identification number.
摘要翻译：一种半导体集成电路装置，包括数据发送器电路和多个数据接收器电路，每个数据接收器电路具有数据转换器电路，其恢复识别号码数据的每一位并将数据从数据发送器电路的移位寄存器传送到2位通过第一和第二传输线传输的补充数据;接收控制电路，当经由第三传输线接收到传送完成信号时，将分配的识别号与恢复的标识号数据进行比较，以及移位寄存器接收控制电路，其中每个接收控制电路根据识别号码数据和所分配的识别号码之间的比较结果，将对应于识别号码数据的数据发送器电路发送的传送数据提供给相关联的移位寄存器。

6. 发明授权

US07609551B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07609551B2
公开(公告)日：2009-10-27
申请号：US11860956
申请日：2007-09-25
申请人： Tomoaki Shino , Akihiro Nitayama , Takeshi Hamamoto , Hideaki Aochi , Takashi Ohsawa , Ryo Fukuda
发明人： Tomoaki Shino , Akihiro Nitayama , Takeshi Hamamoto , Hideaki Aochi , Takashi Ohsawa , Ryo Fukuda
IPC分类号： G11C14/00 , G11C16/04
CPC分类号： H01L29/792 , G11C11/404 , G11C11/4074 , G11C14/0018 , G11C2211/4016 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L27/1203 , H01L29/42344 , H01L29/785 , H01L29/78648
摘要： This disclosure concerns a memory comprising a charge trapping film; a gate insulating film; a back gate on the charge trapping film; a front gate on the gate insulating film; and a body region provided between a drain and a source, wherein the memory includes a first storage state for storing data depending on the number of majority carriers in the body region and a second storage state for storing data depending on the amount of charges in the charge trapping film, and the memory is shifted from the first storage state to the second storage state by converting the number of majority carriers in the body region into the amount of charges in the charge trapping film or from the second storage state to the first storage state by converting the amount of charges in the charge trapping film into the number of majority carriers in the body region.
摘要翻译：本公开涉及包含电荷捕获膜的存储器; 栅极绝缘膜; 电荷捕获膜上的后门; 栅极绝缘膜上的前门; 以及设置在漏极和源极之间的体区，其中所述存储器包括用于根据所述身体区域中的多数载体的数量存储数据的第一存储状态和用于根据所述体内区域中的电荷量存储数据的第二存储状态通过将身体区域中的多数载体的数量转换为电荷俘获膜中的电荷量或从第二存储状态到第一存储器，将存储器从第一存储状态转移到第二存储状态通过将电荷俘获膜中的电荷量转换成体区中的多数载体的数量来进行状态。

7. 发明授权

US07602657B2 Semiconductor memory device having floating body cell 失效
标题翻译：具有浮体电池的半导体存储器件
公开(公告)号：US07602657B2
公开(公告)日：2009-10-13
申请号：US11950097
申请日：2007-12-04
申请人： Ryo Fukuda
发明人： Ryo Fukuda
IPC分类号： G11C7/00
CPC分类号： G11C11/404 , G11C7/065 , G11C7/08 , G11C7/12 , G11C11/4091 , G11C11/4094 , G11C2207/005 , G11C2207/2281 , G11C2211/4016
摘要： A semiconductor memory device includes a sense amplifier for the FBC, a first node and a second node can be disconnected from each other by a first isolation transistor. A third node and a fourth node can be disconnected from each other by a second isolation transistor. The first node is connected to the first memory cell. The third node is connected to the second memory cell. A first amplification transistor and a second amplification transistor are connected between the first node and the third node. A third amplification transistor and a fourth amplification transistor are connected between the second node and the fourth node. This enables to parallelly execute read data transfer to the data lines and precharge to prepare for the next read operation.
摘要翻译：半导体存储器件包括用于FBC的读出放大器，第一节点和第二节点可以通过第一隔离晶体管彼此断开。第三节点和第四节点可以通过第二隔离晶体管彼此断开。第一个节点连接到第一个存储单元。第三节点连接到第二个存储单元。第一放大晶体管和第二放大晶体管连接在第一节点和第三节点之间。第三放大晶体管和第四放大晶体管连接在第二节点和第四节点之间。这使得能够并行地执行对数据线的读取数据传输并预充电以准备下一次读取操作。

8. 发明申请

US20090183020A1 ASYNCHRONOUS SERIAL DATA APPARATUS FOR TRANSFERRING DATA BETWEEN ONE TRANSMITTER AND A PLURALITY OF SHIFT REGISTERS, AVOIDING SKEW DURING TRANSMISSION 失效
标题翻译：用于在一台发射机和多台移动寄存器之间传输数据的异步串行数据设备，传输期间避开千兆位
公开(公告)号：US20090183020A1
公开(公告)日：2009-07-16
申请号：US12405953
申请日：2009-03-17
申请人： Tomohisa Takai , Ryo Fukuda
发明人： Tomohisa Takai , Ryo Fukuda
IPC分类号： G06F1/08
CPC分类号： G06F13/4282
摘要： A semiconductor integrated circuit apparatus, comprising a data transmitter circuit, and a plurality of data receiver circuits each having a data converter circuit which restores each of bits of identification number data and transfer data from a shift register of the data transmitter circuit to 2-bit complementary data transmitted via first and second transmission lines, a reception control circuit which, when a transfer completion signal has been received via a third transmission line, compares an allocated identification number with the restored identification number data, and a shift register provided in association with the reception control circuit, wherein each reception control circuit feeds transfer data transmitted from the data transmitter circuit corresponding to the identification number data to the associated shift register in accordance with a result of comparison between the identification number data and the allocated identification number.
摘要翻译：一种半导体集成电路装置，包括数据发送器电路和多个数据接收器电路，每个数据接收器电路具有数据转换器电路，其恢复识别号码数据的每一位并将数据从数据发送器电路的移位寄存器传送到2位通过第一和第二传输线传输的补充数据;接收控制电路，当经由第三传输线接收到传送完成信号时，将分配的识别号与恢复的标识号数据进行比较，以及移位寄存器接收控制电路，其中每个接收控制电路根据识别号码数据和所分配的识别号码之间的比较结果，将对应于识别号码数据的数据发送器电路发送的传送数据提供给相关联的移位寄存器。

9. 发明申请

US20080251830A1 SEMICONDUCTOR STORAGE DEVICE AND DRIVING METHOD THEREOF 失效
标题翻译：半导体存储器件及其驱动方法
公开(公告)号：US20080251830A1
公开(公告)日：2008-10-16
申请号：US12060522
申请日：2008-04-01
申请人： Tomoki Higashi , Takashi Ohsawa , Ryo Fukuda
发明人： Tomoki Higashi , Takashi Ohsawa , Ryo Fukuda
IPC分类号： H01L27/102 , G11C16/04
CPC分类号： H01L27/1022 , G11C11/4023 , G11C11/4026 , G11C11/405 , G11C11/4085 , G11C2211/4016 , H01L21/8249 , H01L21/84 , H01L27/0207 , H01L27/105 , H01L27/1052 , H01L27/108 , H01L27/10802 , H01L27/1203 , H01L29/7841
摘要： This disclosure concerns a semiconductor storage device comprising a semiconductor layer provided on the insulation layer provided on the semiconductor substrate; a source layer and a drain layer provided in the semiconductor layer; a body provided between the source layer and the drain layer, the body being in an electrically floating state; an emitter layer contacting with the source layer, the emitter layer having an opposite conductive type to the source layer; a word line including the source layer, the drain layer, and the body, the word line being provided to memory cells arrayed in a first direction in a plurality of tow-dimensionally arranged memory cells; a source line connected to the source layers of the memory cells arrayed in the first direction; and a bit line connected to the drain layers of the memory cells arrayed in a second direction intersecting the first direction.
摘要翻译：本公开涉及一种半导体存储装置，其包括设置在设置在半导体衬底上的绝缘层上的半导体层; 设置在所述半导体层中的源极层和漏极层; 设置在所述源极层和所述漏极层之间的主体，所述主体处于电浮动状态; 与源极层接触的发射极层，发射极层与源极层具有相反的导电类型; 包括源层，漏极层和主体的字线，字线被提供给在多个维度上排列的存储单元中沿第一方向排列的存储单元; 连接到沿着第一方向排列的存储单元的源层的源极线; 以及连接到沿与第一方向相交的第二方向排列的存储单元的漏极层的位线。

10. 发明授权

US07379350B2 Semiconductor memory device operating using read only memory data 失效
标题翻译：半导体存储器件使用只读存储器数据进行操作
公开(公告)号：US07379350B2
公开(公告)日：2008-05-27
申请号：US11487514
申请日：2006-07-17
申请人： Ryo Fukuda
发明人： Ryo Fukuda
IPC分类号： G11C11/00
CPC分类号： G11C7/20 , G11C29/802 , G11C2029/3202
摘要： A semiconductor memory device operating using initialization data, includes a first latch circuit which latches the initialization data, a memory cell array including a plurality of memory cells and having a first region and a second region, the first region storing data, and a buffer circuit having a function for accessing the first latch circuit, the buffer circuit transferring, to the second region, the initialization data transferred from the first latch circuit, and transferring, to the first latch circuit, the initialization data transferred form the second region.
摘要翻译：使用初始化数据操作的半导体存储器件包括锁存初始化数据的第一锁存电路，包括多个存储器单元并具有第一区域和第二区域的存储单元阵列，第一区域存储数据，以及缓冲电路具有访问第一锁存电路的功能，缓冲电路向第二区域传送从第一锁存电路传送的初始化数据，并将从第二区域传送的初始化数据传送到第一锁存电路。

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