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1. 发明申请

US20180163323A1 METHOD FOR PRODUCING GROUP 13 NITRIDE SINGLE CRYSTAL AND APPARATUS FOR PRODUCING GROUP 13 NITRIDE SINGLE CRYSTAL 审中-公开
公开(公告)号：US20180163323A1
公开(公告)日：2018-06-14
申请号：US15891764
申请日：2018-02-08
申请人： Takashi Satoh , Naoya Miyoshi , Junichi Wada , Masahiro Hayashi , Seiji Sarayama , Haruo Sunakawa , Yujirou Ishihara , Akira Usui
发明人： Takashi Satoh , Naoya Miyoshi , Junichi Wada , Masahiro Hayashi , Seiji Sarayama , Haruo Sunakawa , Yujirou Ishihara , Akira Usui
IPC分类号： C30B29/40 , C30B19/04 , C30B19/06 , C30B19/10 , C30B17/00 , C30B35/00
CPC分类号： C30B29/403 , C30B9/10 , C30B9/12 , C30B17/00 , C30B19/02 , C30B19/04 , C30B19/06 , C30B19/106 , C30B29/406 , C30B35/007
摘要： A method for producing a group 13 nitride single crystal includes dissolving and crystal growing. The dissolving includes dissolving nitrogen in a mixed melt in a reaction vessel that contains the mixed melt, a seed crystal, and a surrounding member. The mixed melt contains an alkali metal and a group 13 metal. The seed crystal is a seed crystal that is placed in the mixed melt and includes a group 13 nitride crystal in which a principal face is a c-plane. The surrounding member is arranged so as to surround the entire area of a side face of the seed crystal. The crystal growing includes growing a group 13 nitride crystal on the seed crystal.

2. 发明授权

US06348096B1 Method for manufacturing group III-V compound semiconductors 失效
标题翻译： III-V族化合物半导体的制造方法
公开(公告)号：US06348096B1
公开(公告)日：2002-02-19
申请号：US09038273
申请日：1998-03-11
申请人： Haruo Sunakawa , Akira Usui
发明人： Haruo Sunakawa , Akira Usui
IPC分类号： C30B2504
CPC分类号： C30B25/02 , C30B29/40 , C30B29/403 , C30B29/406 , H01L21/0237 , H01L21/0254 , H01L21/0262 , H01L21/02639 , H01L33/007 , H01L33/0075 , Y10T117/10
摘要： The Group III-V compound semiconductor manufacturing method which pertains to the present invention is a semiconductor manufacturing method employing epitaxy which comprises (a) a step in which growing areas are produced using a mask patterned on a substrate surface and (b) a step in which a Group III-V compound semiconductor layer is grown in the growing areas while forming facet structures. As epitaxy is continued, adjacent facet structures come into contact so that the surface of the semiconductor layer becomes planarized. Since lattice defects extend towards the facet structures, they do not extend towards the surface of the semiconductor layer. Accordingly, the number of lattice defects in the vicinity of the semiconductor layer surface is reduced.
摘要翻译：涉及本发明的III-V族化合物半导体制造方法是使用外延的半导体制造方法，其包括（a）使用在基板表面上图案化的掩模制造生长区域的步骤，（b）其中III-V族化合物半导体层在生长区域中生长，同时形成小面结构。随着外延继续，相邻的小面结构接触，使得半导体层的表面变平坦化。由于晶格缺陷朝着小平面结构延伸，所以它们不向半导体层的表面延伸。因此，半导体层表面附近的晶格缺陷的数量减少。

3. 发明授权

US06555845B2 Method for manufacturing group III-V compound semiconductors 有权
公开(公告)号：US06555845B2
公开(公告)日：2003-04-29
申请号：US10014900
申请日：2001-12-14
申请人： Haruo Sunakawa , Akira Usui
发明人： Haruo Sunakawa , Akira Usui
IPC分类号： H01L2715
CPC分类号： C30B25/02 , C30B29/40 , C30B29/403 , C30B29/406 , H01L21/0237 , H01L21/0254 , H01L21/0262 , H01L21/02639 , H01L33/007 , H01L33/0075 , Y10T117/10
摘要： The Group III-V compound semiconductor manufacturing method which pertains to the present invention is a semiconductor manufacturing method employing epitaxy which comprises (a) a step in which growing areas are produced using a mask patterned on a substrate surface and (b) a step in which a Group III-V compound semiconductor layer is grown in the growing areas while forming facet structures. As epitaxy is continued, adjacent facet structures come into contact so that the surface of the semiconductor layer becomes planarized. Since lattice defects extend towards the facet structures, they do not extend towards the surface of the semiconductor layer. Accordingly, the number of lattice defects in the vicinity of the semiconductor layer surface is reduced.

4. 发明授权

US06252261B1 GaN crystal film, a group III element nitride semiconductor wafer and a manufacturing process therefor 有权
标题翻译： GaN晶体膜，III族元素氮化物半导体晶片及其制造方法
公开(公告)号：US06252261B1
公开(公告)日：2001-06-26
申请号：US09342003
申请日：1999-06-28
申请人： Akira Usui , Akira Sakai , Haruo Sunakawa , Masashi Mizuta , Yoshishige Matsumoto
发明人： Akira Usui , Akira Sakai , Haruo Sunakawa , Masashi Mizuta , Yoshishige Matsumoto
IPC分类号： H01L310328
CPC分类号： H01L21/02378 , B82Y20/00 , H01L21/0242 , H01L21/02458 , H01L21/0254 , H01L21/0262 , H01L21/02639 , H01L21/02647 , H01L21/02658 , H01L29/2003 , H01S5/0202 , H01S5/0213 , H01S5/0217 , H01S5/34333 , H01S2304/12
摘要： A GaN crystal film having a mask patterned in a stripe for forming multiple growing areas on a sapphire substrate and coalesced GaN crystals covering the mask dividing the areas, grown from the neighboring growing areas, comprising defects where multiple dislocations along with the stripe are substantially aligned with the normal line of the substrate, in the crystal areas over the mask, and dislocations propagating in substantially parallel with the substrate surface while, in the vicinity of the areas where the crystals are coalesced over the mask, propagating substantially in the normal line of the substrate surface, and a manufacturing process therefor. According to this invention, there can be provided a GaN crystal film in which strain, defects and dislocations are reduced and which tends not to generate cracks.
摘要翻译：一种GaN晶体膜，其具有在条纹上图案化的掩模，用于在蓝宝石衬底上形成多个生长区域，并且覆盖覆盖从相邻生长区域生长的区域的掩模的聚结的GaN晶体，其包括与条纹多个位错基本对齐的缺陷与衬底的法线，在掩模上方的晶体区域中，以及基本上平行于衬底表面传播的位错，而在晶体结合在掩模上的区域附近，基本上在基板表面及其制造工艺。根据本发明，可以提供一种其中应变，缺陷和位错减少并且不会产生裂纹的GaN晶体膜。

5. 发明授权

US6096130A Method of crystal growth of a GaN layer over a GaAs substrate 失效
标题翻译： GaAs衬底上的GaN层的晶体生长方法
公开(公告)号：US6096130A
公开(公告)日：2000-08-01
申请号：US824017
申请日：1997-03-21
申请人： Akitaka Kimura , Haruo Sunakawa , Masaaki Nido
发明人： Akitaka Kimura , Haruo Sunakawa , Masaaki Nido
IPC分类号： C30B29/38 , C30B25/02 , H01L21/205 , H01L33/12 , H01L33/16 , H01L33/32 , H01S5/00 , H01S5/323 , C30B25/14
CPC分类号： C30B25/02 , C30B29/406 , H01L21/02395 , H01L21/02433 , H01L21/02458 , H01L21/02463 , H01L21/0254 , H01L21/02614 , H01L21/0262 , H01L21/02661
摘要： A method of crystal growth of a GaN layer with an extremely high surface planarity over a GaAs substrate is provided, wherein a GaAs substrate is heated to a temperature in the range of 600.degree. C. to 700.degree. C. without supplying any group-V element including arsenic to form a Ga-rich surface on the GaAs substrate, before a first source material including N and a second source material including Ga are supplied along with a carrier gas onto a surface of the GaAs substrate to form a GaN layer over the GaAs substrate.
摘要翻译：提供了一种在GaAs衬底上具有极高表面平面度的GaN层的晶体生长方法，其中将GaAs衬底加热至600℃至700℃的温度，而不提供任何V族在包括N的第一源材料和包含Ga的第二源材料在内的GaAs衬底上形成富镓表面的元素与载气一起被供应到GaAs衬底的表面上以在GaAs衬底的表面上形成GaN层 GaAs衬底。

6. 发明授权

US5843227A Crystal growth method for gallium nitride films 失效
标题翻译：氮化镓薄膜的晶体生长方法
公开(公告)号：US5843227A
公开(公告)日：1998-12-01
申请号：US782075
申请日：1997-01-13
申请人： Akitaka Kimura , Haruo Sunakawa , Masaaki Nido , Atsushi Yamaguchi
发明人： Akitaka Kimura , Haruo Sunakawa , Masaaki Nido , Atsushi Yamaguchi
IPC分类号： C30B29/38 , C30B25/02 , C30B25/18 , H01L21/205 , H01L33/16 , H01L33/32 , H01S5/00 , H01S5/323
CPC分类号： C30B25/02 , C30B25/18 , C30B29/406
摘要： A crystal growth method for growing on a gallium arsenide (GaAs) substrate a gallium nitride (GaN) film which is good in surface flatness and superior in crystallinity. According to the method, a GaAs substrate having a surface which is inclined with respect to the GaAs(100) face is used. The inclination angle of the substrate surface is larger than 0 degree but smaller than 35 degrees with respect to the GaAs(100) face. The inclination direction of the substrate surface is within a range of an angular range from the �0,0,1! direction of GaAs to the �0,-1,0! direction past the �0,-1,1! direction and angles less than 5 degrees on opposite sides of the angular range around an �1,0,0! direction of gallium arsenide taken as an axis, or within another range crystallographically equivalent to the range. The GaN layer is formed on the surface of the GaAs substrate preferably by hydride vapor deposition method.
摘要翻译：一种晶体生长方法，用于在砷化镓（GaAs）衬底上生长表面平坦度好并且结晶度优异的氮化镓（GaN）膜。根据该方法，使用具有相对于GaAs（100）面倾斜的表面的GaAs衬底。衬底表面的倾斜角度相对于GaAs（100）面大于0度但小于35度。衬底表面的倾斜方向在从GaAs的[0,0,1]方向到[0，-1,1]方向的[0，-1,0]方向的角度范围的范围内，以及在作为轴的砷化镓的[1,0.0]方向的角度范围的相对侧的角度小于5度，或在与该范围相似的等距范围内的角度。优选通过氢化物气相沉积法在GaAs衬底的表面上形成GaN层。

7. 发明授权

US06809351B2 Group III-V compound semiconductor crystal structure and method of epitaxial growth of the same as well as semiconductor device including the same 有权
标题翻译： III-V族化合物半导体晶体结构及其外延生长方法以及包括其的半导体器件
公开(公告)号：US06809351B2
公开(公告)日：2004-10-26
申请号：US10091437
申请日：2002-03-07
申请人： Masaru Kuramoto , Haruo Sunakawa
发明人： Masaru Kuramoto , Haruo Sunakawa
IPC分类号： H01L310328
CPC分类号： C30B25/02 , C30B25/04 , C30B29/403 , C30B29/406 , H01L21/0237 , H01L21/02381 , H01L21/02392 , H01L21/02395 , H01L21/0242 , H01L21/02433 , H01L21/02458 , H01L21/0254 , H01L21/02639 , H01L21/02647
摘要： A Group III-V compound semiconductor epitaxial layer has a tilt angle of at most 100 seconds and/or a tilt angle of at most 100 seconds. The layer is epitaxially grown by use of a mask, wherein the mask satisfies the equation (1): h≧(w/2)tan &thgr; (1) where “&thgr;” is a base angle of a facet structure of the Group III-V compound semiconductor layer on the epitaxial growth; “h” is a thickness of the mask; and “w” is an opening width of the mask at its lower level, and the opening width is defined in a direction included in a plane which is vertical to both the surface of the base layer and the side face of the facet structure.
摘要翻译： III-V族化合物半导体外延层具有至多100秒的倾斜角和/或至多100秒的倾斜角。该层通过掩模外延生长，其中掩模满足等式（1）：其中“θ”是第III-V族化合物半导体层在外延生长时的小平面结构的底角; “h”是掩模的厚度; 并且“w”是掩模在其较低水平处的开口宽度，并且开口宽度被限定在垂直于基底层的表面和小面结构的侧面的平面中的方向上。

8. 发明授权

US4845049A Doping III-V compound semiconductor devices with group VI monolayers using ALE 失效
标题翻译：掺杂III-V化合物半导体器件，使用ALE的VI组单层
公开(公告)号：US4845049A
公开(公告)日：1989-07-04
申请号：US173808
申请日：1988-03-28
申请人： Haruo Sunakawa
发明人： Haruo Sunakawa
IPC分类号： H01L21/20 , H01L21/205
CPC分类号： H01L21/0262 , H01L21/02395 , H01L21/02463 , H01L21/02499 , H01L21/02546 , H01L21/02576 , H01L21/02584 , Y10S148/04 , Y10S148/065 , Y10S148/11
摘要： An n-type III-V compound semiconductor comprises a plurality of monolayers of III-V compound semiconductor molecules having a layer-by-layer structure of group III element and group V element laminated alternately, and a group VI element-doped monolayer. The group VI element-doped monolayer is inserted into the III-V compound semiconductor molecules by occupying lattice points which were occupied by the group V element. The layers of the semiconductor are grown by Atomic Layer Epitaxy process.
摘要翻译： n型III-V族化合物半导体包括具有交替层叠的III族元素和V族元素的层叠结构的III-V族化合物半导体分子的多个单层和VI族元素掺杂单层。通过占据由V族元素占据的晶格点，将VI族元素掺杂单层插入到III-V族化合物半导体分子中。通过原子层外延工艺生长半导体层。

9. 发明授权

US5825053A Heterostructure III-V nitride semiconductor device including InP substrate 失效
标题翻译：异质结构III-V族氮化物半导体器件包括InP衬底
公开(公告)号：US5825053A
公开(公告)日：1998-10-20
申请号：US799828
申请日：1997-02-13
申请人： Akitaka Kimura , Haruo Sunakawa , Masaaki Nido , Atsushi Yamaguchi
发明人： Akitaka Kimura , Haruo Sunakawa , Masaaki Nido , Atsushi Yamaguchi
IPC分类号： C30B29/38 , H01L21/205 , H01L33/16 , H01L33/20 , H01L33/32 , H01S5/00 , H01L33/00
CPC分类号： H01L33/0075
摘要： In a heterostructure III-V nitride semiconductor device, an InP substrate has a surface having a sloped angle of 0.degree. to 16.degree. with respect to a (100) surface thereof. At least one GaN layer is formed on the InP substrate.
摘要翻译：在异质结构III-V族氮化物半导体器件中，InP衬底具有相对于其（100）表面具有0°至16°的倾斜角的表面。在InP衬底上形成至少一个GaN层。

10. 发明授权

US4859627A Group VI doping of III-V semiconductors during ALE 失效
标题翻译： ALE期间III-V族半导体掺杂VI族
公开(公告)号：US4859627A
公开(公告)日：1989-08-22
申请号：US214241
申请日：1988-07-01
申请人： Haruo Sunakawa
发明人： Haruo Sunakawa
IPC分类号： C30B25/02 , C30B29/40 , H01L21/205
CPC分类号： H01L21/02395 , H01L21/02392 , H01L21/02461 , H01L21/02463 , H01L21/02543 , H01L21/02546 , H01L21/02576 , H01L21/02584 , H01L21/0262 , Y10S148/04 , Y10S148/065 , Y10S148/11
摘要： A method of producing n-type III-V compound semiconductor comprises growing a plurality of monolayers of III-V compound semiconductor molecules on a III-V compound substrate; growing a single layer of group VI element on the III-V monolayers so as to occupy the lattice points for group V element by means of Atomic Layer Epitaxy process; decreasing the number of group VI element by exposing the single layer to the gas of group V element; and growing a plurality of monolayers of III-V compound semiconductor molecules on the group VI element-doped layer by means of the Atomic Layer Epitaxy process.
摘要翻译：制造n型III-V族化合物半导体的方法包括在III-V族化合物基板上生长III-V族化合物半导体分子的多个单层; 在III-V单层上生长单层VI族元素，通过原子层外延法占据V族元素的晶格点; 通过将单层暴露于V族元素的气体来减少VI族元素的数量; 并通过原子层外延法在VI族元素掺杂层上生长多个单层III-V族化合物半导体分子。

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