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1. 发明授权

US09012967B2 1T MIM memory for embedded RAM application in soc 有权
标题翻译： 1T MIM存储器，用于soc中的嵌入式RAM应用
公开(公告)号：US09012967B2
公开(公告)日：2015-04-21
申请号：US13369894
申请日：2012-02-09
申请人： Yi-Ching Lin , Chun-Yao Chen , Chen-Jong Wang , Shou-Gwo Wuu , Chung S. Wang , Chien-Hua Huang , Kun-Lung Chen , Ping Yang
发明人： Yi-Ching Lin , Chun-Yao Chen , Chen-Jong Wang , Shou-Gwo Wuu , Chung S. Wang , Chien-Hua Huang , Kun-Lung Chen , Ping Yang
IPC分类号： H01L27/108 , H01L29/94 , H01L27/02
CPC分类号： H01L27/10897 , H01L27/0207 , H01L27/10852 , H01L27/10894
摘要： Embedded memories. The devices include a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of capacitors. The substrate comprises transistors. The first dielectric layer, embedding first and second conductive plugs electrically connecting the transistors therein, overlies the substrate. The second dielectric layer, comprising a plurality of capacitor openings exposing the first conductive plugs, overlies the first dielectric layer. The capacitors comprise a plurality of bottom plates, respectively disposed in the capacitor openings, electrically connecting the first conductive plugs, a plurality of capacitor dielectric layers respectively overlying the bottom plates, and a top plate, comprising a top plate opening, overlying the capacitor dielectric layers. The top plate opening exposes the second dielectric layer, and the top plate is shared by the capacitors.
摘要翻译：嵌入式记忆这些器件包括衬底，第一介电层，第二电介质层，第三电介质层和多个电容器。衬底包括晶体管。第一介电层，嵌入电连接其中的晶体管的第一和第二导电插塞覆盖在基板上。包括暴露第一导电插塞的多个电容器开口的第二电介质层覆盖在第一电介质层上。电容器包括分别设置在电容器开口中的多个底板，电连接第一导电插塞，分别覆盖在底板上的多个电容器电介质层，以及顶板，包括覆盖电容器电介质的顶板开口层。顶板开口暴露第二电介质层，并且顶板由电容器共享。

2. 发明申请

US20120139022A1 1T MIM MEMORY FOR EMBEDDED RAM APPLICATION IN SOC 审中-公开
标题翻译： 1T MIM存储器嵌入式RAM应用于SOC
公开(公告)号：US20120139022A1
公开(公告)日：2012-06-07
申请号：US13369894
申请日：2012-02-09
申请人： Yi-Ching Lin , Chun-Yao Chen , Chen-Jong Wang , Shou-Gwo Wuu , Chung S. Wang , Chien-Hua Huang , Kun-Lung Chen , Ping Yang
发明人： Yi-Ching Lin , Chun-Yao Chen , Chen-Jong Wang , Shou-Gwo Wuu , Chung S. Wang , Chien-Hua Huang , Kun-Lung Chen , Ping Yang
IPC分类号： H01L29/92 , H01L27/108
CPC分类号： H01L27/10897 , H01L27/0207 , H01L27/10852 , H01L27/10894
摘要： Embedded memories. The devices include a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of capacitors. The substrate comprises transistors. The first dielectric layer, embedding first and second conductive plugs electrically connecting the transistors therein, overlies the substrate. The second dielectric layer, comprising a plurality of capacitor openings exposing the first conductive plugs, overlies the first dielectric layer. The capacitors comprise a plurality of bottom plates, respectively disposed in the capacitor openings, electrically connecting the first conductive plugs, a plurality of capacitor dielectric layers respectively overlying the bottom plates, and a top plate, comprising a top plate opening, overlying the capacitor dielectric layers. The top plate opening exposes the second dielectric layer, and the top plate is shared by the capacitors.
摘要翻译：嵌入式记忆这些器件包括衬底，第一介电层，第二电介质层，第三电介质层和多个电容器。衬底包括晶体管。第一介电层，嵌入电连接其中的晶体管的第一和第二导电插塞覆盖在基板上。包括暴露第一导电插塞的多个电容器开口的第二电介质层覆盖在第一电介质层上。电容器包括分别设置在电容器开口中的多个底板，电连接第一导电插塞，分别覆盖在底板上的多个电容器电介质层，以及顶板，包括覆盖电容器电介质的顶板开口层。顶板开口暴露第二电介质层，并且顶板由电容器共享。

3. 发明授权

US08148223B2 1T MIM memory for embedded ram application in soc 有权
标题翻译： 1T MIM存储器，用于嵌入式RAM应用
公开(公告)号：US08148223B2
公开(公告)日：2012-04-03
申请号：US11437673
申请日：2006-05-22
申请人： Yi-Ching Lin , Chun-Yao Chen , Chen-Jong Wang , Shou-Gwo Wuu , Chung S. Wang , Chien-Hua Huang , Kun-Lung Chen , Ping Yang
发明人： Yi-Ching Lin , Chun-Yao Chen , Chen-Jong Wang , Shou-Gwo Wuu , Chung S. Wang , Chien-Hua Huang , Kun-Lung Chen , Ping Yang
IPC分类号： H01L21/8242
CPC分类号： H01L27/10897 , H01L27/0207 , H01L27/10852 , H01L27/10894
摘要： Embedded memories. The devices include a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of capacitors. The substrate comprises transistors. The first dielectric layer, embedding first and second conductive plugs electrically connecting the transistors therein, overlies the substrate. The second dielectric layer, comprising a plurality of capacitor openings exposing the first conductive plugs, overlies the first dielectric layer. The capacitors comprise a plurality of bottom plates, respectively disposed in the capacitor openings, electrically connecting the first conductive plugs, a plurality of capacitor dielectric layers respectively overlying the bottom plates, and a top plate, comprising a top plate opening, overlying the capacitor dielectric layers. The top plate opening exposes the second dielectric layer, and the top plate is shared by the capacitors.
摘要翻译：嵌入式记忆这些器件包括衬底，第一介电层，第二电介质层，第三电介质层和多个电容器。衬底包括晶体管。第一介电层，嵌入电连接其中的晶体管的第一和第二导电插塞覆盖在基板上。包括暴露第一导电插塞的多个电容器开口的第二电介质层覆盖在第一电介质层上。电容器包括分别设置在电容器开口中的多个底板，电连接第一导电插塞，分别覆盖在底板上的多个电容器电介质层，以及顶板，包括覆盖电容器电介质的顶板开口层。顶板开口暴露第二电介质层，并且顶板由电容器共享。

4. 发明申请

US20070267674A1 1T MIM memory for embedded ram application in soc 有权
标题翻译： 1T MIM存储器，用于嵌入式RAM应用
公开(公告)号：US20070267674A1
公开(公告)日：2007-11-22
申请号：US11437673
申请日：2006-05-22
申请人： Yi-Ching Lin , Chun-Yao Chen , Chen-Jong Wang , Shou-Gwo Wuu , Chung S. Wang , Chien-Hua Huang , Kun-Lung Chen , Ping Yang
发明人： Yi-Ching Lin , Chun-Yao Chen , Chen-Jong Wang , Shou-Gwo Wuu , Chung S. Wang , Chien-Hua Huang , Kun-Lung Chen , Ping Yang
IPC分类号： H01L29/94
CPC分类号： H01L27/10897 , H01L27/0207 , H01L27/10852 , H01L27/10894
摘要： Embedded memories. The devices include a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of capacitors. The substrate comprises transistors. The first dielectric layer, embedding first and second conductive plugs electrically connecting the transistors therein, overlies the substrate. The second dielectric layer, comprising a plurality of capacitor openings exposing the first conductive plugs, overlies the first dielectric layer. The capacitors comprise a plurality of bottom plates, respectively disposed in the capacitor openings, electrically connecting the first conductive plugs, a plurality of capacitor dielectric layers respectively overlying the bottom plates, and a top plate, comprising a top plate opening, overlying the capacitor dielectric layers. The top plate opening exposes the second dielectric layer, and the top plate is shared by the capacitors.
摘要翻译：嵌入式记忆这些器件包括衬底，第一介电层，第二电介质层，第三电介质层和多个电容器。衬底包括晶体管。第一介电层，嵌入电连接其中的晶体管的第一和第二导电插塞覆盖在基板上。包括暴露第一导电插塞的多个电容器开口的第二电介质层覆盖在第一电介质层上。电容器包括分别设置在电容器开口中的多个底板，电连接第一导电插塞，分别覆盖在底板上的多个电容器电介质层，以及顶板，包括覆盖电容器电介质的顶板开口层。顶板开口暴露第二电介质层，并且顶板由电容器共享。

5. 发明授权

US10002820B2 Through silicon via layout pattern 有权
公开(公告)号：US10002820B2
公开(公告)日：2018-06-19
申请号：US13478815
申请日：2012-05-23
申请人： Sun-Rong Jan , Che-Yu Yeh , Chee Wee Liu , Chien-Hua Huang , Bing J. Sheu
发明人： Sun-Rong Jan , Che-Yu Yeh , Chee Wee Liu , Chien-Hua Huang , Bing J. Sheu
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device comprises a substrate with a first side and a second side, wherein a plurality of active circuits are formed adjacent to the first side of the substrate and a plurality of through silicon vias arranged in a polygon shape and extending from the first side of to the second side, wherein the polygon shape has more than six sides, and wherein each through silicon via is placed at a corresponding apex of the polygon shape.

6. 发明申请

US20060232322A1 Voltage transfer circuit 有权
标题翻译：电压传输电路
公开(公告)号：US20060232322A1
公开(公告)日：2006-10-19
申请号：US11162667
申请日：2005-09-19
申请人： Chien-Hua Huang
发明人： Chien-Hua Huang
IPC分类号： H03K17/687 , H03H11/24 , H03K17/296
CPC分类号： H03K19/0013 , H03K19/018521
摘要： A voltage transfer circuit outputs an equivalent to an input voltage when enabled. Otherwise, the transfer circuit is in standby and outputs an equivalent to a standby voltage (e.g., signal ground). The voltage transfer circuit includes a switching circuit, a standby circuit, and an input-transfer circuit. The output of the transfer circuit is fed back to both the switching circuit and the input-transfer circuit. When the transfer circuit is in standby, the feedback of the output voltage provides for voltage-balancing in the input-transfer circuit, thereby reducing or eliminating leakage current in the input-transfer circuit. Similarly, when the transfer circuit is in active mode, the feedback of the output voltage provides for voltage-balancing in the standby circuit, thereby reducing or eliminating leakage current in the standby circuit.
摘要翻译：电压传输电路在使能时输出等效于输入电压。否则，传输电路处于待机状态，并输出等效于待机电压（例如，信号地）。电压传输电路包括开关电路，备用电路和输入传输电路。传输电路的输出反馈给开关电路和输入传输电路。当传送电路处于待机状态时，输出电压的反馈提供输入传输电路中的电压平衡，从而减少或消除输入传输电路中的漏电流。类似地，当传输电路处于主动模式时，输出电压的反馈提供备用电路中的电压平衡，从而减少或消除备用电路中的漏电流。

7. 发明申请

US20060152990A1 Multiple-time electrical fuse programming circuit 有权
公开(公告)号：US20060152990A1
公开(公告)日：2006-07-13
申请号：US11028839
申请日：2005-01-04
申请人： Chien-Hua Huang
发明人： Chien-Hua Huang
IPC分类号： G11C17/18
CPC分类号： G11C11/5692 , G11C17/165 , G11C17/18 , G11C29/02 , G11C29/027 , G11C29/4401
摘要： A multiple-time electrical fuse programming circuit is described. The circuit includes a programming counter to record the number of programmings, a blowing reference voltage generator to generate a blowing voltage reference wherein the fuse resistance after programming is determined by the blowing voltage reference, at least one self-controlled programmable fuses which includes a programmable fuse and a control circuit. The multiple-time electrical fuse programming circuit also has a fuse detection reference generator and a high voltage power source.

8. 发明申请

US20060150062A1 Method and system for correcting soft errors in memory circuit 失效
标题翻译：用于校正存储器电路中的软错误的方法和系统
公开(公告)号：US20060150062A1
公开(公告)日：2006-07-06
申请号：US11026354
申请日：2004-12-30
申请人： Chien-Hua Huang
发明人： Chien-Hua Huang
IPC分类号： G11C29/00
CPC分类号： G11C7/1006 , G01R31/31816 , G06F11/1008 , G11C29/42 , G11C29/52 , G11C2029/0409
摘要： A method and a system for correcting a soft error in a memory circuit during a stand-by mode are disclosed. According to the disclosure, after reading data from at least one memory cell without outputting the read data through an input/output module of the memory circuit in the stand-by mode, it is determined whether the read data is a soft error. If so, a correct value is written to the memory cell if the read data is the soft error.
摘要翻译：公开了一种用于在待机模式期间校正存储电路中的软错误的方法和系统。根据本公开，在从待机模式中经由存储电路的输入/输出模块输出读取数据之后，从至少一个存储单元读取数据之后，确定读取的数据是否为软错误。如果是这样，如果读取的数据是软错误，则将正确的值写入存储单元。

9. 发明申请

US20060145679A1 VOLTAGE REGULATOR HAVING POSITIVE TEMPERATURE COEFFICIENT FOR SELF-COMPENSATION AND RELATED METHOD OF REGULATING VOLTAGE 有权
标题翻译：具有用于自我补偿的正温度系数的电压调节器和相关调节电压的方法
公开(公告)号：US20060145679A1
公开(公告)日：2006-07-06
申请号：US10905386
申请日：2004-12-30
申请人： Chien-Hua Huang
发明人： Chien-Hua Huang
IPC分类号： G05F3/16 , G05F3/20
CPC分类号： G05F3/262 , Y10S323/907
摘要： Disclosed herein is a voltage regulator, and related method, for regulating a boost voltage generated by a boost circuit. In one embodiment, the voltage regulator includes a regulated voltage input operable to receive a regulated voltage derived from the boost voltage, a reference voltage input operable to receive a constant reference voltage, and an output node operable to provide a feedback signal to the boost circuit for controlling the generated boost voltage. In addition, the voltage regulator includes at least one transistor coupled to the regulated voltage input, the reference voltage input, and the output node, and operable to produce the feedback signal based on a comparison of the regulated voltage to the reference voltage. The voltage regulator still further includes a variable current source coupled to the output node and having one or more performance characteristics, where the variable current source is operable to generate a variable current at the output node to mitigate the affect of one or more performance characteristics of the at least one transistor based on the comparison and the feedback signal such that the boost circuit generates the boost voltage to be substantially constant.
摘要翻译：这里公开了一种用于调节由升压电路产生的升压电压的电压调节器和相关方法。在一个实施例中，电压调节器包括可操作以接收从升压电压导出的调节电压的调节电压输入，可操作以接收恒定参考电压的参考电压输入，以及用于向升压电路提供反馈信号的输出节点用于控制产生的升压电压。此外，电压调节器包括耦合到调节电压输入，参考电压输入和输出节点的至少一个晶体管，并且可操作以基于调节电压与参考电压的比较来产生反馈信号。电压调节器还包括耦合到输出节点并具有一个或多个性能特性的可变电流源，其中可变电流源可操作以在输出节点处产生可变电流，以减轻一个或多个性能特性的影响基于比较的至少一个晶体管和反馈信号，使得升压电路将升压电压基本上恒定。

10. 发明授权

US07035131B2 Dynamic random access memory cell leakage current detector 有权
标题翻译：动态随机存取存储单元泄漏电流检测器
公开(公告)号：US07035131B2
公开(公告)日：2006-04-25
申请号：US10840098
申请日：2004-05-06
申请人： Chien-Hua Huang , Chung-Cheng Chou
发明人： Chien-Hua Huang , Chung-Cheng Chou
IPC分类号： G11C11/24
CPC分类号： G11C29/50016 , G11C7/12 , G11C11/401 , G11C11/4094 , G11C29/50
摘要： A circuit operable to measure leakage current in a Dynamic Random Access Memory (DRAM) is provided comprising a plurality of DRAM bit cell access transistors coupled to a common bit line, a common word line, and a common storage node, wherein said access transistors may be biased to simulate a corresponding plurality of inactive bit cells of a DRAM; and a current mirror in communication with the common storage node operable to mirror a total leakage current from said plurality of bit cell access transistors when the access transistors are biased to simulate the inactive bit cells.
摘要翻译：提供了可操作以测量动态随机存取存储器（DRAM）中的泄漏电流的电路，其包括耦合到公共位线，公共字线和公共存储节点的多个DRAM位单元存取晶体管，其中所述存取晶体管可以被偏置以模拟DRAM的对应的多个非活动位单元; 以及与公共存储节点通信的电流镜，可操作以当存取晶体管被偏置以模拟非活动位单元时，来自所述多个位单元存取晶体管的总泄漏电流。

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