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1. 发明申请

US20070267674A1 1T MIM memory for embedded ram application in soc 有权
标题翻译： 1T MIM存储器，用于嵌入式RAM应用
公开(公告)号：US20070267674A1
公开(公告)日：2007-11-22
申请号：US11437673
申请日：2006-05-22
申请人： Yi-Ching Lin , Chun-Yao Chen , Chen-Jong Wang , Shou-Gwo Wuu , Chung S. Wang , Chien-Hua Huang , Kun-Lung Chen , Ping Yang
发明人： Yi-Ching Lin , Chun-Yao Chen , Chen-Jong Wang , Shou-Gwo Wuu , Chung S. Wang , Chien-Hua Huang , Kun-Lung Chen , Ping Yang
IPC分类号： H01L29/94
CPC分类号： H01L27/10897 , H01L27/0207 , H01L27/10852 , H01L27/10894
摘要： Embedded memories. The devices include a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of capacitors. The substrate comprises transistors. The first dielectric layer, embedding first and second conductive plugs electrically connecting the transistors therein, overlies the substrate. The second dielectric layer, comprising a plurality of capacitor openings exposing the first conductive plugs, overlies the first dielectric layer. The capacitors comprise a plurality of bottom plates, respectively disposed in the capacitor openings, electrically connecting the first conductive plugs, a plurality of capacitor dielectric layers respectively overlying the bottom plates, and a top plate, comprising a top plate opening, overlying the capacitor dielectric layers. The top plate opening exposes the second dielectric layer, and the top plate is shared by the capacitors.
摘要翻译：嵌入式记忆这些器件包括衬底，第一介电层，第二电介质层，第三电介质层和多个电容器。衬底包括晶体管。第一介电层，嵌入电连接其中的晶体管的第一和第二导电插塞覆盖在基板上。包括暴露第一导电插塞的多个电容器开口的第二电介质层覆盖在第一电介质层上。电容器包括分别设置在电容器开口中的多个底板，电连接第一导电插塞，分别覆盖在底板上的多个电容器电介质层，以及顶板，包括覆盖电容器电介质的顶板开口层。顶板开口暴露第二电介质层，并且顶板由电容器共享。

2. 发明授权

US08148223B2 1T MIM memory for embedded ram application in soc 有权
标题翻译： 1T MIM存储器，用于嵌入式RAM应用
公开(公告)号：US08148223B2
公开(公告)日：2012-04-03
申请号：US11437673
申请日：2006-05-22
申请人： Yi-Ching Lin , Chun-Yao Chen , Chen-Jong Wang , Shou-Gwo Wuu , Chung S. Wang , Chien-Hua Huang , Kun-Lung Chen , Ping Yang
发明人： Yi-Ching Lin , Chun-Yao Chen , Chen-Jong Wang , Shou-Gwo Wuu , Chung S. Wang , Chien-Hua Huang , Kun-Lung Chen , Ping Yang
IPC分类号： H01L21/8242
CPC分类号： H01L27/10897 , H01L27/0207 , H01L27/10852 , H01L27/10894
摘要： Embedded memories. The devices include a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of capacitors. The substrate comprises transistors. The first dielectric layer, embedding first and second conductive plugs electrically connecting the transistors therein, overlies the substrate. The second dielectric layer, comprising a plurality of capacitor openings exposing the first conductive plugs, overlies the first dielectric layer. The capacitors comprise a plurality of bottom plates, respectively disposed in the capacitor openings, electrically connecting the first conductive plugs, a plurality of capacitor dielectric layers respectively overlying the bottom plates, and a top plate, comprising a top plate opening, overlying the capacitor dielectric layers. The top plate opening exposes the second dielectric layer, and the top plate is shared by the capacitors.
摘要翻译：嵌入式记忆这些器件包括衬底，第一介电层，第二电介质层，第三电介质层和多个电容器。衬底包括晶体管。第一介电层，嵌入电连接其中的晶体管的第一和第二导电插塞覆盖在基板上。包括暴露第一导电插塞的多个电容器开口的第二电介质层覆盖在第一电介质层上。电容器包括分别设置在电容器开口中的多个底板，电连接第一导电插塞，分别覆盖在底板上的多个电容器电介质层，以及顶板，包括覆盖电容器电介质的顶板开口层。顶板开口暴露第二电介质层，并且顶板由电容器共享。

3. 发明授权

US09012967B2 1T MIM memory for embedded RAM application in soc 有权
标题翻译： 1T MIM存储器，用于soc中的嵌入式RAM应用
公开(公告)号：US09012967B2
公开(公告)日：2015-04-21
申请号：US13369894
申请日：2012-02-09
申请人： Yi-Ching Lin , Chun-Yao Chen , Chen-Jong Wang , Shou-Gwo Wuu , Chung S. Wang , Chien-Hua Huang , Kun-Lung Chen , Ping Yang
发明人： Yi-Ching Lin , Chun-Yao Chen , Chen-Jong Wang , Shou-Gwo Wuu , Chung S. Wang , Chien-Hua Huang , Kun-Lung Chen , Ping Yang
IPC分类号： H01L27/108 , H01L29/94 , H01L27/02
CPC分类号： H01L27/10897 , H01L27/0207 , H01L27/10852 , H01L27/10894
摘要： Embedded memories. The devices include a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of capacitors. The substrate comprises transistors. The first dielectric layer, embedding first and second conductive plugs electrically connecting the transistors therein, overlies the substrate. The second dielectric layer, comprising a plurality of capacitor openings exposing the first conductive plugs, overlies the first dielectric layer. The capacitors comprise a plurality of bottom plates, respectively disposed in the capacitor openings, electrically connecting the first conductive plugs, a plurality of capacitor dielectric layers respectively overlying the bottom plates, and a top plate, comprising a top plate opening, overlying the capacitor dielectric layers. The top plate opening exposes the second dielectric layer, and the top plate is shared by the capacitors.
摘要翻译：嵌入式记忆这些器件包括衬底，第一介电层，第二电介质层，第三电介质层和多个电容器。衬底包括晶体管。第一介电层，嵌入电连接其中的晶体管的第一和第二导电插塞覆盖在基板上。包括暴露第一导电插塞的多个电容器开口的第二电介质层覆盖在第一电介质层上。电容器包括分别设置在电容器开口中的多个底板，电连接第一导电插塞，分别覆盖在底板上的多个电容器电介质层，以及顶板，包括覆盖电容器电介质的顶板开口层。顶板开口暴露第二电介质层，并且顶板由电容器共享。

4. 发明申请

US20120139022A1 1T MIM MEMORY FOR EMBEDDED RAM APPLICATION IN SOC 审中-公开
标题翻译： 1T MIM存储器嵌入式RAM应用于SOC
公开(公告)号：US20120139022A1
公开(公告)日：2012-06-07
申请号：US13369894
申请日：2012-02-09
申请人： Yi-Ching Lin , Chun-Yao Chen , Chen-Jong Wang , Shou-Gwo Wuu , Chung S. Wang , Chien-Hua Huang , Kun-Lung Chen , Ping Yang
发明人： Yi-Ching Lin , Chun-Yao Chen , Chen-Jong Wang , Shou-Gwo Wuu , Chung S. Wang , Chien-Hua Huang , Kun-Lung Chen , Ping Yang
IPC分类号： H01L29/92 , H01L27/108
CPC分类号： H01L27/10897 , H01L27/0207 , H01L27/10852 , H01L27/10894
摘要： Embedded memories. The devices include a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of capacitors. The substrate comprises transistors. The first dielectric layer, embedding first and second conductive plugs electrically connecting the transistors therein, overlies the substrate. The second dielectric layer, comprising a plurality of capacitor openings exposing the first conductive plugs, overlies the first dielectric layer. The capacitors comprise a plurality of bottom plates, respectively disposed in the capacitor openings, electrically connecting the first conductive plugs, a plurality of capacitor dielectric layers respectively overlying the bottom plates, and a top plate, comprising a top plate opening, overlying the capacitor dielectric layers. The top plate opening exposes the second dielectric layer, and the top plate is shared by the capacitors.
摘要翻译：嵌入式记忆这些器件包括衬底，第一介电层，第二电介质层，第三电介质层和多个电容器。衬底包括晶体管。第一介电层，嵌入电连接其中的晶体管的第一和第二导电插塞覆盖在基板上。包括暴露第一导电插塞的多个电容器开口的第二电介质层覆盖在第一电介质层上。电容器包括分别设置在电容器开口中的多个底板，电连接第一导电插塞，分别覆盖在底板上的多个电容器电介质层，以及顶板，包括覆盖电容器电介质的顶板开口层。顶板开口暴露第二电介质层，并且顶板由电容器共享。

5. 发明授权

US07382012B2 Reducing parasitic capacitance of MIM capacitor in integrated circuits by reducing effective dielectric constant of dielectric layer 有权
标题翻译：通过降低介电层的有效介电常数，降低集成电路中MIM电容的寄生电容
公开(公告)号：US07382012B2
公开(公告)日：2008-06-03
申请号：US11361330
申请日：2006-02-24
申请人： Kuo-Chi Tu , Chun-Yao Chen , Yi-Ching Lin
发明人： Kuo-Chi Tu , Chun-Yao Chen , Yi-Ching Lin
IPC分类号： H01L27/108 , H01L21/20 , G11C11/00
CPC分类号： H01L28/40 , H01L27/10852 , H01L27/10894 , H01L28/56
摘要： A memory device having improved sensing speed and reliability and a method of forming the same are provided. The memory device includes a first dielectric layer having a low k value over a semiconductor substrate, a second dielectric layer having a second k value over the first dielectric layer, and a capacitor formed in the second dielectric layer wherein the capacitor comprises a cup region at least partially filled by the third dielectric layer. The memory device further includes a third dielectric layer over the second dielectric layer and a bitline over the third dielectric layer. The bitline is electrically coupled to the capacitor. A void having great dimensions is preferably formed in the cup region of the capacitor.
摘要翻译：提供了具有改进的感测速度和可靠性的记忆装置及其形成方法。存储器件包括在半导体衬底上具有低k值的第一电介质层，在第一介电层上具有第二k值的第二电介质层和形成在第二电介质层中的电容器，其中电容器包括位于最少部分地被第三介电层填充。存储器件还包括第二电介质层上的第三电介质层和第三电介质层上的位线。位线电耦合到电容器。优选地，在电容器的杯区域中形成具有大尺寸的空隙。

6. 发明申请

US20070200162A1 Reducing dielectric constant for MIM capacitor 有权
标题翻译：降低MIM电容的介电常数
公开(公告)号：US20070200162A1
公开(公告)日：2007-08-30
申请号：US11361330
申请日：2006-02-24
申请人： Kuo-Chi Tu , Chun-Yao Chen , Yi-Ching Lin
发明人： Kuo-Chi Tu , Chun-Yao Chen , Yi-Ching Lin
IPC分类号： H01L29/76
CPC分类号： H01L28/40 , H01L27/10852 , H01L27/10894 , H01L28/56
摘要： A memory device having improved sensing speed and reliability and a method of forming the same are provided. The memory device includes a first dielectric layer having a low k value over a semiconductor substrate, a second dielectric layer having a second k value over the first dielectric layer, and a capacitor formed in the second dielectric layer wherein the capacitor comprises a cup region at least partially filled by the third dielectric layer. The memory device further includes a third dielectric layer over the second dielectric layer and a bitline over the third dielectric layer. The bitline is electrically coupled to the capacitor. A void having great dimensions is preferably formed in the cup region of the capacitor.
摘要翻译：提供了具有改进的感测速度和可靠性的记忆装置及其形成方法。存储器件包括在半导体衬底上具有低k值的第一电介质层，在第一介电层上具有第二k值的第二电介质层和形成在第二电介质层中的电容器，其中电容器包括位于最少部分地被第三介电层填充。存储器件还包括第二电介质层上的第三电介质层和第三电介质层上的位线。位线电耦合到电容器。优选地，在电容器的杯区域中形成具有大尺寸的空隙。

7. 发明授权

US07484972B1 Rotatable plug structure with a finger hole 失效
标题翻译：可旋转插头结构，带指孔
公开(公告)号：US07484972B1
公开(公告)日：2009-02-03
申请号：US11979399
申请日：2007-11-02
申请人： Ming-Chou Kuo , Yi-Ching Lin
发明人： Ming-Chou Kuo , Yi-Ching Lin
IPC分类号： H01R13/44
CPC分类号： H01R35/04 , H01R13/44 , H01R13/60
摘要： A rotatable plug includes a plug body, a rotatable base and at least two conductive terminals. One end of the plug body has an accommodating space. The plug body is provided with a penetrating hole to make the plug body to form a hollow annular body. The rotatable base is rotatably provided in the accommodating space of the plug body. The two conductive terminals are provided on the rotatable base. The two conductive terminals rotate together with the rotatable base to the outside of the plug body or are accommodated in the plug body. Via this arrangement, the conductive terminals can be avoided from getting inclined or suffering damage by the impact or compression during transportation. Further, it is convenient for the user to put his/her finger in the hollow annular body to pull out the plug.
摘要翻译：可旋转插头包括插头主体，可旋转底座和至少两个导电端子。插头体的一端具有容纳空间。塞体设置有穿孔，以使塞体形成中空的环形体。可旋转底座可旋转地设置在塞体的容纳空间中。两个导电端子设置在可旋转底座上。两个导电端子与可旋转基座一起旋转到插塞体的外部，或者容纳在插头体中。通过这种布置，可以避免导电端子在运输过程中受冲击或压缩而变得倾斜或遭受损坏。此外，用户方便地将他/她的手指放在中空的环形体中以拉出插头。

8. 发明申请

US20080124875A1 Method for forming a strained channel in a semiconductor device 有权
标题翻译：在半导体器件中形成应变通道的方法
公开(公告)号：US20080124875A1
公开(公告)日：2008-05-29
申请号：US11592204
申请日：2006-11-03
申请人： Ken Liao , Kuo-Hua Pan , Yun-Hsiu Chen , Syun-Ming Jang , Yi-Ching Lin
发明人： Ken Liao , Kuo-Hua Pan , Yun-Hsiu Chen , Syun-Ming Jang , Yi-Ching Lin
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L21/266 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/665 , H01L29/6659 , H01L29/66636
摘要： A method for forming a strained channel in a semiconductor device is provided, comprises providing of a transistor comprising a gate stack exposed with a gate electrode on a semiconductor substrate, a pair of source/drain regions in the substrate on opposite sides of the gate stack and a pair of spacers on opposing sidewalls of the gate stack. A passivation layer is formed to cover the gate electrode and spacers of the transistor. A passivation layer is formed to cover the gate electrode and the spacers. A recess region is formed in each of the source/drain regions, wherein an edge of the recess region aligns to an outer edge of the spacers. The recess regions are filled with a strain-exerting material, thereby forming a strained channel region in the semiconductor substrate between the source/drain regions.
摘要翻译：提供了一种在半导体器件中形成应变通道的方法，包括提供晶体管，其包括在半导体衬底上暴露有栅极电极的栅极堆叠，在栅极堆叠的相对侧的衬底中的一对源极/漏极区域以及在栅极堆叠的相对的侧壁上的一对隔板。形成钝化层以覆盖晶体管的栅电极和间隔物。形成钝化层以覆盖栅电极和间隔物。在每个源极/漏极区域中形成凹陷区域，其中凹部区域的边缘与间隔物的外边缘对准。用应变施加材料填充凹陷区域，从而在源极/漏极区域之间的半导体衬底中形成应变通道区域。

9. 发明授权

US5175126A Process of making titanium nitride barrier layer 失效
标题翻译：制造氮化钛阻挡层的工艺
公开(公告)号：US5175126A
公开(公告)日：1992-12-29
申请号：US635686
申请日：1990-12-27
申请人： Huei-Min Ho , Yi-Ching Lin
发明人： Huei-Min Ho , Yi-Ching Lin
IPC分类号： H01L21/768
CPC分类号： H01L21/76831 , H01L21/76843 , H01L21/76856
摘要： Two methods for substantially improving the integrity of a TiN barrier layer are disclosed. The first method allows an atmospheric anneal in a conventional semiconductor furnace. The atmospheric anneal substantially seals the exposed TiN surface preventing subsequent metal layers from migrating through the barrier layer. The second method involves a reaction within a plasma reactor using a plasma gas. The plasma gas reacts with titanium within the TiN film to form a desired titanium compound. The gas is adsorbed onto the TiN grains at the grain boundaries within the TiN film thus filling the grain boundaries and thus substantially preventing subsequent metal layers from migrating though the TiN barrier layer. The second method allows the deposition of TiN, the plasma reaction, and subsequent metal depositions to take place on the same equipment using the same evacuation cycle.
摘要翻译：公开了用于显着改善TiN阻挡层完整性的两种方法。第一种方法允许常规半导体炉中的大气退火。大气退火基本上密封暴露的TiN表面，防止随后的金属层迁移通过阻挡层。第二种方法涉及使用等离子体气体的等离子体反应器内的反应。等离子体气体与TiN膜内的钛反应形成所需的钛化合物。气体被吸附到TiN膜内的晶界处的TiN晶粒上，从而填充晶界，从而基本上防止随后的金属层通过TiN势垒层迁移。第二种方法允许沉积TiN，等离子体反应和随后的金属沉积在相同的设备上使用相同的抽空循环进行。

10. 发明授权

US07754571B2 Method for forming a strained channel in a semiconductor device 有权
标题翻译：在半导体器件中形成应变通道的方法
公开(公告)号：US07754571B2
公开(公告)日：2010-07-13
申请号：US11592204
申请日：2006-11-03
申请人： Ken Liao , Kuo-Hua Pan , Yun-Hsiu Chen , Syun-Ming Jang , Yi-Ching Lin
发明人： Ken Liao , Kuo-Hua Pan , Yun-Hsiu Chen , Syun-Ming Jang , Yi-Ching Lin
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L21/266 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/665 , H01L29/6659 , H01L29/66636
摘要： A method for forming a strained channel in a semiconductor device is provided, comprises providing of a transistor comprising a gate stack exposed with a gate electrode on a semiconductor substrate, a pair of source/drain regions in the substrate on opposite sides of the gate stack and a pair of spacers on opposing sidewalls of the gate stack. A passivation layer is formed to cover the gate electrode and spacers of the transistor. A passivation layer is formed to cover the gate electrode and the spacers. A recess region is formed in each of the source/drain regions, wherein an edge of the recess region aligns to an outer edge of the spacers. The recess regions are filled with a strain-exerting material, thereby forming a strained channel region in the semiconductor substrate between the source/drain regions.
摘要翻译：提供了一种在半导体器件中形成应变通道的方法，包括提供晶体管，该晶体管包括在半导体衬底上暴露有栅电极的栅极叠层，在栅极叠层的相对侧上的衬底中的一对源极/漏极区域以及在栅极堆叠的相对的侧壁上的一对隔板。形成钝化层以覆盖晶体管的栅电极和间隔物。形成钝化层以覆盖栅电极和间隔物。在每个源极/漏极区域中形成凹陷区域，其中凹部区域的边缘与间隔物的外边缘对准。用应变施加材料填充凹陷区域，从而在源极/漏极区域之间的半导体衬底中形成应变通道区域。

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