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1. 发明授权

US08261219B2 System on chip development with reconfigurable multi-project wafer technology 有权
标题翻译：系统片上开发与可重构多项目晶圆技术
公开(公告)号：US08261219B2
公开(公告)日：2012-09-04
申请号：US12133323
申请日：2008-06-04
申请人： Kun-Lung Chen , Shine Chien Chung , Yung-Chin Hou , Yu-Chun Wu
发明人： Kun-Lung Chen , Shine Chien Chung , Yung-Chin Hou , Yu-Chun Wu
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method is disclosed for designing a semiconductor circuit on a multi-project wafer (MPW). One or more standard modules designed by one or more vendors with verified functions are first identified. Some of the standard modules are charged based on usage. At least one reconfigurable module of the MPW is programmed by making one or more connections through one or more connection layers. The standard modules are further connected with the programmed reconfigurable module according to the predetermined design of the circuit. The completed circuit is then verified for final uses.
摘要翻译：公开了一种在多工程晶片（MPW）上设计半导体电路的方法。首先确定由具有验证功能的一个或多个供应商设计的一个或多个标准模块。一些标准模块根据用途收费。通过使一个或多个连接通过一个或多个连接层来编程MPW的至少一个可重新配置的模块。根据电路的预定设计，标准模块还与编程的可重配置模块进一步连接。完成的电路然后被验证用于最终用途。

2. 发明授权

US07577052B2 Power switching circuit 有权
标题翻译：电源开关电路
公开(公告)号：US07577052B2
公开(公告)日：2009-08-18
申请号：US11638187
申请日：2006-12-13
申请人： Jui-Jen Wu , Kun-Lung Chen , Hung-Jen Liao , Yung-Lung Lin , Chen Yen-Huei , Dao-Ping Wang
发明人： Jui-Jen Wu , Kun-Lung Chen , Hung-Jen Liao , Yung-Lung Lin , Chen Yen-Huei , Dao-Ping Wang
IPC分类号： G11C5/10
CPC分类号： G11C11/412 , G11C11/413
摘要： A power control circuit for an integrated circuit module includes at least one switch device coupled between a supply voltage and a power node of the integrated circuit module; and a switch control module having a first terminal coupled to the switch device, a second terminal coupled to a control signal, a third terminal coupled to a first storage node of at least one tracking cell, a fourth terminal coupled to a second storage node of the tracking cell, and a fifth terminal coupled to the power node of the integrated circuit module, for controlling the switch device to pass the supply voltage to the power node with or without a substantial voltage drop depending on an operation mode of the integrated circuit module.
摘要翻译：用于集成电路模块的功率控制电路包括耦合在电源电压和集成电路模块的功率节点之间的至少一个开关装置; 以及开关控制模块，其具有耦合到所述开关装置的第一端子，耦合到控制信号的第二端子，耦合到至少一个跟踪单元的第一存储节点的第三端子，耦合到所述至少一个跟踪单元的第二存储节点的第四端子跟踪单元和耦合到集成电路模块的功率节点的第五端子，用于根据集成电路模块的操作模式控制开关装置将电源电压传递到功率节点，具有或不具有实质的电压降。

3. 发明授权

US07564709B2 Method and system for utilizing DRAM components in a system-on-chip 有权
标题翻译：在片上系统中利用DRAM组件的方法和系统
公开(公告)号：US07564709B2
公开(公告)日：2009-07-21
申请号：US11638596
申请日：2006-12-13
申请人： Kun Lung Chen , Shine Chung
发明人： Kun Lung Chen , Shine Chung
IPC分类号： G11C11/24 , G11C11/34 , H01L29/94
CPC分类号： H01L27/10894 , H01L23/5223 , H01L27/0207 , H01L2924/0002 , H01L2924/00
摘要： A system-on-chip semiconductor circuit includes a logic circuit having at least one first transistor with a thin gate dielectric, at least one dynamic random access memory cell coupled with the logic circuit having at least one storage capacitor and at least one thick gate dielectric access transistor, and an analog circuit operable with the logic circuit and the memory cell having at least one thick gate dielectric switched transistor and at least one switched capacitor, wherein the storage capacitors of the memory cell and the switched transistors are of the same type, and wherein the thick gate dielectric switched transistor and the switched capacitor of the analog circuit are made by a process for making the dynamic random access memory cell.
摘要翻译：片上系统半导体电路包括具有至少一个第一晶体管与薄栅介质的逻辑电路，至少一个与逻辑电路耦合的动态随机存取存储单元，其具有至少一个存储电容器和至少一个厚栅极电介质存取晶体管，以及可与具有至少一个厚栅极介质开关晶体管和至少一个开关电容器的逻辑电路和存储单元可操作的模拟电路，其中存储单元和开关晶体管的存储电容器具有相同类型，并且其中所述厚栅介质切换晶体管和所述模拟电路的开关电容器是通过用于制造所述动态随机存取存储单元的过程制成的。

4. 发明授权

US07484138B2 Method and system for improving reliability of memory device 有权
标题翻译：提高存储器件可靠性的方法和系统
公开(公告)号：US07484138B2
公开(公告)日：2009-01-27
申请号：US11450535
申请日：2006-06-09
申请人： Chen-Hui Hsieh , Kun Lung Chen , Shine Chien Chung , Grigori Grigoriev
发明人： Chen-Hui Hsieh , Kun Lung Chen , Shine Chien Chung , Grigori Grigoriev
IPC分类号： G11C29/00 , G01R31/28
CPC分类号： G11C29/24 , G11C29/26 , G11C29/4401 , G11C29/802
摘要： A system for improving reliability of a memory device includes one or more memory banks, each of which has one or more regular memory cell rows and one or more redundant memory cell rows. At least one built-in-self-test (BIST) unit is coupled to the memory banks for testing the redundant memory cell rows to determine their respective quality standards, and testing the regular memory cell rows to identify the regular memory cell row that fails to pass a predetermined quality standard. At least one built-in-self-repair (BISR) unit is coupled to the BIST unit for replacing the failed regular memory cell row with the redundant memory cell row having a quality standard equal to or higher than the predetermined quality standard. The BIST unit repeatedly tests the regular memory cell rows a number of times, with each time applying a different quality standard.
摘要翻译：一种用于提高存储器件的可靠性的系统包括一个或多个存储体，每个存储体具有一个或多个常规存储单元行和一个或多个冗余存储单元行。至少一个内置自检（BIST）单元耦合到存储体，用于测试冗余存储单元行以确定其相应的质量标准，并测试常规存储单元行以识别出错的常规存储单元行通过一个预定的质量标准。至少一个内置自修复（BISR）单元耦合到BIST单元，以用具有等于或高于预定质量标准的质量标准的冗余存储单元行替换故障的常规存储单元行。 BIST单元反复测试常规存储单元行多次，每次应用不同的质量标准。

5. 发明申请

US20080158939A1 MEMORY HAVING IMPROVED POWER DESIGN 有权
标题翻译：具有改进功率设计的记忆
公开(公告)号：US20080158939A1
公开(公告)日：2008-07-03
申请号：US11619103
申请日：2007-01-02
申请人： Yen-Huei Chen , Hung-Jen Liao , Kun-Lung Chen , Jui-Jen Wu , Yung-Lung Lin , Dao-Ping Wang
发明人： Yen-Huei Chen , Hung-Jen Liao , Kun-Lung Chen , Jui-Jen Wu , Yung-Lung Lin , Dao-Ping Wang
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , G11C11/413
摘要： A memory includes a plurality of cells arranged in a matrix having a plurality of rows and a plurality of columns, wherein each cell is capable of storing a bit. Each cell is coupled between a first power supply node that receives a power supply voltage and a second power supply node that receives a second voltage. A plurality of word lines are associated with the memory cells and supplied by a third voltage in read or write operation. The third voltage is a suppressed power supply voltage. The second voltage is negative in read operation and positive in write operation.
摘要翻译：存储器包括以具有多个行和多个列的矩阵的形式排列的多个单元，其中每个单元能够存储位。每个单元耦合在接收电源电压的第一电源节点和接收第二电压的第二电源节点之间。多个字线与存储器单元相关联并且在读或写操作中由第三电压提供。第三电压是抑制电源电压。读操作中的第二电压为负，写操作为正。

6. 发明申请

US20080142860A1 Method and system for utilizing DRAM components in a system-on-chip 有权
标题翻译：在片上系统中利用DRAM组件的方法和系统
公开(公告)号：US20080142860A1
公开(公告)日：2008-06-19
申请号：US11638596
申请日：2006-12-13
申请人： Kun Lung Chen , Shine Chung
发明人： Kun Lung Chen , Shine Chung
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10894 , H01L23/5223 , H01L27/0207 , H01L2924/0002 , H01L2924/00
摘要： A system-on-chip semiconductor circuit includes a logic circuit having at least one first transistor with a thin gate dielectric, at least one dynamic random access memory cell coupled with the logic circuit having at least one storage capacitor and at least one thick gate dielectric access transistor, and an analog circuit operable with the logic circuit and the memory cell having at least one thick gate dielectric switched transistor and at least one switched capacitor, wherein the storage capacitors of the memory cell and the switched transistors are of the same type, and wherein the thick gate dielectric switched transistor and the switched capacitor of the analog circuit are made by a process for making the dynamic random access memory cell.
摘要翻译：片上系统半导体电路包括具有至少一个第一晶体管与薄栅介质的逻辑电路，至少一个与逻辑电路耦合的动态随机存取存储单元，其具有至少一个存储电容器和至少一个厚栅极电介质存取晶体管，以及可与具有至少一个厚栅极介质开关晶体管和至少一个开关电容器的逻辑电路和存储单元可操作的模拟电路，其中存储单元和开关晶体管的存储电容器具有相同类型，并且其中所述厚栅介质切换晶体管和所述模拟电路的开关电容器是通过用于制造所述动态随机存取存储单元的过程制成的。

7. 发明申请

US20050257177A1 System on chip development with reconfigurable multi-project wafer technology 有权
标题翻译：系统片上开发与可重构多项目晶圆技术
公开(公告)号：US20050257177A1
公开(公告)日：2005-11-17
申请号：US11119086
申请日：2005-04-29
申请人： Kun-Lung Chen , Shine Chung , Yung-Chin Hou , Yu-Chun Wu
发明人： Kun-Lung Chen , Shine Chung , Yung-Chin Hou , Yu-Chun Wu
IPC分类号： G06F7/00 , G06F17/50 , H03K19/177
CPC分类号： G06F17/5045
摘要： A method is disclosed for designing a semiconductor circuit on a multi-project wafer (MPW). One or more standard modules designed by one or more vendors with verified functions are first identified. Some of the standard modules are charged based on usage. At least one reconfigurable module of the MPW is programmed by making one or more connections through one or more connection layers. The standard modules are further connected with the programmed reconfigurable module according to the predetermined design of the circuit. The completed circuit is then verified for final uses.
摘要翻译：公开了一种在多工程晶片（MPW）上设计半导体电路的方法。首先确定由具有验证功能的一个或多个供应商设计的一个或多个标准模块。一些标准模块根据用途收费。通过使一个或多个连接通过一个或多个连接层来编程MPW的至少一个可重新配置的模块。根据电路的预定设计，标准模块还与编程的可重配置模块进一步连接。完成的电路然后被验证用于最终用途。

8. 发明授权

US09012967B2 1T MIM memory for embedded RAM application in soc 有权
标题翻译： 1T MIM存储器，用于soc中的嵌入式RAM应用
公开(公告)号：US09012967B2
公开(公告)日：2015-04-21
申请号：US13369894
申请日：2012-02-09
申请人： Yi-Ching Lin , Chun-Yao Chen , Chen-Jong Wang , Shou-Gwo Wuu , Chung S. Wang , Chien-Hua Huang , Kun-Lung Chen , Ping Yang
发明人： Yi-Ching Lin , Chun-Yao Chen , Chen-Jong Wang , Shou-Gwo Wuu , Chung S. Wang , Chien-Hua Huang , Kun-Lung Chen , Ping Yang
IPC分类号： H01L27/108 , H01L29/94 , H01L27/02
CPC分类号： H01L27/10897 , H01L27/0207 , H01L27/10852 , H01L27/10894
摘要： Embedded memories. The devices include a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of capacitors. The substrate comprises transistors. The first dielectric layer, embedding first and second conductive plugs electrically connecting the transistors therein, overlies the substrate. The second dielectric layer, comprising a plurality of capacitor openings exposing the first conductive plugs, overlies the first dielectric layer. The capacitors comprise a plurality of bottom plates, respectively disposed in the capacitor openings, electrically connecting the first conductive plugs, a plurality of capacitor dielectric layers respectively overlying the bottom plates, and a top plate, comprising a top plate opening, overlying the capacitor dielectric layers. The top plate opening exposes the second dielectric layer, and the top plate is shared by the capacitors.
摘要翻译：嵌入式记忆这些器件包括衬底，第一介电层，第二电介质层，第三电介质层和多个电容器。衬底包括晶体管。第一介电层，嵌入电连接其中的晶体管的第一和第二导电插塞覆盖在基板上。包括暴露第一导电插塞的多个电容器开口的第二电介质层覆盖在第一电介质层上。电容器包括分别设置在电容器开口中的多个底板，电连接第一导电插塞，分别覆盖在底板上的多个电容器电介质层，以及顶板，包括覆盖电容器电介质的顶板开口层。顶板开口暴露第二电介质层，并且顶板由电容器共享。

9. 发明授权

US08587077B2 Integrated compact MEMS device with deep trench contacts 失效
标题翻译：具有深沟槽触点的集成紧凑型MEMS器件
公开(公告)号：US08587077B2
公开(公告)日：2013-11-19
申请号：US13342129
申请日：2012-01-02
申请人： Kun-Lung Chen
发明人： Kun-Lung Chen
IPC分类号： H01L29/84
CPC分类号： B81C1/00238 , B81B2201/0235 , B81B2207/012 , B81C2203/0792 , G01C19/5783 , G01P1/02 , H01L24/05 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/92 , H01L24/94 , H01L2224/0401 , H01L2224/04042 , H01L2224/05568 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/05655 , H01L2224/131 , H01L2224/13111 , H01L2224/29011 , H01L2224/29124 , H01L2224/32145 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/73253 , H01L2224/73265 , H01L2224/83005 , H01L2224/92225 , H01L2224/94 , H01L2924/00014 , H01L2924/01322 , H01L2924/10253 , H01L2924/1461 , H01L2924/16235 , H01L2924/3025 , H01L2224/45099 , H01L2924/00 , H01L2924/014 , H01L2224/83 , H01L2224/03 , H01L2224/11 , H01L2924/01014 , H01L2224/05552 , H01L2924/00012
摘要： A compact MEMS motion sensor device is provided, including a CMOS substrate layer, with plural anchor posts having an isolation oxide layer surrounding a conductive layer. On one side of the CMOS substrate layer, the device further includes a field oxide (FOX) layer, a first set and a second set of implant doped silicon areas, a first polysilicon layer, an oxide layer embedded with plural metal layers interleaved with via hole layers, a Nitride deposition layer, an under bump metal (UBM) layer and a plurality of solder spheres. On the other side of the CMOS substrate layer, it further includes a backside interconnect isolation oxide layer, a first MEMS bonding layer, a first metal compound layer, a second MEMS bonding layer, a MEMS layer, a first MEMS eutectic bonding layer, a second metal compound layer, a second MEMS eutectic bonding layer, and a MEMS cap layer.
摘要翻译：提供了一种紧凑的MEMS运动传感器装置，其包括CMOS衬底层，多个锚柱具有围绕导电层的隔离氧化层。在CMOS衬底层的一侧，该器件还包括场氧化物（FOX）层，第一组和第二组注入掺杂硅区，第一多晶硅层，嵌入多个金属层的氧化物层，其与通孔交错空穴层，氮化物沉积层，下凸块金属（UBM）层和多个焊料球。在CMOS衬底层的另一侧，还包括背面互连隔离氧化物层，第一MEMS结合层，第一金属化合物层，第二MEMS结合层，MEMS层，第一MEMS共晶接合层，第二金属化合物层，第二MEMS共晶接合层和MEMS覆盖层。

10. 发明申请

US20130168740A1 INTEGRATED COMPACT MEMS DEVICE WITH DEEP TRENCH CONTACTS 失效
标题翻译：具有深度触感的集成紧凑型MEMS器件
公开(公告)号：US20130168740A1
公开(公告)日：2013-07-04
申请号：US13342129
申请日：2012-01-02
申请人： Kun-Lung Chen
发明人： Kun-Lung Chen
IPC分类号： H01L29/84
CPC分类号： B81C1/00238 , B81B2201/0235 , B81B2207/012 , B81C2203/0792 , G01C19/5783 , G01P1/02 , H01L24/05 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/92 , H01L24/94 , H01L2224/0401 , H01L2224/04042 , H01L2224/05568 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/05655 , H01L2224/131 , H01L2224/13111 , H01L2224/29011 , H01L2224/29124 , H01L2224/32145 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/73253 , H01L2224/73265 , H01L2224/83005 , H01L2224/92225 , H01L2224/94 , H01L2924/00014 , H01L2924/01322 , H01L2924/10253 , H01L2924/1461 , H01L2924/16235 , H01L2924/3025 , H01L2224/45099 , H01L2924/00 , H01L2924/014 , H01L2224/83 , H01L2224/03 , H01L2224/11 , H01L2924/01014 , H01L2224/05552 , H01L2924/00012
摘要： A compact MEMS motion sensor device is provided, including a CMOS substrate layer, with plural anchor posts having an isolation oxide layer surrounding a conductive layer. On one side of CMOS substrate layer, the device further includes a field oxide (FOX) layer, a first set and a second set of implant doped silicon areas, a first polysilicon layer, an oxide layer embedded with plural metal layers interleaved with via hole layers, a Nitride deposition layer, an under bump metal (UBM) layer and a plurality of solder spheres. On the other side of CMOS substrate layer, the present invention further includes a backside interconnect isolation oxide layer, a first MEMS bonding layer, a first metal compound layer, a second MEMS bonding layer, a MEMS layer, a first MEMS eutectic bonding layer, a second metal compound layer, a second MEMS eutectic bonding layer, and a MEMS cap layer.
摘要翻译：提供了一种紧凑的MEMS运动传感器装置，其包括CMOS衬底层，多个锚柱具有围绕导电层的隔离氧化层。在CMOS衬底层的一侧，该器件还包括场氧化物（FOX）层，第一组和第二组注入掺杂硅区，第一多晶硅层，嵌入多个金属层的氧化物层，其与通孔交错层，氮化物沉积层，下凸块金属（UBM）层和多个焊球。在CMOS衬底层的另一侧，本发明还包括背面互连隔离氧化物层，第一MEMS结合层，第一金属化合物层，第二MEMS结合层，MEMS层，第一MEMS共晶接合层，第二金属化合物层，第二MEMS共晶接合层和MEMS覆盖层。

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