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41. 发明授权

US06617246B2 Semiconductor processing methods and integrated circuitry 有权
标题翻译：半导体处理方法和集成电路
公开(公告)号：US06617246B2
公开(公告)日：2003-09-09
申请号：US09891575
申请日：2001-06-25
申请人： Gurtej S. Sandhu , Ravi Iyer
发明人： Gurtej S. Sandhu , Ravi Iyer
IPC分类号： H01L2144
CPC分类号： H01L21/76843 , H01L21/32051 , H01L21/76846 , H01L21/7685
摘要： In aspect, the invention includes a semiconductor processing method including: a) forming an electrically insulative layer over a substrate; b) forming an opening within the electrically insulative layer, the opening having a periphery defined at least in part by a bottom surface and a sidewall surface; c) forming a first layer including TiN within the opening, the first layer being over the bottom surface and along the sidewall surface; d) forming a second layer including elemental Ti over the electrically insulative layer but substantially not within the opening, the second layer having a thickness of less than 50 Å along the sidewall surface and over the bottom surface; and e) forming a layer which includes aluminum within the opening and over the second layer. In another aspect, the invention includes a semiconductor processing method including: a) forming a first layer which includes aluminum over an electrically insulative layer; b) forming a first layer which includes titanium over the first layer which includes aluminum; c) forming a second layer which includes titanium over the first layer which includes titanium, one of the first and second layers which include titanium including elemental Ti and the other of the first and second layers which include titanium including TiN; and d) forming a second layer which includes aluminum over the second layer which includes titanium.
摘要翻译：在本发明中，本发明包括半导体处理方法，包括：a）在衬底上形成电绝缘层; b）在所述电绝缘层内形成开口，所述开口具有至少部分地由底表面和侧壁表面限定的周边; c）在所述开口内形成包括TiN的第一层，所述第一层在所述底表面上并沿着所述侧壁表面; d）在所述电绝缘层上形成包括元素Ti的第二层，但基本上不在所述开口内，所述第二层沿着所述侧壁表面并且在所述底表面上具有小于的厚度; 以及e）在所述开口内和所述第二层上形成包括铝的层。另一方面，本发明包括一种半导体处理方法，包括：a）在电绝缘层上形成包括铝的第一层; b）在包括铝的第一层上形成包括钛的第一层; c）在包括钛的第一层上形成包括钛的第二层，所述第一层和第二层中的一个包括包括元素Ti的钛，并且所述第一和第二层中的另一个包括包括TiN的钛; 以及d）在包括钛的第二层上形成包括铝的第二层。

42. 发明授权

US06605502B2 Isolation using an antireflective coating 有权
公开(公告)号：US06605502B2
公开(公告)日：2003-08-12
申请号：US10172895
申请日：2002-06-17
申请人： Ravi Iyer , Steven M. McDonald , Thomas R. Glass , Zhiping Yin
发明人： Ravi Iyer , Steven M. McDonald , Thomas R. Glass , Zhiping Yin
IPC分类号： H01L2176
CPC分类号： G03F7/091 , G03F7/092 , H01L21/0276 , H01L21/32 , H01L21/76202 , Y10T428/24471 , Y10T428/24917
摘要： A method of forming an oxidation diffusion barrier stack for use in fabrication of integrated circuits includes forming an inorganic antireflective material layer on a semiconductor substrate assembly with an oxidation diffusion barrier layer then formed on the inorganic antireflective material layer. Another method of forming such a stack includes forming a pad oxide layer on the semiconductor substrate assembly with an inorganic antireflective material layer then formed on the pad oxide layer and an oxidation diffusion barrier layer formed on the antireflective material layer. Another method of forming the stack includes forming a pad oxide layer on the semiconductor substrate assembly. A first oxidation diffusion barrier layer is then formed on the pad oxide layer, an inorganic antireflective material layer is formed on the first oxidation diffusion barrier layer, and a second oxidation diffusion barrier layer is formed on the inorganic antireflective material layer. The antireflective material layer may include a layer of material selected from the group of silicon nitride, silicon oxide, and silicon oxynitride and further may be a silicon-rich layer. The oxidation diffusion barrier stacks may be used for oxidation of field regions for isolation in an integration circuit. Further, the various oxidation diffusion barrier stacks are also described.

43. 发明授权

US06555471B2 Method of making a void-free aluminum film 有权
公开(公告)号：US06555471B2
公开(公告)日：2003-04-29
申请号：US09899373
申请日：2001-07-02
申请人： Gurtej S. Sandhu , Ravi Iyer
发明人： Gurtej S. Sandhu , Ravi Iyer
IPC分类号： H01L21425
CPC分类号： H01L23/53223 , H01L21/76847 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A method for depositing an aluminum film limits the growth of voids and notches in the aluminum film and forms and aluminum film with a reduced amount of voids and notches. The first step of the method is to form an underlying layer upon which is deposited an aluminum film having a first thickness. The surface of the aluminum film is then exposed to a passivation species which coats the aluminum grains and precipitates at the grain boundaries so as to prevent grain movement. The exposure of the aluminum film to the passivation species reduces void formation and coalescence of the voids. An aluminum layer having a second thickness is then deposited over the initially deposited aluminum layer. In a second embodiment of the invention, the passivation species is deposited with MOCVD and to form an electromigration-resistant alloy. A third embodiment involves multiple depositions of aluminum, with exposure to a passivation species conducted after each deposition. Each deposition is also conducted at a successively lower temperature than the prior deposition.

44. 发明授权

US06509281B2 Techniques for improving adhesion of silicon dioxide to titanium 失效
标题翻译：提高二氧化硅与钛的附着力的技术
公开(公告)号：US06509281B2
公开(公告)日：2003-01-21
申请号：US10016066
申请日：2001-12-11
申请人： Ravi Iyer
发明人： Ravi Iyer
IPC分类号： H01L2131
CPC分类号： H01L21/02164 , H01L21/02304 , H01L21/02315 , H01L21/316 , H01L21/31612
摘要： The present invention is described in several embodiments depicting structures and methods to form these structures. A first embodiment is a structure having a silicon dioxide film bonded to a metal film comprising: a metal nitride film bonded to the metal film; and the silicon dioxide film bonded to the metal nitride film. A second embodiment is a structure having a silicon dioxide film bonded to a metal film comprising: a metal oxide film bonded to the metal film; and the silicon dioxide film bonded to the metal oxide film. A third embodiment is a structure having a silicon dioxide film is bonded to a metal film comprising: a metal/oxide/nitride film bonded to the metal film; and the silicon dioxide film bonded to the metal/oxide/nitride film.
摘要翻译：在描述形成这些结构的结构和方法的几个实施例中描述了本发明。第一实施例是具有与金属膜结合的二氧化硅膜的结构，包括：与金属膜结合的金属氮化物膜; 和与金属氮化物膜结合的二氧化硅膜。第二实施例是具有与金属膜结合的二氧化硅膜的结构，包括：与金属膜结合的金属氧化物膜; 和与金属氧化物膜结合的二氧化硅膜。第三实施方案是将二氧化硅膜结合到金属膜上的结构，包括：金属/氧化物/氮化物膜与金属膜结合; 和与金属/氧化物/氮化物膜结合的二氧化硅膜。

45. 发明授权

US06495450B1 Isolation using an antireflective coating 有权
标题翻译：使用抗反射涂层进行隔离
公开(公告)号：US06495450B1
公开(公告)日：2002-12-17
申请号：US09620790
申请日：2000-07-21
申请人： Ravi Iyer , Steven M. McDonald , Thomas R. Glass , Zhiping Yin
发明人： Ravi Iyer , Steven M. McDonald , Thomas R. Glass , Zhiping Yin
IPC分类号： H01L214763
CPC分类号： G03F7/091 , G03F7/092 , H01L21/0276 , H01L21/32 , H01L21/76202 , Y10T428/24471 , Y10T428/24917
摘要： A method of forming an oxidation diffusion barrier stack for use in fabrication of integrated circuits includes forming an inorganic antireflective material layer on a semiconductor substrate assembly with an oxidation diffusion barrier layer then formed on the inorganic antireflective material layer. Another method of forming such a stack includes forming a pad oxide layer on the semiconductor substrate assembly with an inorganic antireflective material layer then formed on the pad oxide layer and an oxidation diffusion barrier layer formed on the antireflective material layer. The antireflective material layer may include a layer of material selected from the group of silicon nitride, silicon oxide, and silicon oxynitride and further may be a silicon-rich layer. The oxidation diffusion barrier stacks may be used for oxidation of field regions for isolation in an integration circuit. Further, the various oxidation diffusion barrier stacks are also described.
摘要翻译：形成用于集成电路制造的氧化扩散阻挡层叠体的方法包括在半导体衬底组件上形成无机抗反射材料层，然后在无机抗反射材料层上形成氧化扩散阻挡层。形成这种堆叠的另一种方法包括在半导体衬底组件上形成衬垫氧化物层，然后在衬垫氧化物层上形成无机抗反射材料层，形成在抗反射材料层上的氧化扩散阻挡层。抗反射材料层可以包括选自氮化硅，氧化硅和氮氧化硅的材料层，并且还可以是富硅层。氧化扩散阻挡层可以用于场集成电路中用于隔离的场区氧化。此外，还描述了各种氧化扩散阻挡层叠体。

46. 发明授权

US06432813B1 Semiconductor processing method of forming insulative material over conductive lines 有权
标题翻译：通过导线形成绝缘材料的半导体加工方法
公开(公告)号：US06432813B1
公开(公告)日：2002-08-13
申请号：US09369492
申请日：1999-08-05
申请人： Gurtej S. Sandhu , Ravi Iyer
发明人： Gurtej S. Sandhu , Ravi Iyer
IPC分类号： H01L2144
CPC分类号： H01L21/768 , H01L21/76838 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor processing method of forming an electrically conductive interconnect line having an electrical conductive covering predominately coextensive therewith, includes, a) providing an conductive interconnect line over a first electrically insulating material, the line having a top and sidewalls; b) selectively depositing a second electrically insulating material layer over the interconnect line and the first insulating material in a manner which deposits a greater thickness of the second insulating material atop the interconnect line than a thickness of the second insulating material over the first insulating material; c) anisotropically etching the second insulating material layer inwardly to at least the first insulating material yet leaving second insulating material over the top and the side walls of the interconnect line; and d) providing an electrically conductive layer over the anisotropically etched second insulating layer to form a conductive layer (which is predominately coextensive with the interconnect line over the etched second insulating material. The method further comprises provision of a base electrically conductive layer beneath the first insulating material, with the anisotropically etching step etching through the first insulating material to the base conductive layer, and the conductive layer being provided in electrical connection with the base conductive layer. Integrated circuitry produce by the method and other methods is also disclosed.
摘要翻译：一种形成具有与其主要共同延伸的导电覆盖层的导电互连线的半导体处理方法包括：a）在第一电绝缘材料上提供导电互连线，该线具有顶部和侧壁; b）在所述互连线和所述第一绝缘材料上选择性地沉积第二电绝缘材料层，所述第二电绝缘材料层以在所述互连线上方沉积更大厚度的所述第二绝缘材料的厚度大于所述第一绝缘材料上所述第二绝缘材料的厚度; c）将第二绝缘材料层向内各向异性地蚀刻到至少第一绝缘材料，而使第二绝缘材料留在互连线的顶部和侧壁上; 并且d）在各向异性蚀刻的第二绝缘层上方提供导电层以形成导电层（其主要与蚀刻的第二绝缘材料上的互连线共同延伸）。该方法还包括在第一绝缘层之下提供基底导电层绝缘材料，通过各向异性蚀刻步骤通过第一绝缘材料蚀刻到基底导电层，并且导电层设置为与基底导电层电连接。集成电路通过该方法产生，并且还公开了其他方法。

47. 发明授权

US06340637B2 Chemical vapor deposition of titanium from titanium tetrachloride and hydrocarbon reactants 有权
标题翻译：来自四氯化钛和烃反应物的钛的化学气相沉积
公开(公告)号：US06340637B2
公开(公告)日：2002-01-22
申请号：US09730038
申请日：2000-12-05
申请人： Ravi Iyer , Sujit Sharan
发明人： Ravi Iyer , Sujit Sharan
IPC分类号： H01L2144
CPC分类号： C23C16/08 , H01L21/28556 , H01L21/28568 , Y10S438/909
摘要： A new process for depositing titanium metal layers via chemical vapor deposition is disclosed. The process provides deposited titanium layers having a high degree of conformality, even in trenches and contact openings having aspect ratios greater than 1:5. The reaction gases for the improved process are titanium tetrachloride and a hydrocarbon gas, which for a preferred embodiment of the process is methane. The reaction is carried out in a plasma environment created by a radio frequency source greater than 10 KHz. The key to obtaining titanium metal as a reaction product, rather than titanium carbide, is to set the plasma sustaining electrical power within a range that will remove just one hydrogen atom from each molecule of the hydrocarbon gas. In a preferred embodiment of the process, highly reactive methyl radicals (CH3—) are formed from methane gas. These radicals attack the titanium-chlorine bonds of the tetrachloride molecule and form chloromethane, which is evacuated from the chamber as it is formed. Titanium metal deposits an a wafer or other substrate that has been heated to a temperature within a preferred range of 200-500° C.
摘要翻译：公开了一种通过化学气相沉积沉积钛金属层的新工艺。该方法即使在具有大于1:5的纵横比的沟槽和接触开口中也提供具有高度保形性的沉积钛层。用于改进方法的反应气体是四氯化钛和烃气体，其中该方法的优选实施方案是甲烷。该反应在由大于10KHz的射频源产生的等离子体环境中进行。获得钛金属作为反应产物而不是碳化钛的关键是将等离子体维持电功率设置在仅从烃气体的每个分子除去一个氢原子的范围内。在该方法的优选实施方案中，由甲烷气体形成高反应性甲基（CH 3 - ）。这些自由基攻击四氯化碳分子的钛 - 氯键，并形成氯甲烷，其形成时从室中排出。钛金属沉积了已被加热到200-500℃的优选范围内的晶片或其它基底。

48. 发明授权

US06333556B1 Insulating materials 失效
标题翻译：绝缘材料
公开(公告)号：US06333556B1
公开(公告)日：2001-12-25
申请号：US08947847
申请日：1997-10-09
申请人： Werner Juengling , Kirk D. Prall , Ravi Iyer , Gurtej S. Sandhu , Guy Blalock
发明人： Werner Juengling , Kirk D. Prall , Ravi Iyer , Gurtej S. Sandhu , Guy Blalock
IPC分类号： H01L23485
CPC分类号： H01L21/7682 , H01L21/02115 , H01L21/02118 , H01L21/02167 , H01L21/02203 , H01L21/02274 , H01L21/02282 , H01L21/02362 , H01L21/31695 , H01L21/76826 , H01L21/76828 , H01L21/76829 , H01L21/76834 , H01L23/5222 , H01L23/5329 , H01L2221/1047 , H01L2924/0002 , Y10T428/12014 , Y10T428/24149 , Y10T428/249921 , Y10T428/25 , Y10T428/259 , H01L2924/00
摘要： The invention encompasses methods of forming insulating materials between conductive elements. In one aspect, the invention includes a method of forming a material adjacent a conductive electrical component comprising: a) partially vaporizing a mass to form a matrix adjacent the conductive electrical component, the matrix having at least one void within it. In another aspect, the invention includes a method of forming a material between a pair of conductive electrical components comprising the following steps: a) forming a pair of conductive electrical components within a mass and separated by an expanse of the mass; b) forming at least one support member within the expanse of the mass, the support member not comprising a conductive interconnect; and c) vaporizing the expanse of the mass to a degree effective to form at least one void between the support member and each of the pair of conductive electrical components. In another aspect, the invention includes an insulating material adjacent a conductive electrical component, the insulating material comprising a matrix and at least one void within the matrix. In another aspect, the invention includes an insulating region between a pair of conductive electrical components comprising: a) a support member between the conductive electrical components, the support member not comprising a conductive interconnect; and b) at least one void between the support member and each of the pair of conductive electrical components.
摘要翻译：本发明包括在导电元件之间形成绝缘材料的方法。在一个方面，本发明包括形成邻近导电电气部件的材料的方法，该方法包括：a）部分蒸发物质以形成邻近导电电气部件的基体，所述基质在其内具有至少一个空隙。另一方面，本发明包括一种在一对导电电气部件之间形成材料的方法，包括以下步骤：a）在质量体内形成一对导电的电气部件，并由质量块的一部分分隔; b）在所述物体的宽度内形成至少一个支撑构件，所述支撑构件不包括导电互连; 以及c）将所述物质的所述膨胀物蒸发至有效地在所述支撑构件和所述一对导电电气部件中的每一个之间形成至少一个空隙的程度。在另一方面，本发明包括与导电电气部件相邻的绝缘材料，所述绝缘材料包含基体和所述基体内的至少一个空隙。在另一方面，本发明包括在一对导电电气部件之间的绝缘区域，包括：a）导电电气部件之间的支撑部件，所述支撑部件不包括导电互连; 以及b）所述支撑构件和所述一对导电电气部件中的每一个之间的至少一个空隙。

49. 发明授权

US06313046B1 Method of forming materials between conductive electrical components, and insulating materials 失效
标题翻译：在导电电气部件和绝缘材料之间形成材料的方法
公开(公告)号：US06313046B1
公开(公告)日：2001-11-06
申请号：US09115339
申请日：1998-07-14
申请人： Werner Juengling , Kirk D. Prall , Ravi Iyer , Gurtej S. Sandhu , Guy Blalock
发明人： Werner Juengling , Kirk D. Prall , Ravi Iyer , Gurtej S. Sandhu , Guy Blalock
IPC分类号： H01L2131
CPC分类号： H01L21/7682 , H01L21/02115 , H01L21/02118 , H01L21/02167 , H01L21/02203 , H01L21/02274 , H01L21/02282 , H01L21/02362 , H01L21/31695 , H01L21/76826 , H01L21/76828 , H01L21/76829 , H01L21/76834 , H01L23/5222 , H01L23/5329 , H01L2221/1047 , H01L2924/0002 , Y10T428/12014 , Y10T428/24149 , Y10T428/249921 , Y10T428/25 , Y10T428/259 , H01L2924/00
摘要： The invention encompasses methods of forming insulating materials between conductive elements. In one aspect, the invention includes a method of forming a material adjacent a conductive electrical component comprising: a) partially vaporizing a mass to form a matrix adjacent the conductive electrical component, the matrix having at least one void within it. In another aspect, the invention includes a method of forming a material between a pair of conductive electrical components comprising the following steps: a) forming a pair of conductive electrical components within a mass and separated by an expanse of the mass; b) forming at least one support member within the expanse of the mass, the support member not comprising a conductive interconnect; and c) vaporizing the expanse of the mass to a degree effective to form at least one void between the support member and each of the pair of conductive electrical components. In another aspect, the invention includes an insulating material adjacent a conductive electrical component, the insulating material comprising a matrix and at least one void within the matrix. In another aspect, the invention includes an insulating region between a pair of conductive electrical components comprising: a) a support member between the conductive electrical components, the support member not comprising a conductive interconnect; and b) at least one void between the support member and each of the pair of conductive electrical components.
摘要翻译：本发明涵盖在导电元件之间形成绝缘材料的方法。在一个方面，本发明包括形成邻近导电电气部件的材料的方法，该方法包括：a）部分蒸发物质以形成邻近导电电气部件的基体，所述基质在其内具有至少一个空隙。另一方面，本发明包括一种在一对导电电气部件之间形成材料的方法，包括以下步骤：a）在质量体内形成一对导电的电气部件，并由质量块的一部分分隔; b）在所述物体的宽度内形成至少一个支撑构件，所述支撑构件不包括导电互连; 以及c）将所述物质的所述膨胀物蒸发至有效地在所述支撑构件和所述一对导电电气部件中的每一个之间形成至少一个空隙的程度。在另一方面，本发明包括与导电电气部件相邻的绝缘材料，所述绝缘材料包含基体和所述基体内的至少一个空隙。在另一方面，本发明包括在一对导电电气部件之间的绝缘区域，包括：a）导电电气部件之间的支撑部件，所述支撑部件不包括导电互连; 以及b）所述支撑构件和所述一对导电电气部件中的每一个之间的至少一个空隙。

50. 发明授权

US06277737B1 Semiconductor processing methods and integrated circuitry 有权
标题翻译：半导体处理方法和集成电路
公开(公告)号：US06277737B1
公开(公告)日：2001-08-21
申请号：US09146113
申请日：1998-09-02
申请人： Gurtej S. Sandhu , Ravi Iyer
发明人： Gurtej S. Sandhu , Ravi Iyer
IPC分类号： H01L2144
CPC分类号： H01L21/76843 , H01L21/32051 , H01L21/76846 , H01L21/7685
摘要： In aspect, the invention includes a semiconductor processing method comprising: a) forming an electrically insulative layer over a substrate; b) forming an opening within the electrically insulative layer, the opening having a periphery defined at least in part by a bottom surface and a sidewall surface; c) forming a first layer comprising TiN within the opening, the first layer being over the bottom surface and along the sidewall surface; d) forming a second layer comprising elemental Ti over the electrically insulative layer but substantially not within the opening, the second layer having a thickness of less than 50 Å along the sidewall surface and over the bottom surface; and e) forming an aluminum-comprising layer within the opening and over the second layer. In another aspect, the invention includes a semiconductor processing method comprising: a) forming a first aluminum-comprising layer over an electrically insulative layer; b) forming a first titanium-comprising layer over the first aluminum-comprising layer; c) forming a second titanium-comprising layer over the first titanium-comprising layer, one of the first and second titanium-comprising layers comprising elemental Ti and the other of the first and second titanium-comprising layers comprising TiN; and d) forming a second aluminum-comprising layer over the second titanium-comprising layer.
摘要翻译：在本发明中，本发明包括半导体处理方法，包括：a）在衬底上形成电绝缘层; b）在所述电绝缘层内形成开口，所述开口具有至少部分地由底表面和侧壁表面限定的周边; c）在所述开口内形成包含TiN的第一层，所述第一层在所述底表面上并沿着所述侧壁表面; d）在所述电绝缘层上形成包括元素Ti的第二层，但基本上不在所述开口内，所述第二层沿着所述侧壁表面并在所述底表面上具有小于的厚度; 以及e）在所述开口内和所述第二层上形成含铝层。另一方面，本发明包括一种半导体处理方法，包括：a）在电绝缘层上形成第一含铝层; b）在所述第一含铝层上形成第一含钛层; c）在所述第一含钛层上形成第二含钛层，所述第一和第二含钛层中的一个包含元素Ti，所述第一和第二含钛层中的另一个包含TiN; 以及d）在所述第二含钛层上形成第二含铝层。

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