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31. 发明授权

US07017066B2 Method, system and synchronization circuit for providing hardware component access to a set of data values without restriction 失效
标题翻译：方法，系统和同步电路，用于不受限制地提供对一组数据值的硬件组件访问
公开(公告)号：US07017066B2
公开(公告)日：2006-03-21
申请号：US10411864
申请日：2003-04-10
申请人： Eric E. Retter , John M. Sutton
发明人： Eric E. Retter , John M. Sutton
IPC分类号： G06F1/12 , G06F1/14 , G06F1/04 , G04C11/00 , G04C19/00 , G04C19/02
CPC分类号： H04N21/426 , G06F1/12 , H04L7/0045 , H04L7/02
摘要： The present invention provides hardware-based synchronization within a device such as a set top box so that sets of data values can be communicated between a set of DCR registers operating at a first frequency and a set of clock register operating at a second frequency. Specifically, to communicate an initial set of data values from the set of DCR registers to the set of clock registers, a control signal is stretched and then synchronized with a clock signal having the second frequency. To communicate a current set of data values from the set of clock registers to the set of DCR registers, the control signal is synchronized with a clock signal having the first frequency. By communicating the current set of data values to the first set of registers, a hardware component (e.g., a CPU) can access the current set of data values without restriction.
摘要翻译：本发明在诸如机顶盒的设备中提供基于硬件的同步，使得可以在以第一频率工作的一组DCR寄存器和以第二频率操作的一组时钟寄存器之间传送数据值集合。具体地说，为了将来自DCR寄存器的一组初始的数据值集合传送到时钟寄存器组，控制信号被拉伸，然后与具有第二频率的时钟信号同步。为了将当前的一组数据值从该组时钟寄存器传送到一组DCR寄存器，控制信号与具有第一频率的时钟信号同步。通过将当前数据值集合传送到第一组寄存器，硬件组件（例如，CPU）可以无限制地访问当前数据值集合。

32. 发明授权

US06958953B2 Real time clock circuit having an internal clock generator 失效
标题翻译：具有内部时钟发生器的实时时钟电路
公开(公告)号：US06958953B2
公开(公告)日：2005-10-25
申请号：US10437123
申请日：2003-05-13
申请人： Eric E. Retter , John M. Sutton
发明人： Eric E. Retter , John M. Sutton
IPC分类号： G04G5/00 , G04G15/00 , G04C11/02
CPC分类号： G04G15/006 , G04R20/02
摘要： Under the present invention a real time clock circuit, within a set-top box, is provided with an internal clock generator for generating multiple clock signals. Once generated, a first clock signal is divided into an initial set of values representing time and optionally day/date intervals, and then communicated to a set of clock registers. The initial set of values can then be communicated (directly or via a set of DCR registers) to a display component within the set-top box. Updated clock signals are received by the set of DCR registers from an external source such as a satellite or the like thus making the clock very accurate, and are communicated to the display component. Similar to the initial set of values, the updated set of values could be communicated to the display component directly from the set of DCR registers, or via the set of clock registers.
摘要翻译：在本发明中，在机顶盒内的实时时钟电路设置有用于产生多个时钟信号的内部时钟发生器。一旦生成，第一时钟信号被分成表示时间和可选的日/日间隔的初始值集合，然后传送给一组时钟寄存器。然后可以将初始值集合（直接或经由一组DCR寄存器）传送到机顶盒内的显示组件。更新的时钟信号由来自诸如卫星等的外部源的DCR寄存器组接收，从而使时钟非常精确，并被传送到显示组件。类似于初始值的值，更新的值集合可以直接从DCR寄存器集或通过一组时钟寄存器传送给显示组件。

33. 发明授权

US08131974B2 Access speculation predictor implemented via idle command processing resources 失效
标题翻译：通过空闲命令处理资源实现访问推测预测器
公开(公告)号：US08131974B2
公开(公告)日：2012-03-06
申请号：US12105427
申请日：2008-04-18
申请人： Richard Nicholas , Ram Raghavan , Eric E. Retter , Jeffrey A. Stuecheli
发明人： Richard Nicholas , Ram Raghavan , Eric E. Retter , Jeffrey A. Stuecheli
IPC分类号： G06F12/00 , G06F9/26 , G06F9/34
CPC分类号： G06F12/0862 , G06F12/0831 , G06F2212/507 , G06F2212/6022 , G06F2212/6024 , Y02D10/13
摘要： An access speculation predictor is provided that may be implemented using idle command processing resources, such as registers of idle finite state machines (FSMs) in a memory controller. The access speculation predictor may predict whether to perform speculative retrieval of data for a data request from a main memory of the data processing system based on history information stored for a memory region targeted by the data request. In particular, a first address may be extracted from the data request and compared to memory regions associated with second addresses stored in address registers of a plurality of FSMs of the memory controller. A FSM whose memory region includes the first address may be selected. History information for the memory region may be obtained from the selected FSM. The history information may be used to control whether to speculatively retrieve the data for the data request from a main memory.
摘要翻译：提供了可以使用诸如存储器控制器中的空闲有限状态机（FSM）的寄存器的空闲命令处理资源来实现的访问推测预测器。访问推测预测器可以基于针对数据请求所针对的存储区域存储的历史信息来预测是否对数据处理系统的主存储器执行针对数据请求的数据的推测检索。特别地，可以从数据请求中提取第一地址，并与存储在存储器控制器的多个FSM的地址寄存器中的第二地址相关联的存储器区域进行比较。可以选择其存储区域包括第一地址的FSM。可以从所选择的FSM获得用于存储器区域的历史信息。历史信息可以用于控制是否从主存储器推测性地检索数据请求的数据。

34. 发明授权

US08122222B2 Access speculation predictor with predictions based on a scope predictor 失效
标题翻译：基于范围预测器访问具有预测的投机预测因子
公开(公告)号：US08122222B2
公开(公告)日：2012-02-21
申请号：US12105360
申请日：2008-04-18
申请人： Richard Nicholas , Eric E. Retter , Jeffrey A. Stuecheli
发明人： Richard Nicholas , Eric E. Retter , Jeffrey A. Stuecheli
IPC分类号： G06F12/00 , G06F9/26 , G06F9/34
CPC分类号： G06F12/0862 , G06F12/0215 , G06F12/0831 , G06F2212/1041 , G06F2212/507 , G06F2212/6022 , G06F2212/6024
摘要： An access speculation predictor may predict whether to perform speculative retrieval of data for a data request from a main memory based on whether a scope predictor indicates whether a local or global request is predicted to be necessary to obtain the data for the data request. In particular, a first address and a scope predictor may be extracted from a first data request. A determination may be made as to whether a memory controller receiving the first data request is local to a source of the first data request or not. Speculative retrieval of the data for the first data request from a main memory may be controlled based on whether the memory controller is local to the source of the first data request and whether the scope predictor identifies whether a local or a global request is predicted to be necessary.
摘要翻译：访问推测预测器可以基于范围预测器是否预测本地或全局请求是否需要以获得数据请求的数据来预测是否对来自主存储器的数据请求的数据进行推测检索。特别地，可以从第一数据请求中提取第一地址和范围预测器。可以确定接收第一数据请求的存储器控制器是否是本地的第一数据请求的源。可以基于存储器控制器是否为第一数据请求的源的本地来控制来自主存储器的用于第一数据请求的数据的推测性检索，以及范围预测器是否预测本地或全局请求是否被预测为必要。

35. 发明申请

US20100005281A1 POWER-ON INITIALIZATION AND TEST FOR A CASCADE INTERCONNECT MEMORY SYSTEM 失效
标题翻译：串联互连存储器系统的上电初始化和测试
公开(公告)号：US20100005281A1
公开(公告)日：2010-01-07
申请号：US12166139
申请日：2008-07-01
申请人： Peter L. Buchmann , Frank D. Ferraiolo , Kevin C. Gower , Robert J. Reese , Eric E. Retter , Martin L. Schmatz , Michael B. Spear , Peter M. Thomsen , Michael R. Trombley
发明人： Peter L. Buchmann , Frank D. Ferraiolo , Kevin C. Gower , Robert J. Reese , Eric E. Retter , Martin L. Schmatz , Michael B. Spear , Peter M. Thomsen , Michael R. Trombley
IPC分类号： G06F9/24
CPC分类号： G06F13/4243 , Y02D10/14 , Y02D10/151
摘要： A memory buffer, memory system and method for power-on initialization and test for a cascade interconnect memory system. The memory buffer includes a bus interface to links in a high-speed channel for communicating with a memory controller via a direct connection or via a cascade interconnection through an other memory buffer. The interface is operable in a SBC mode and a high-speed mode. The memory buffer also includes a field service interface (FSI) slave for receiving FSI signals from a FSI master. In addition, the memory buffer includes logic for executing a power-on and initialization training sequence initiated by the memory controller.
摘要翻译：用于级联互连存储器系统的上电初始化和测试的存储器缓冲器，存储器系统和方法。存储器缓冲器包括到高速通道中的链路的总线接口，用于经由直接连接或通过其他存储器缓冲器的级联互连与存储器控制器进行通信。该接口可在SBC模式和高速模式下工作。存储器缓冲器还包括用于从FSI主机接收FSI信号的现场服务接口（FSI）从站。此外，存储器缓冲器包括用于执行由存储器控制器启动的上电和初始化训练序列的逻辑。

36. 发明授权

US07571357B2 Memory wrap test mode using functional read/write buffers 失效
标题翻译：内存包装测试模式使用功能读/写缓冲区
公开(公告)号：US07571357B2
公开(公告)日：2009-08-04
申请号：US11466111
申请日：2006-08-22
申请人： Mark A. Brittain , Edgar R. Cordero , John T. Hollaway, Jr. , Eric E. Retter
发明人： Mark A. Brittain , Edgar R. Cordero , John T. Hollaway, Jr. , Eric E. Retter
IPC分类号： G06F11/00
CPC分类号： G01R31/31722 , G01R31/31712 , G11C29/48
摘要： A memory controller for a processing unit provides a memory wrap test mode path which selectively writes data from the write buffer of the controller to the read buffer of the controller, thereby allowing the write and read buffers to substitute for a system memory device during testing of the processing unit. The processing unit can thus be tested without the attached memory device yet still operate under conditions which generate bus traffic and chip noise similar to that generated under actual (end-use) operation. When a processor issues a write operation in test mode, the controller writes the data to an entry of the read buffer which corresponds to the write address. Thereafter, the processor can issue a read operation with the same address and the read buffer will send the data from the corresponding entry.
摘要翻译：用于处理单元的存储器控制器提供存储器包裹测试模式路径，其选择性地将数据从控制器的写入缓冲器写入到控制器的读取缓冲器，从而允许写入和读取缓冲器在测试期间替换系统存储器件处理单元。因此，处理单元可以在没有附加的存储器件的情况下进行测试，但仍然在产生与实际（最终使用）操作下生成的总线流量和芯片噪声类似的条件下操作。当处理器在测试模式下发出写入操作时，控制器将数据写入对应于写入地址的读取缓冲器的条目。此后，处理器可以发出具有相同地址的读取操作，并且读取缓冲器将从相应的条目发送数据。

37. 发明申请

US20080215929A1 SWITCHING A DEFECTIVE SIGNAL LINE WITH A SPARE SIGNAL LINE WITHOUT SHUTTING DOWN THE COMPUTER SYSTEM 失效
标题翻译：切换带有备用信号线的有缺陷的信号线，而不需要切断计算机系统
公开(公告)号：US20080215929A1
公开(公告)日：2008-09-04
申请号：US12098294
申请日：2008-04-04
申请人： Edgar R. Cordero , James S. Fields , Kevin C. Gower , Eric E. Retter
发明人： Edgar R. Cordero , James S. Fields , Kevin C. Gower , Eric E. Retter
IPC分类号： G06F11/00
CPC分类号： G06F11/10 , G06F11/2007 , G11C29/025 , G11C2029/0409
摘要： A method, computer program product and system for switching a defective signal line with a spare signal line without shutting down the computer system. A service processor monitors error correction code (ECC) check units configured to detect an error in a signal line. If an ECC check unit detects an error rate that exceeds a threshold, then the signal line with such an error rate may be said to be “defective.” The service processor configures switch control units in the driver/receiver pair associated with the defective signal line to be able to switch the defective signal line with a spare line upon receipt of a command from a memory controller switch control unit. In this manner, the system is not deactivated in order to switch a defective signal line with a spare line thereby reducing the time that the processor cannot send information to the memory buffers.
摘要翻译：一种用于在不关闭计算机系统的情况下用备用信号线切换有缺陷的信号线的方法，计算机程序产品和系统。服务处理器监视配置成检测信号线中的错误的纠错码（ECC）检查单元。如果ECC检查单元检测到错误率超过阈值，则具有这种错误率的信号线可能被认为是“有缺陷的”。服务处理器配置与缺陷信号线相关联的驱动器/接收器对中的开关控制单元，以便在从存储器控制器开关控制单元接收到命令时能够用备用线切换故障信号线。以这种方式，为了用备用线切换有缺陷的信号线，系统不被去激活，从而减少处理器不能向存储器缓冲器发送信息的时间。

38. 发明授权

US06701397B1 Pre-arbitration request limiter for an integrated multi-master bus system 失效
标题翻译：集成多主总线系统的仲裁前请求限制器
公开(公告)号：US06701397B1
公开(公告)日：2004-03-02
申请号：US09531654
申请日：2000-03-21
申请人： Eric M. Foster , Steven B. Herndon , Eric E. Retter , Ronald S. Svec
发明人： Eric M. Foster , Steven B. Herndon , Eric E. Retter , Ronald S. Svec
IPC分类号： G06F1300
CPC分类号： G09G5/001 , G06F13/3625
摘要： A method and structure for dynamically blocking access of a request signal R to a shared bus such that R originates from a non real-time master and requests access to an address range of an address space. The shared bus manages requests for access to the address space. The non real-time master and a real-time master compete for access to the address space by presenting address access requests to the shared bus. The dynamic blocking of access by R to the shared bus is accomplished by use of a request limiter, which is a device that is coupled to a real-time clock and uses an algorithm to determine when to enable and disable access of R to the shared bus. The algorithm uses a windowing scheme that permits access of R to the shared bus every Nth clock cycle, wherein the value of the integer N may be supplied to the request limiter by the real-time master. An example of the algorithm includes blocking access of R to the shared bus whenever all of the following conditions occur: the real-time master has a non-empty internal queue, the real master and the non real master are both requesting access to a same address range of the address space, and the real-time clock is not at the Nth clock cycle that permits access of R to the shared bus.
摘要翻译：一种用于动态地阻止请求信号R访问共享总线的方法和结构，使得R从非实时主机发起，并请求访问地址空间的地址范围。共享总线管理访问地址空间的请求。非实时主机和实时主机通过向共享总线呈现地址访问请求来竞争访问地址空间。通过使用请求限制器来实现R到共享总线的动态阻塞，该请求限制器是耦合到实时时钟的设备，并且使用算法来确定何时启用和禁用对共享的R的访问总线。该算法使用允许每N个时钟周期将R访问共享总线的开窗方案，其中整数N的值可以由实时主机提供给请求限制器。该算法的一个例子包括：当所有以下情况发生时，将R阻塞到共享总线的访问：实时主机具有非空的内部队列，实际主机和非真实主机都请求访问相同的地址空间的地址范围，并且实时时钟不在允许R访问共享总线的第N个时钟周期。

39. 发明授权

US06654835B1 High bandwidth data transfer employing a multi-mode, shared line buffer 有权
标题翻译：采用多模式共享线路缓冲器的高带宽数据传输
公开(公告)号：US06654835B1
公开(公告)日：2003-11-25
申请号：US09535068
申请日：2000-03-23
申请人： Eric M. Foster , Eric E. Retter , Ronald S. Svec
发明人： Eric M. Foster , Eric E. Retter , Ronald S. Svec
IPC分类号： G06F1300
CPC分类号： G06F13/1673 , H04N5/775 , H04N9/8042
摘要： A technique for transferring data between a first device and a second device using a shared line buffer connected to a system bus which couples the first device and the second device. The technique includes (i) transferring data between the line buffer and dedicated memory associated with the first device, wherein the first device includes a data controller coupled to the system bus through a bus interface. The transferring (i) includes using the data transfer controller to effectuate a multiword data transfer between the dedicated memory and the line buffer. The technique further includes multiword data (ii) transferring between the line buffer and the second device across the system bus. When the transferring (i) precedes the transferring (ii), data is read from the dedicated memory from output to the second device, and when the transferring (ii) precedes the transferring (i), data is written to dedicated memory from the second device.
摘要翻译：一种用于使用连接到耦合第一设备和第二设备的系统总线的共享线路缓冲器在第一设备和第二设备之间传送数据的技术。该技术包括（i）在行缓冲器和与第一设备相关联的专用存储器之间传送数据，其中第一设备包括通过总线接口耦合到系统总线的数据控制器。传输（i）包括使用数据传输控制器来实现专用存储器和行缓冲器之间的多字数据传输。该技术还包括多字数据（ii）跨系统总线在线路缓冲器和第二设备之间传送。当传输（i）在传输（ii）之前时，数据从专用存储器从输出读取到第二设备，并且当传输（ii）在传输（i）之前时，数据从第二个数据被写入专用存储器设备。

40. 发明授权

US5617577A Advanced parallel array processor I/O connection 失效
标题翻译：高级并行阵列处理器I / O连接
公开(公告)号：US5617577A
公开(公告)日：1997-04-01
申请号：US400687
申请日：1995-03-08
申请人： Thomas N. Barker , Clive A. Collins , Michael C. Dapp , James W. Dieffenderfer , Donald G. Grice , Billy J. Knowles , Donald M. Lesmeister , Richard E. Nier , Eric E. Retter , David B. Rolfe , Vincent J. Smoral
发明人： Thomas N. Barker , Clive A. Collins , Michael C. Dapp , James W. Dieffenderfer , Donald G. Grice , Billy J. Knowles , Donald M. Lesmeister , Richard E. Nier , Eric E. Retter , David B. Rolfe , Vincent J. Smoral
IPC分类号： G06F7/57 , G06F9/30 , G06F9/318 , G06F9/38 , G06F15/173 , G06F15/80 , G06F13/00
CPC分类号： G06F7/483 , G06F15/17337 , G06F15/17343 , G06F15/17381 , G06F15/8007
摘要： A fast I/O for a multi-PME computer system provides a way to break into a network coupling to alternate network couplings. The system coupling is called a zipper.Our I/O zipper concept can be used to implement the concept that the port into a node could be driven by the port out of a node or by data coming from the system bus. Conversely, data being put out of a node would be available to both the input to another node and to the system bus. Outputting data to both the system bus and another node is not done simultaneously but in different cycles. The zipper passes data into and out of a network of interconnected nodes is used in a system of interconnecting nodes in a mesh, rings of wrapped tori. such that there is no edge to the network, the zipper mechanism logically breaks the the rings along a dimension orthogonal to the rings such that an edge to the network is established. The coupling dynamically toggles the network between a network without an edge and a network with an edge. Data passes into the network or out of the network through the edge when it is active, and the coupling permits dispersal of data entering the network or collection of data leaving the network such that the data rate through the edge matches both the sustained and peak data rates of the system external to the network.
摘要翻译：多PME计算机系统的快速I / O提供了一种方法，可以将网络耦合到备用网络耦合中。系统耦合称为拉链。我们的I / O拉链概念可用于实现端口到节点中的端口可以由节点驱动的端口或来自系统总线的数据的概念。相反，放出节点的数据对于另一个节点和系统总线的输入将是可用的。将数据输出到系统总线和另一个节点都不是同时进行，而是在不同的周期内完成。拉链将数据传入和传出互连节点的网络用于网状互连节点的系统，包裹圆环的环。使得网络没有边缘，拉链机构沿着与环正交的尺寸逻辑地断开环，使得建立到网络的边缘。耦合动态地在无边缘的网络和具有边缘的网络之间切换网络。当数据有效时，数据通过边缘进入网络或网络，并且耦合允许分散进入网络的数据或离开网络的数据收集，使得通过边缘的数据速率与持续和峰值数据匹配网络外部系统的速率。

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