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31. 发明授权

US08258811B2 Enhanced field programmable gate array 有权
标题翻译：增强型现场可编程门阵列
公开(公告)号：US08258811B2
公开(公告)日：2012-09-04
申请号：US13158019
申请日：2011-06-10
申请人： Samuel W. Beal , Sinan Kaptanoglu , Jung-Cheun Lien , William Shu , King W. Chan , William C. Plants
发明人： Samuel W. Beal , Sinan Kaptanoglu , Jung-Cheun Lien , William Shu , King W. Chan , William C. Plants
IPC分类号： H03K19/177
CPC分类号： H03K19/17768 , H03K19/1736 , H03K19/17704 , H03K19/17732 , H03K19/17736 , H03K19/17744 , H03K19/17796
摘要： An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmable gate array, the mask-programmable gate array and the integrated circuit I/O.
摘要翻译：增强的性能现场可编程门阵列集成电路包括现场可编程门阵列和其它功能电路，例如同一集成电路中的掩模可编程门阵列。电路接口提供现场可编程门阵列，掩模可编程门阵列和集成电路I / O之间的通信。

32. 发明授权

US08225259B1 Apparatus and methods for time-multiplex field-programmable gate arrays with multiple clocks 有权
标题翻译：具有多个时钟的时域复用现场可编程门阵列的装置和方法
公开(公告)号：US08225259B1
公开(公告)日：2012-07-17
申请号：US11129796
申请日：2005-05-16
申请人： David W. Mendel , Sinan Kaptanoglu
发明人： David W. Mendel , Sinan Kaptanoglu
IPC分类号： G06F17/50
CPC分类号： H03K19/17748 , H03K19/017581 , H03K19/177 , H03K19/17728 , H03K19/1774 , H03K19/17796
摘要： A multiple-clock time-multiplexed field programmable gate array (TM-FPGA) includes programmable logic circuitry. A plurality of clock signals within the TM-FPGA couple to the programmable logic circuitry. A user's circuit can be mapped to the programmable logic circuitry without the user's intervention in mapping the circuit to the programmable logic circuitry.
摘要翻译：多时钟时间复用现场可编程门阵列（TM-FPGA）包括可编程逻辑电路。 TM-FPGA内的多个时钟信号耦合到可编程逻辑电路。用户的电路可以映射到可编程逻辑电路，而无需用户介入将电路映射到可编程逻辑电路。

33. 发明授权

US08217678B1 Fracturable lookup table and logic element 有权
标题翻译：可破坏的查找表和逻辑元素
公开(公告)号：US08217678B1
公开(公告)日：2012-07-10
申请号：US12834404
申请日：2010-07-12
申请人： David Lewis , Bruce Pedersen , Sinan Kaptanoglu , Andy L. Lee
发明人： David Lewis , Bruce Pedersen , Sinan Kaptanoglu , Andy L. Lee
IPC分类号： H03K19/173
CPC分类号： H03K19/177
摘要： A logic element includes memory elements, multiplexers, and controls. The multiplexers are arranged in levels including a highest level of multiplexers with inputs connected to the memory elements and outputs connected to inputs of a next-to-highest level of multiplexers and a first level of multiplexers with inputs connected to outputs of a second level of multiplexers and at least one output. The controls are connected to the multiplexers. In a first operational mode the controls determine a first-mode output at the at least one output of the first level of multiplexers, and in a second operational mode the controls determine a plurality of second-mode outputs at selected outputs of multiplexers not at the first level of multiplexers.
摘要翻译：逻辑元件包括存储器元件，多路复用器和控制器。多路复用器被布置在包括最高级别的多路复用器的级别中，其中连接到存储器元件的输入端和连接到下一级到最高级复用器的输出的输出端和第一级多路复用器，其输入端连接到第二级多路复用器和至少一个输出。控制器连接到多路复用器。在第一操作模式中，所述控制确定所述第一级多路复用器的所述至少一个输出处的第一模式输出，并且在第二操作模式中，所述控制确定多路复用器的选定输出处的多个第二模式输出，第一级多路复用器。

34. 发明授权

US07911230B1 Omnibus logic element for packing or fracturing 有权
$Omnibus logic element for packing or fracturing$
标题翻译：用于包装或压裂的综合逻辑元件
公开(公告)号：US07911230B1
公开(公告)日：2011-03-22
申请号：US12425342
申请日：2009-04-16
申请人： James Schleicher , Richard Yuan , Bruce Pedersen , Sinan Kaptanoglu , Gregg Baeckler , David Lewis , Mike Hutton , Andy Lee , Rahul Saini , Henry Kim
发明人： James Schleicher , Richard Yuan , Bruce Pedersen , Sinan Kaptanoglu , Gregg Baeckler , David Lewis , Mike Hutton , Andy Lee , Rahul Saini , Henry Kim
IPC分类号： H03K19/173
CPC分类号： H03K19/17728 , G06F7/50 , H03K19/017581
摘要： Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can be configured to implement register packing and/or a fracturable look up table.
摘要翻译：公开了可以提供多个有利特征的逻辑元件（LE）。例如，LE可以被配置为实现寄存器打包和/或可破碎的查找表。

35. 发明授权

US07557612B2 Block symmetrization in a field programmable gate array 有权
标题翻译：在现场可编程门阵列中的块对称
公开(公告)号：US07557612B2
公开(公告)日：2009-07-07
申请号：US12130876
申请日：2008-05-30
申请人： Sinan Kaptanoglu
发明人： Sinan Kaptanoglu
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17728 , H03K19/1778 , H03K19/17796
摘要： An FPGA architecture has top, middle and low levels. The top level is an array of B16×16 tiles enclosed by I/O blocks. The routing resources in the middle level are expressway routing channels including interconnect conductors. At the lowest level, there are block connect routing channels, local mesh routing channels, and direct connect interconnect conductors to connect the logic elements to further routing resources. Each B1 block includes four clusters of devices. Each of the clusters includes first and second LUT3s, a LUT2, and a DFF. Each of the LUT3s have three inputs and one output. Each of the LUT2s have two inputs and one output. Each DFF has a data input and a data output. In each of the clusters the outputs of the LUT3s are multiplexed to the input of DFF, and symmetrized with the output of the DFF to form two outputs of each of the clusters.
摘要翻译： FPGA架构具有顶级，中级和低级。顶级是由I / O块包围的B16x16瓦数组。中间路由资源是高速公路路由信道，包括互连导体。在最底层，有块连接路由通道，本地网状路由通道和直接连接互连导体，以将逻辑元件连接到更多的路由资源。每个B1块包括四组设备。每个簇包括第一和第二LUT3，LUT2和DFF。每个LUT3有三个输入和一个输出。每个LUT2有两个输入和一个输出。每个DFF都有数据输入和数据输出。在每个簇中，LUT3的输出被复用到DFF的输入，并且与DFF的输出对称，以形成每个簇的两个输出。

36. 发明授权

US07538579B1 Omnibus logic element 有权
标题翻译：综合逻辑元素
公开(公告)号：US07538579B1
公开(公告)日：2009-05-26
申请号：US11607171
申请日：2006-12-01
申请人： James Schleicher , Richard Yuan , Bruce Pedersen , Sinan Kaptanoglu , Gregg Baeckler , David Lewis , Mike Hutton , Andy Lee , Rahul Saini , Henry Kim
发明人： James Schleicher , Richard Yuan , Bruce Pedersen , Sinan Kaptanoglu , Gregg Baeckler , David Lewis , Mike Hutton , Andy Lee , Rahul Saini , Henry Kim
IPC分类号： H03K19/177
CPC分类号： H03K19/17728 , G06F7/50 , H03K19/017581
摘要： Disclosed is an LE that can provide a number of advantageous features. For example, the LE can provide efficient and flexible use of LUTs and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality.
摘要翻译：公开了可以提供许多有利特征的LE。例如，LE可以提供LUT和输入共享的高效灵活的使用。 LE还可以灵活地使用一个或多个专用加法器并且包括寄存器功能。

37. 发明授权

US07408383B1 FPGA architecture having two-level cluster input interconnect scheme without bandwidth limitation 有权
标题翻译：具有两级集群输入互连方案的FPGA架构，无带宽限制
公开(公告)号：US07408383B1
公开(公告)日：2008-08-05
申请号：US11855974
申请日：2007-09-14
申请人： Wenyi Feng , Sinan Kaptanoglu
发明人： Wenyi Feng , Sinan Kaptanoglu
IPC分类号： H01L25/00 , H03K19/177
CPC分类号： H03K19/17736
摘要： An interconnect architecture for a programmable logic device comprises a plurality of interconnect routing lines. The data inputs of a plurality of first-level multiplexers are connected to the plurality of interconnect routing lines such that each interconnect routing line is connected to only one multiplexer. A plurality of second-level multiplexers are organized into multiplexer groups. Each of a plurality of lookup tables is associated with one of the multiplexer groups and has a plurality of lookup table inputs. Each lookup table input is coupled to the output of a different one of the second-level multiplexers in the one of the multiplexer groups with which it is associated. The data inputs of the second-level multiplexers are connected to the outputs of the first-level multiplexers such that each output of each first-level multiplexer is connected to an input of only one second-level multiplexer in each multiplexer group.
摘要翻译：用于可编程逻辑器件的互连架构包括多个互连路由线。多个第一级复用器的数据输入连接到多个互连路由线，使得每个互连路由线仅连接到一个多路复用器。多个第二级多路复用器被组织成多路复用器组。多个查找表中的每一个与多路复用器组中的一个相关联并且具有多个查找表输入。每个查找表输入耦合到与其相关联的多路复合器组中的一个中的不同的一个二级多路复用器的输出。第二级复用器的数据输入连接到第一级复用器的输出端，使得每个第一级多路复用器的每个输出端连接到每个复用器组中只有一个二级多路复用器的输入。

38. 发明授权

US07330052B2 Area efficient fractureable logic elements 有权
$Area efficient fractureable logic elements$
标题翻译：区域有效的可断裂逻辑元件
公开(公告)号：US07330052B2
公开(公告)日：2008-02-12
申请号：US11234538
申请日：2005-09-22
申请人： Sinan Kaptanoglu , Bruce B. Pedersen , James G. Schleicher , Jinyong Yuan , Michael D. Hutton , David Lewis
发明人： Sinan Kaptanoglu , Bruce B. Pedersen , James G. Schleicher , Jinyong Yuan , Michael D. Hutton , David Lewis
IPC分类号： G06F7/38 , H03K19/177
CPC分类号： H03K19/1737
摘要： A fracturable logic element includes a first, second, third, and fourth two-input lookup tables (2-LUTs). Each 2-LUT includes four memory elements. Each memory element is configured to hold one data bit. The fracturable logic element also includes a set of six inputs and a control circuit configured to operate in a first mode and a second mode. When the control circuit operates in the first mode, a first combinatorial output is generated using four of the set of six inputs and the first, second, third, and fourth 2-LUTs. When the control circuit operates in the second mode, a second combinatorial output is generated using a first subset of three of the set of six inputs and the first and second 2-LUTs. Additionally, when the control circuit operates in the second mode, a third combinatorial output is generated using a second subset of three of the set of six inputs and the third and fourth 2-LUTs, the first and second subsets being non-intersecting subsets of the set of six inputs.
摘要翻译：可分解逻辑元件包括第一，第二，第三和第四双输入查找表（2-LUT）。每个2-LUT包括四个存储元件。每个存储器元件被配置为保持一个数据位。可分解逻辑元件还包括一组六个输入和被配置为在第一模式和第二模式下操作的控制电路。当控制电路在第一模式下工作时，使用六个输入和第一，第二，第三和第四2-LUT中的四个产生第一组合输出。当控制电路在第二模式下操作时，使用六组输入和第一和第二2-LUT组中的三个的第一子集来生成第二组合输出。另外，当控制电路在第二模式下工作时，使用六组输入和第三和第四2-LUT组中的三个的第二子集来产生第三组合输出，第一和第二子集是不相交的子集一组六个输入。

39. 发明授权

US07312632B2 Fracturable lookup table and logic element 有权
标题翻译：可破坏的查找表和逻辑元素
公开(公告)号：US07312632B2
公开(公告)日：2007-12-25
申请号：US11753048
申请日：2007-05-24
申请人： David Lewis , Bruce Pedersen , Sinan Kaptanoglu , Andy Lee
发明人： David Lewis , Bruce Pedersen , Sinan Kaptanoglu , Andy Lee
IPC分类号： H03K19/173
CPC分类号： H03K19/17728 , H03K19/1737
摘要： A logic element includes memory elements, multiplexers, and controls. The multiplexers are arranged in levels including a highest level of multiplexers with inputs connected to the memory elements and outputs connected to inputs of a next-to-highest level of multiplexers and a first level of multiplexers with inputs connected to outputs of a second level of multiplexers and at least one output. The controls are connected to the multiplexers. In a first operational mode the controls determine a first-mode output at the at least one output of the first level of multiplexers, and in a second operational mode the controls determine a plurality of second-mode outputs at selected outputs of multiplexers not at the first level of multiplexers.
摘要翻译：逻辑元件包括存储器元件，多路复用器和控制器。多路复用器被布置在包括最高级别的多路复用器的级别中，其中连接到存储器元件的输入端和连接到下一级到最高级复用器的输出的输出端和第一级多路复用器，其输入端连接到第二级多路复用器和至少一个输出。控制器连接到多路复用器。在第一操作模式中，所述控制确定所述第一级多路复用器的所述至少一个输出处的第一模式输出，并且在第二操作模式中，所述控制确定多路复用器的选定输出处的多个第二模式输出，第一级多路复用器。

40. 发明申请

US20070222477A1 FRACTURABLE LOOKUP TABLE AND LOGIC ELEMENT 有权
标题翻译：可折叠的表和逻辑元件
公开(公告)号：US20070222477A1
公开(公告)日：2007-09-27
申请号：US11753048
申请日：2007-05-24
申请人： David Lewis , Bruce Pedersen , Sinan Kaptanoglu , Andy Lee
发明人： David Lewis , Bruce Pedersen , Sinan Kaptanoglu , Andy Lee
IPC分类号： H03K19/177
CPC分类号： H03K19/17728 , H03K19/1737
摘要： A logic element includes memory elements, multiplexers, and controls. The multiplexers are arranged in levels including a highest level of multiplexes with inputs connected to the memory elements and outputs connected to inputs of a next-to-highest level of multiplexers and a first level of multiplexers with inputs connected to outputs of a second level of multiplexers and at least one output. The controls are connected to the multiplexers. In a first operational mode the controls determine a first-mode output at the at least one output of the first level of multiplexers, and in a second operational mode the controls determine a plurality of second-mode outputs at selected outputs of multiplexers not at the first level of multiplexers.
摘要翻译：逻辑元件包括存储器元件，多路复用器和控制器。多路复用器被布置成包括具有连接到存储器元件的输入的最高级复用的输出和连接到下一个到最高级多路复用器的输出的输出以及具有连接到第二级的多路复用器的输出的第一级多路复用器多路复用器和至少一个输出。控制器连接到多路复用器。在第一操作模式中，所述控制确定所述第一级多路复用器的所述至少一个输出处的第一模式输出，并且在第二操作模式中，所述控制确定多路复用器的选定输出处的多个第二模式输出，第一级多路复用器。

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