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1. 发明授权

US07419882B2 Alignment mark and alignment method for the fabrication of trench-capacitor dram devices 有权
标题翻译：用于制造沟槽电容器的对准标记和对准方法
公开(公告)号：US07419882B2
公开(公告)日：2008-09-02
申请号：US11160683
申请日：2005-07-05
申请人： Yuan-Hsun Wu , An-Hsiung Liu , Chiang-Lin Shih , Pei-Ing Lee , Hui-Min Mao , Lin-Chin Su
发明人： Yuan-Hsun Wu , An-Hsiung Liu , Chiang-Lin Shih , Pei-Ing Lee , Hui-Min Mao , Lin-Chin Su
IPC分类号： H01L21/20
CPC分类号： G03F9/7084 , G03F7/70633 , G03F9/708 , H01L23/544 , H01L27/1087 , H01L2223/54453 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： A small-size (w
摘要翻译：提出了与“k1工艺”结合的小尺寸（w <0.5微米）对准标记，其特别适用于需要高精度AA-DT对准的沟槽电容器DRAM器件的制造。利用“k1工艺”来蚀刻散布在对准标记沟槽中的多晶硅，并且在AA图案转印之前刷新沟槽轮廓，从而提高晶片对准精度和精度。

2. 发明申请

US20060234440A1 ALIGNMENT MARK AND ALIGNMENT METHOD FOR THE FABRICATION OF TRENCH-CAPACITOR DRAM DEVICES 有权
标题翻译：用于制造TRENCH-CAPACITOR DRAM器件的对准标记和对准方法
公开(公告)号：US20060234440A1
公开(公告)日：2006-10-19
申请号：US11160683
申请日：2005-07-05
申请人： Yuan-Hsun WU , An-Hsiung Liu , Chiang-Lin Shih , Pei-Ing Lee , Hui-Min Mao , Lin-Chin Su
发明人： Yuan-Hsun WU , An-Hsiung Liu , Chiang-Lin Shih , Pei-Ing Lee , Hui-Min Mao , Lin-Chin Su
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： G03F9/7084 , G03F7/70633 , G03F9/708 , H01L23/544 , H01L27/1087 , H01L2223/54453 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： A small-size (w
摘要翻译：提出了与“k1工艺”结合的小尺寸（w <0.5微米）对准标记，其特别适用于需要高精度AA-DT对准的沟槽电容器DRAM器件的制造。利用“k1工艺”来蚀刻散布在对准标记沟槽中的多晶硅，并且在AA图案转印之前刷新沟槽轮廓，从而提高晶片对准精度和精度。

3. 发明申请

US20070190736A1 OVERLAY ALIGNMENT MARK AND ALIGNMENT METHOD FOR THE FABRICATION OF TRENCH-CAPACITOR DRAM DEVICES 有权
标题翻译：覆盖电容器DRAM器件的覆盖对准标记和对准方法
公开(公告)号：US20070190736A1
公开(公告)日：2007-08-16
申请号：US11616849
申请日：2006-12-27
申请人： An-Hsiung Liu , Chiang-Lin Shih , Wen-Bin Wu , Hui-Min Mao , Lin-Chin Su , Pei-Ing Lee
发明人： An-Hsiung Liu , Chiang-Lin Shih , Wen-Bin Wu , Hui-Min Mao , Lin-Chin Su , Pei-Ing Lee
IPC分类号： H01L21/20
CPC分类号： H01L29/66181 , G03F7/70633 , G03F9/7076 , G03F9/708 , G03F9/7084 , H01L23/544 , H01L27/1087 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A small-size (w
摘要翻译：提出了与“k1工艺”结合的小尺寸（w <0.5微米）对准标记，其特别适用于制造需要高精度AA-DT和GC-DT重叠对准的沟槽电容器DRAM器件。利用“k1工艺”来蚀刻散布在对准标记沟槽中的多晶硅，并刷新沟槽轮廓，从而提高覆盖对准精度和精度。

4. 发明授权

US07723181B2 Overlay alignment mark and alignment method for the fabrication of trench-capacitor dram devices 有权
标题翻译：覆盖对准标记和对准方法，用于制造沟槽电容器电容器
公开(公告)号：US07723181B2
公开(公告)日：2010-05-25
申请号：US11616849
申请日：2006-12-27
申请人： An-Hsiung Liu , Chiang-Lin Shih , Wen-Bin Wu , Hui-Min Mao , Lin-Chin Su , Pei-Ing Lee
发明人： An-Hsiung Liu , Chiang-Lin Shih , Wen-Bin Wu , Hui-Min Mao , Lin-Chin Su , Pei-Ing Lee
IPC分类号： H01L21/8242
CPC分类号： H01L29/66181 , G03F7/70633 , G03F9/7076 , G03F9/708 , G03F9/7084 , H01L23/544 , H01L27/1087 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A small-size (w
摘要翻译：提出了与“k1工艺”结合的小尺寸（w <0.5微米）对准标记，其特别适用于制造需要高精度AA-DT和GC-DT重叠对准的沟槽电容器DRAM器件。利用“k1工艺”来蚀刻散布在对准标记沟槽中的多晶硅，并刷新沟槽轮廓，从而提高覆盖对准精度和精度。

5. 发明授权

US07285377B2 Fabrication method for a damascene bit line contact plug 有权
标题翻译：镶嵌位线接触插头的制造方法
公开(公告)号：US07285377B2
公开(公告)日：2007-10-23
申请号：US10715616
申请日：2003-11-18
申请人： Yi-Nan Chen , Jeng-Ping Lin , Chih-Ching Lin , Hui-Min Mao
发明人： Yi-Nan Chen , Jeng-Ping Lin , Chih-Ching Lin , Hui-Min Mao
IPC分类号： G03F7/00
CPC分类号： H01L21/76897 , H01L21/76885 , H01L27/105 , H01L27/1052 , H01L27/10888
摘要： A fabrication method for a damascene bit line contact plug. A semiconductor substrate has a first gate conductive structure, a second gate conductive structure and a source/drain region formed therebetween. A first conductive layer is formed in a space between the first gate conductive structure and the second gate conductive structure to be electrically connected to the source/drain region. An inter-layer dielectric with a planarized surface is formed to cover the first conductive layer, the first gate conductive structure, and the second gate conductive structure. A bit line contact hole is formed in the inter-layer dielectric to expose the top of the first conductive layer. A second conductive layer is formed in the bit line contact hole, in which the combination of the second conductive layer and the first conductive layer serves as a damascene bit line contact plug.
摘要翻译：镶嵌位线接触插头的制造方法。半导体衬底具有形成在其间的第一栅极导电结构，第二栅极导电结构和源极/漏极区。第一导电层形成在第一栅极导电结构和第二栅极导电结构之间的空间中，以电连接到源极/漏极区。形成具有平坦化表面的层间电介质以覆盖第一导电层，第一栅极导电结构和第二栅极导电结构。在层间电介质中形成位线接触孔，露出第一导电层的顶部。第二导电层形成在位线接触孔中，其中第二导电层和第一导电层的组合用作镶嵌位线接触插塞。

6. 发明授权

US07009236B2 Memory device with vertical transistors and deep trench capacitors and method of fabricating the same 有权
标题翻译：具有垂直晶体管和深沟槽电容器的存储器件及其制造方法
公开(公告)号：US07009236B2
公开(公告)日：2006-03-07
申请号：US10691173
申请日：2003-10-22
申请人： Yi-Nan Chen , Hui-Min Mao , Chih-Yuan Hsiao , Ming-Cheng Chang
发明人： Yi-Nan Chen , Hui-Min Mao , Chih-Yuan Hsiao , Ming-Cheng Chang
IPC分类号： H01L27/108
CPC分类号： H01L27/10864 , H01L27/10867
摘要： A memory device with vertical transistors and deep trench capacitors. The device includes a substrate containing at least one deep trench and a capacitor deposited in the lower portion of the deep trench. A conducting structure, having a first conductive layer and a second conductive layer, is deposited on the trench capacitor. A ring shaped insulator is deposited on the sidewall and between the substrate and the first conductive layer. The first conductive layer is surrounded by the ring shaped insulator, and the second conductive layer is deposited on the first conductive layer and the ring shaped insulator. A diffusion barrier between the second conductive layer and the substrate of the deep trench is deposited on one side of the sidewall of the deep trench. A TTO is deposited on the conducting structure. A control gate is deposited on the TTO.
摘要翻译：具有垂直晶体管和深沟槽电容器的存储器件。该器件包括含有至少一个深沟槽和沉积在深沟槽的下部的电容器的衬底。具有第一导电层和第二导电层的导电结构沉积在沟槽电容器上。环形绝缘体沉积在侧壁上以及衬底和第一导电层之间。第一导电层被环形绝缘体包围，并且第二导电层沉积在第一导电层和环形绝缘体上。在深沟槽的侧壁的一侧上沉积第二导电层和深沟槽的衬底之间的扩散阻挡层。 TTO沉积在导电结构上。控制门被存放在TTO上。

7. 发明授权

US07195975B2 Method of forming bit line contact via 有权
标题翻译：形成位线接触通孔的方法
公开(公告)号：US07195975B2
公开(公告)日：2007-03-27
申请号：US10714001
申请日：2003-11-14
申请人： Tzu-Ching Tsai , Yi-Nan Chen , Hui-Min Mao
发明人： Tzu-Ching Tsai , Yi-Nan Chen , Hui-Min Mao
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： H01L21/76897 , H01L21/76829 , H01L21/76895
摘要： A method of forming a bit line contact via. The method includes providing a substrate having a transistor with a gate electrode, drain region, and source region, forming a conductive layer overlying the drain region, conformally forming an insulating barrier layer overlying the substrate, blanketly forming a dielectric layer overlying the insulating barrier layer, and forming a via through the dielectric layer and insulating barrier layer, exposing the conductive layer.
摘要翻译：形成位线接触通孔的方法。该方法包括提供具有晶体管的衬底，该晶体管具有栅极，漏极区和源极区，形成覆盖漏极区的导电层，保形地形成覆盖衬底的绝缘阻挡层，覆盖在绝缘阻挡层上的绝缘层并且通过介电层和绝缘阻挡层形成通孔，暴露导电层。

8. 发明授权

US07064044B2 Contact etching utilizing multi-layer hard mask 有权
标题翻译：使用多层硬掩模进行接触蚀刻
公开(公告)号：US07064044B2
公开(公告)日：2006-06-20
申请号：US11019850
申请日：2004-12-21
申请人： Yi-Nan Chen , Hui-Min Mao
发明人： Yi-Nan Chen , Hui-Min Mao
IPC分类号： H01L21/76
CPC分类号： H01L21/31144 , G03F9/7076 , G03F9/708 , G03F9/7084 , H01L21/76802 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A method for forming contact holes using a multi-layer hard mask. A substrate with a device region and an alignment region having an opening therein to serve as an alignment mark is provided. A dielectric layer is formed overlying the substrate and fills the opening, followed by the multi-layer hard mask. The multi-layer hard mask over the opening is partially removed and that on the device region is patterned to form a plurality of holes therein and expose the underlying dielectric layer. The exposed dielectric layer on the device region is etched to form the plurality of contact holes therein.
摘要翻译：一种使用多层硬掩模形成接触孔的方法。提供了具有器件区域和其中具有开口的对准区域用作对准标记的衬底。形成覆盖在基板上的电介质层，并填充开口，接着是多层硬掩模。开口上的多层硬掩模被部分去除，并且在器件区域上被图案化以在其中形成多个孔并且暴露下面的介电层。在器件区域上暴露的介电层被蚀刻以在其中形成多个接触孔。

9. 发明授权

US06987322B2 Contact etching utilizing multi-layer hard mask 有权
公开(公告)号：US06987322B2
公开(公告)日：2006-01-17
申请号：US10923591
申请日：2004-08-20
申请人： Yi-Nan Chen , Hui-Min Mao
发明人： Yi-Nan Chen , Hui-Min Mao
IPC分类号： H01L23/48
CPC分类号： H01L21/31144 , G03F9/7076 , G03F9/708 , G03F9/7084 , H01L21/76802 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A method for forming contact holes using a multi-layer hard mask. A substrate with a device region and an alignment region having an opening therein to serve as an alignment mark is provided. A dielectric layer is formed overlying the substrate and fills the opening, followed by the multi-layer hard mask. The multi-layer hard mask over the opening is partially removed and that on the device region is patterned to form a plurality of holes therein and expose the underlying dielectric layer. The exposed dielectric layer on the device region is etched to form the plurality of contact holes therein.

10. 发明申请

US20050168740A1 Method of evaluating reticle pattern overlay registration 审中-公开
标题翻译：评估标线图案重叠注册的方法
公开(公告)号：US20050168740A1
公开(公告)日：2005-08-04
申请号：US11090643
申请日：2005-03-25
申请人： Wen-Bin Wu , Chih-Yuan Hsiao , Hui-Min Mao
发明人： Wen-Bin Wu , Chih-Yuan Hsiao , Hui-Min Mao
IPC分类号： G03F7/20 , G03F9/00 , G01B11/00 , G06F17/50
CPC分类号： G03F9/7019 , G03F7/70633 , G03F9/7011
摘要： A method for evaluating reticle registration between two reticle patterns. A wafer is defined and etched to form a first exposure pattern, by photolithography with a first reticle having a first reticle pattern thereon. A photoresist layer is formed over the wafer and defined as a second exposure pattern, by photolithography with a second reticle having a second reticle pattern thereon. A deviation value between the first and second exposure patterns is measured by a CD-SEM. The deviation value is calibrated according to the scaling degree and the overlay offset to obtain a registration data. The reticle registration between the two reticle patterns is evaluated based on the registration data.
摘要翻译：一种用于评估两个掩模版图案之间的掩模版配准的方法。通过用其上具有第一掩模版图案的第一掩模版通过光刻来限定和蚀刻晶片以形成第一曝光图案。在晶片上形成光致抗蚀剂层，并通过光刻法将其定义为第二曝光图案，其上具有第二掩模版图案的第二掩模版。通过CD-SEM测量第一和第二曝光图案之间的偏差值。根据缩放程度和覆盖偏移校正偏差值，以获得注册数据。基于登记数据评价两个掩模图案之间的掩模版登记。

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