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1. 发明申请

US20120042229A1 MULTI-STANDARD VITERBI PROCESSOR 有权
标题翻译：多标准VITERBI处理器
公开(公告)号：US20120042229A1
公开(公告)日：2012-02-16
申请号：US12853589
申请日：2010-08-10
申请人： Weihua Tang , Nur Engin , Frits Anthonie Steenhof , Marc Klaassen , Andries Pieter Hekstra , Sergei Valerjewitsch Sawitzki
发明人： Weihua Tang , Nur Engin , Frits Anthonie Steenhof , Marc Klaassen , Andries Pieter Hekstra , Sergei Valerjewitsch Sawitzki
IPC分类号： H03M13/03 , G06F11/10
CPC分类号： H03M13/4176 , H03M13/4107 , H03M13/4169 , H03M13/6519
摘要： Various embodiments relate to a multi-standard Viterbi decoder. Based on programmable values for constraint length, generator polynomials, and code rate, the multi-standard Viterbi decoder may adhere to a specific convolutional code standard. At a given time, the multi-standard Viterbi decoder may receive a variety of convolutional codes through a channel and may process them using various forms of the trace back method. Various embodiments include a branch metric unit and path metric unit that include a variety of sub-units that may or may not be active based on the value of the programmable value. Various embodiments also enable the multi-standard Viterbi decoder to handle different forms of convolutional codes, such as tail-biting codes. In some embodiments, the multi-standard Viterbi decoder may also process at least two convolutional codes concurrently.
摘要翻译：各种实施例涉及多标准维特比解码器。基于约束长度，生成多项式和码率的可编程值，多标准维特比解码器可以遵循特定的卷积码标准。在给定时间，多标准维特比解码器可以通过信道接收各种卷积码，并且可以使用各种形式的追溯方法来处理它们。各种实施例包括分支度量单位和路径度量单位，其包括可基于可编程值的值而可能或可以不是活动的各种子单元。各种实施例还使得多标准维特比解码器能够处理不同形式的卷积码，例如尾巴码。在一些实施例中，多标准维特比解码器也可以同时处理至少两个卷积码。

2. 发明申请

US20120042228A1 BITWISE RELIABILITY INDICATORS FROM SURVIVOR BITS IN VITERBI DECODERS 有权
标题翻译： VITERBI解码器中的生存位置的可比性可靠性指标
公开(公告)号：US20120042228A1
公开(公告)日：2012-02-16
申请号：US12856143
申请日：2010-08-13
申请人： Andries Pieter Hekstra , Nur Engin
发明人： Andries Pieter Hekstra , Nur Engin
IPC分类号： H03M13/07 , G06F11/10 , G06F11/07
CPC分类号： H04L1/0054 , H03M13/09 , H03M13/2936 , H03M13/373 , H03M13/4138 , H03M13/4161 , H04L1/0059 , H04L1/0065
摘要： Various embodiments relate to the production of erasure flags to indicate errors resulting from decoding of convolutional codes. A Viterbi decoder may use a register exchange method to produce a plurality of survivor codes. At a defined index, a majority vote may take place comparing values of bits in each of the survivor codes. This majority vote may involve obtaining both the quantity of high-order bits and the quantity of low-order bits and obtaining the difference of the two quantities. The absolute value of the difference of high-order bits to low-order bits may be compared to a defined threshold. When the absolute value difference is below the defined quantity, an erasure flag may be produced and associated with the bits of the defined index, indicating that they are eligible for erasure. In some embodiments, a Reed-Solomon decoder may use the erasure flag to target specific survivor bits or survivor bytes for error-correction through erasure.
摘要翻译：各种实施例涉及擦除标志的产生，以指示由卷积码的解码产生的错误。维特比解码器可以使用寄存器交换方法来产生多个幸存代码。在定义的索引中，可以进行多数投票来比较每个幸存者代码中的比特值。这个多数投票可以涉及获得高阶位数量和低位数量，并获得两个数量的差。可以将高阶位与低位的差的绝对值与定义的阈值进行比较。当绝对值差低于定义的数量时，可以产生擦除标志并与定义的索引的位相关联，表示它们符合擦除条件。在一些实施例中，Reed-Solomon解码器可以使用擦除标志来针对特定的幸存者比特或幸存者字节来进行错误校正。

3. 发明授权

US08433975B2 Bitwise reliability indicators from survivor bits in Viterbi decoders 有权
标题翻译：维特比解码器中存活位的逐位可靠性指标
公开(公告)号：US08433975B2
公开(公告)日：2013-04-30
申请号：US12856143
申请日：2010-08-13
申请人： Andries Pieter Hekstra , Nur Engin
发明人： Andries Pieter Hekstra , Nur Engin
IPC分类号： H03M13/00
CPC分类号： H04L1/0054 , H03M13/09 , H03M13/2936 , H03M13/373 , H03M13/4138 , H03M13/4161 , H04L1/0059 , H04L1/0065
摘要： Various embodiments relate to the production of erasure flags to indicate errors resulting from decoding of convolutional codes. A Viterbi decoder may use a register exchange method to produce a plurality of survivor codes. At a defined index, a majority vote may take place comparing values of bits in each of the survivor codes. This majority vote may involve obtaining both the quantity of high-order bits and the quantity of low-order bits and obtaining the difference of the two quantities. The absolute value of the difference of high-order bits to low-order bits may be compared to a defined threshold. When the absolute value difference is below the defined quantity, an erasure flag may be produced and associated with the bits of the defined index, indicating that they are eligible for erasure. In some embodiments, a Reed-Solomon decoder may use the erasure flag to target specific survivor bits or survivor bytes for error-correction through erasure.
摘要翻译：各种实施例涉及擦除标志的产生，以指示由卷积码的解码产生的错误。维特比解码器可以使用寄存器交换方法来产生多个幸存代码。在定义的索引中，可以进行多数投票来比较每个幸存者代码中的比特值。这个多数投票可以涉及获得高阶位数量和低位数量，并获得两个数量的差。可以将高阶位与低位的差的绝对值与定义的阈值进行比较。当绝对值差低于定义的数量时，可以产生擦除标志并与定义的索引的位相关联，表示它们符合擦除条件。在一些实施例中，Reed-Solomon解码器可以使用擦除标志来针对特定的幸存者比特或幸存者字节来进行错误校正。

4. 发明授权

US08904266B2 Multi-standard viterbi processor 有权
标题翻译：多标准维特比处理器
公开(公告)号：US08904266B2
公开(公告)日：2014-12-02
申请号：US12853589
申请日：2010-08-10
申请人： Weihua Tang , Nur Engin , Frits Anthonie Steenhof , Marc Klaassen , Andries Pieter Hekstra , Sergie Valerjewitsch Sawitzki
发明人： Weihua Tang , Nur Engin , Frits Anthonie Steenhof , Marc Klaassen , Andries Pieter Hekstra , Sergie Valerjewitsch Sawitzki
IPC分类号： H03M13/17 , H03M13/00 , H03M13/41
CPC分类号： H03M13/4176 , H03M13/4107 , H03M13/4169 , H03M13/6519
摘要： Various embodiments relate to a multi-standard Viterbi decoder. Based on programmable values for constraint length, generator polynomials, and code rate, the multi-standard Viterbi decoder may adhere to a specific convolutional code standard. At a given time, the multi-standard Viterbi decoder may receive a variety of convolutional codes through a channel and may process them using various forms of the trace back method. Various embodiments include a branch metric unit and path metric unit that include a variety of sub-units that may or may not be active based on the value of the programmable value. Various embodiments also enable the multi-standard Viterbi decoder to handle different forms of convolutional codes, such as tail-biting codes. In some embodiments, the multi-standard Viterbi decoder may also process at least two convolutional codes concurrently.
摘要翻译：各种实施例涉及多标准维特比解码器。基于约束长度，生成多项式和码率的可编程值，多标准维特比解码器可以遵循特定的卷积码标准。在给定时间，多标准维特比解码器可以通过信道接收各种卷积码，并且可以使用各种形式的追溯方法来处理它们。各种实施例包括分支度量单位和路径度量单位，其包括可基于可编程值的值而可能或可以不是活动的各种子单元。各种实施例还使得多标准维特比解码器能够处理不同形式的卷积码，例如尾巴码。在一些实施例中，多标准维特比解码器也可以同时处理至少两个卷积码。

5. 发明授权

US08253353B2 Driving a light source 有权
标题翻译：驾驶光源
公开(公告)号：US08253353B2
公开(公告)日：2012-08-28
申请号：US12668034
申请日：2008-07-14
申请人： Constant Paul Marie Jozef Baggen , Andries Pieter Hekstra , Johan Paul Marie Gerard Linnartz
发明人： Constant Paul Marie Jozef Baggen , Andries Pieter Hekstra , Johan Paul Marie Gerard Linnartz
IPC分类号： H05B37/02
CPC分类号： H05B37/0272 , H04B10/1141 , H04B10/116 , H04L25/4904 , H05B37/0245 , H05B37/0254
摘要： A method for driving a light source (11, 12, 13) is described, wherein the light source is alternately switched ON and OFF in an ON/OFF pattern, wherein the duty cycle of the ON/OFF pattern is varied to vary the average light intensity of the light source, and wherein the shape of the ON/OFF pattern is varied to transmit data. Thus, a control signal for the light source comprises data information as well as duty cycle information. The duty cycle is varied within a range from almost zero to almost 100%, and data is varied and transmitted without affecting the duty cycle.
摘要翻译：描述了用于驱动光源（11,12,13）的方法，其中在ON / OFF模式中光源被交替地接通和断开，其中ON / OFF模式的占空比被改变以改变平均值光源的光强度，并且其中ON / OFF图案的形状被改变以传输数据。因此，用于光源的控制信号包括数据信息以及占空比信息。占空比在几乎零到几乎100％的范围内变化，并且数据被变化和传输而不影响占空比。

6. 发明授权

US07849377B2 SISO decoder with sub-block processing and sub-block based stopping criterion 有权
标题翻译： SISO解码器采用子块处理和基于子块的停止标准
公开(公告)号：US07849377B2
公开(公告)日：2010-12-07
申请号：US10596543
申请日：2004-12-08
申请人： Andries Pieter Hekstra , Johannus Theodorus Matheus Hubertus Dielissen
发明人： Andries Pieter Hekstra , Johannus Theodorus Matheus Hubertus Dielissen
IPC分类号： H03M13/00
CPC分类号： H03M13/3905 , H03M13/2975 , H03M13/3972
摘要： The present invention relates to SISO decoder for iteratively decoding a block of received information symbols (r), in particular for use in a turbo decoder, said block being divided into a number of windows of information symbols. In order to achieve a significant reduction of power consumption a SISO decoder is proposed comprising at least one SISO decoding unit (17, 21) for SISO decoding of the received information symbols (r) of a window, wherein a stopping criterion is applied to each window. This allows to abort iterative decoding for each window individually once convergence of decoding is determined by marking a window or sub-block inactive (17,23). An inactive window is no longer SISO decoded in subsequent iterations.
摘要翻译：本发明涉及用于对接收的信息符号（r）的块进行迭代解码的SISO解码器，特别是在turbo解码器中使用，所述块被划分成多个信息符号窗口。为了实现功耗的显着降低，提出了一种SISO解码器，其包括至少一个SISO解码单元（17,21），用于对窗口的接收信息符号（r）进行SISO解码，其中停止标准被应用于每个窗口。这允许一旦通过标记窗口或子块无效来确定解码收敛，则每个窗口单独中止迭代解码（17,23）。在随后的迭代中，不活动的窗口不再被SISO解码。

7. 发明申请

US20090015446A1 Coder and a Method of Coding For Codes With a Parity-Complementary Word Assignment Having a Constraint of D1=,R=2 有权
标题翻译：编码器和编码代码的方法，其中具有约束D1 =，R = 2的奇偶互补字分配
公开(公告)号：US20090015446A1
公开(公告)日：2009-01-15
申请号：US12097570
申请日：2006-12-08
申请人： Willem Marie Julia Marcel Coene , Andries Pieter Hekstra , Hiroyuki Yamagishi , Makoto Noda
发明人： Willem Marie Julia Marcel Coene , Andries Pieter Hekstra , Hiroyuki Yamagishi , Makoto Noda
IPC分类号： H03M7/00
CPC分类号： G11B20/1426 , G11B20/10055 , G11B20/10296 , G11B2020/1453 , G11B2020/1457 , H03M5/145 , H03M7/40 , H03M13/29 , H03M13/31 , H03M13/3761 , H03M13/3972 , H03M13/41
摘要： Presently known d=1 codes have long trains consisting of consecutive 2T runs and an overall high frequency of occurrence of the shortest 2T runs that reduce the performance of the bit detector By using a code with an MTR constraint of 2 an improvement in the bit detection is achieved. A code constructed in a systematic way that provides an MTR constraint of 2 is presented. A variation of such a code is disclosed where one sub-code is used, where coding states are divided into coding classes and where code words are divided into code word types. Then, for a given sub-code, an code word of type t can be concatenated with an code word of the next sub-code if said subsequent code word of said next sub-code belongs to one of coding states of the coding class with index Tmax+1 t. In the code according to the invention the overall code has the property that the respective channel bit sequences that are encoded from the same message-bit sequence, starting from any possible state of the finite-state-machine, for each of the two values of a DC-control bit, that is part of a given user word have opposite parities for the sequences generated from the starting state up to the state where both encoder paths merge. For the case that the encoder paths do not merge, there is no such constraint. Finally, a new d=1, k=10 sliding-block decodable RLL code is disclosed with the following properties: (i) it has an r=2 constraint which is the lowest MTR value that is compatible with a rate R=⅔; (ii) it enables practical SISO-RLL decoding because of its compact 2-to-3 mapping; and (iii) the new code uses a parity-complementary word assignment4 (PCWA) for DC-control.
摘要翻译：目前已知的d = 1代码具有由连续的2T运行组成的长列，并且总体出现最短的2T运行的频率，从而降低位检测器的性能通过使用MTR约束为2的代码，改进了位检测已完成。提出了一种以系统方式构建的代码，其提供MTR约束为2的代码。公开了这样的代码的变型，其中使用一个子代码，其中编码状态被分为编码类别以及代码字被分成代码字类型。然后，对于给定子码，如果所述下一子码的所述后续码字属于编码类的编码状态之一，则可以将类型t的码字与下一子码的码字连接，指数Tmax + 1t。在根据本发明的代码中，总代码具有以下特性：从相同消息比特序列编码的各个信道比特序列，从有限状态机的任何可能状态开始，对于两个值的作为给定用户字的一部分的DC控制位对于从起始状态直到两个编码器路径合并的状态产生的序列具有相反的奇偶校验。对于编码器路径不合并的情况，没有这样的限制。最后，公开了一种新的d = 1，k = 10滑块可解码的RLL码，具有以下特性：（i）它具有r = 2约束，其是与速率R = 2 / 3; （ii）由于其紧凑的2对3映射，它使实用的SISO-RLL解码成为可能; 和（iii）新的代码使用奇偶互补字分配4（PCWA）进行DC控制。

8. 发明申请

US20080317140A1 Method of Converting a User Bitstream Into Coded Bitstream, Method for Detecting a Synchronization Pattern in a Signal, a Record Carier, a Signal, a Recording Device and a Playback Device 审中-公开
标题翻译：将用户比特流转换为编码比特流的方法，用于检测信号中的同步模式的方法，记录卡尔，信号，记录装置和播放装置
公开(公告)号：US20080317140A1
公开(公告)日：2008-12-25
申请号：US11575138
申请日：2005-09-12
申请人： Willem Marie Julia Marcel Coene , Andries Pieter Hekstra , Alexander Padiy
发明人： Willem Marie Julia Marcel Coene , Andries Pieter Hekstra , Alexander Padiy
IPC分类号： H04B14/04
CPC分类号： H03M5/145 , G11B20/10009 , G11B20/1426 , G11B27/105 , G11B27/3027 , G11B2020/1453
摘要： This ID proposes synchronization patterns for RLL codes with a (repeated) minimum transition run (RMTR) constraint, where the synchronization pattern comprises a synchronization pattern-body that contains a characteristic bit-pattern that represents a violation of the RMTR constraint. Using a violation of the RMTR constraint allows for short synchronization patterns.
摘要翻译：该ID提出具有（重复的）最小过渡运行（RMTR）约束的RLL代码的同步模式，其中同步模式包括包含表示违反RMTR约束的特征位模式的同步模式体。使用违反RMTR约束允许短同步模式。

9. 发明授权

US07185263B2 Method of joint decoding of possibly mutilated code words 失效
标题翻译：联合解码可能残缺码字的方法
公开(公告)号：US07185263B2
公开(公告)日：2007-02-27
申请号：US10506375
申请日：2003-02-14
申请人： Andries Pieter Hekstra , Constant Paul Marie Jozef Baggen , Ludovicus Marinus Gerardus Maria Tolhuizen
发明人： Andries Pieter Hekstra , Constant Paul Marie Jozef Baggen , Ludovicus Marinus Gerardus Maria Tolhuizen
IPC分类号： H03M13/00
CPC分类号： H03M13/37 , G11B20/18
摘要： A method of decoding possibly mutilated code words (r) of a code (C) includes decoding the differences (D) of a number (L−1) of pairs of possibly mutilated code words (rib, ri+1) to obtain estimates (u, v) for the differences of the corresponding pairs of code words (ci, ci+1), combining the estimates (u, v) to obtain a number (L) of at least two corrupted versions (wj) of a particular code word (c), forming a code vector (z) from the number (L) of corrupted versions (wj) of the particular code word (c) in each coordinate, decoding the code vector (z) to a decoded code word (c′) in the code (C), and using the generator matrix (G) to obtain the information word (m) and the address word (a) embedded in the decoded code word (c′).
摘要翻译：解码代码（C）的可能残缺代码字（r）的方法包括解码可能残缺的代码字对（L-1）的数量（L-1）的数量（L-1）（i，i + 1），以获得对应的代码字对（c i，i i，i i + 1）的差的估计（u，v）将所述估计（u，v）组合以获得特定码字（c）的至少两个损坏版本（w SUB）的数目（L），形成码矢量（ z）从每个坐标中的特定码字（c）的损坏版本号（L）的数量（L）开始，将码矢量（z）解码为解码码字（c'），在代码（C）中，并且使用生成矩阵（G）来获得嵌入在解码码字（c'）中的信息字（m）和地址字（a）。

10. 发明授权

US6042006A Authentication system wherein definition signals of two devices are altered, communicated between the two devices, and compared 失效
标题翻译：验证系统，其中两个设备的定义信号被改变，在两个设备之间进行通信并进行比较
公开(公告)号：US6042006A
公开(公告)日：2000-03-28
申请号：US915015
申请日：1997-08-20
申请人： Johan Van Tilburg , Andries Pieter Hekstra
发明人： Johan Van Tilburg , Andries Pieter Hekstra
IPC分类号： G07F7/10 , H04L9/00 , G06K5/00
CPC分类号： G07F7/1008 , G06Q20/341 , G06Q20/4012 , G06Q20/40975
摘要： An authentication system having a first device and a second device between which signals may be communicated. The first device includes a first memory for storing a definition signal and the first device generates a first signal to be communicated to the second device. The first device also generates a first alteration signal, and introduces an alteration into a first section of the definition signal stored in the first memory in accordance with the first alteration signal. The second device includes a second memory for storing the definition signal, and generates, in response to a receipt of the first signal, a second signal to be communicated to the first device. The second signal includes a second section of the definition signal stored in the second memory, and the second device also generates a second alteration signal and introduces an alteration into a third section of the definition signal stored in the second memory in accordance with the second alteration signal. In addition, the first device compares the second section of the definition signal in the second signal originating from the second device with a corresponding section of the definition signal stored in the first memory, and introduces the alteration into the first section of the definition signal stored in the first memory in accordance with a comparison result. The first and third sections, moreover, are corresponding sections of the definition signals stored in the first and second memories, respectively.
摘要翻译：一种具有第一设备和第二设备的认证系统，在该设备之间可以传送信号。第一设备包括用于存储定义信号的第一存储器，并且第一设备生成要传送到第二设备的第一信号。第一设备还产生第一改变信号，并且根据第一改变信号将改变引入存储在第一存储器中的定义信号的第一部分。第二装置包括用于存储定义信号的第二存储器，并且响应于第一信号的接收而产生要传送到第一装置的第二信号。第二信号包括存储在第二存储器中的定义信号的第二部分，并且第二装置还产生第二改变信号，并根据第二变更将改变引入存储在第二存储器中的定义信号的第三部分信号。此外，第一装置将来自第二装置的第二信号中的定义信号的第二部分与存储在第一存储器中的定义信号的相应部分进行比较，并将该改变引入存储的定义信号的第一部分在第一个内存中按照比较结果。此外，第一和第三部分分别是存储在第一和第二存储器中的定义信号的相应部分。

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