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1. 发明授权

US08904266B2 Multi-standard viterbi processor 有权
标题翻译：多标准维特比处理器
公开(公告)号：US08904266B2
公开(公告)日：2014-12-02
申请号：US12853589
申请日：2010-08-10
申请人： Weihua Tang , Nur Engin , Frits Anthonie Steenhof , Marc Klaassen , Andries Pieter Hekstra , Sergie Valerjewitsch Sawitzki
发明人： Weihua Tang , Nur Engin , Frits Anthonie Steenhof , Marc Klaassen , Andries Pieter Hekstra , Sergie Valerjewitsch Sawitzki
IPC分类号： H03M13/17 , H03M13/00 , H03M13/41
CPC分类号： H03M13/4176 , H03M13/4107 , H03M13/4169 , H03M13/6519
摘要： Various embodiments relate to a multi-standard Viterbi decoder. Based on programmable values for constraint length, generator polynomials, and code rate, the multi-standard Viterbi decoder may adhere to a specific convolutional code standard. At a given time, the multi-standard Viterbi decoder may receive a variety of convolutional codes through a channel and may process them using various forms of the trace back method. Various embodiments include a branch metric unit and path metric unit that include a variety of sub-units that may or may not be active based on the value of the programmable value. Various embodiments also enable the multi-standard Viterbi decoder to handle different forms of convolutional codes, such as tail-biting codes. In some embodiments, the multi-standard Viterbi decoder may also process at least two convolutional codes concurrently.
摘要翻译：各种实施例涉及多标准维特比解码器。基于约束长度，生成多项式和码率的可编程值，多标准维特比解码器可以遵循特定的卷积码标准。在给定时间，多标准维特比解码器可以通过信道接收各种卷积码，并且可以使用各种形式的追溯方法来处理它们。各种实施例包括分支度量单位和路径度量单位，其包括可基于可编程值的值而可能或可以不是活动的各种子单元。各种实施例还使得多标准维特比解码器能够处理不同形式的卷积码，例如尾巴码。在一些实施例中，多标准维特比解码器也可以同时处理至少两个卷积码。

2. 发明申请

US20120042229A1 MULTI-STANDARD VITERBI PROCESSOR 有权
标题翻译：多标准VITERBI处理器
公开(公告)号：US20120042229A1
公开(公告)日：2012-02-16
申请号：US12853589
申请日：2010-08-10
申请人： Weihua Tang , Nur Engin , Frits Anthonie Steenhof , Marc Klaassen , Andries Pieter Hekstra , Sergei Valerjewitsch Sawitzki
发明人： Weihua Tang , Nur Engin , Frits Anthonie Steenhof , Marc Klaassen , Andries Pieter Hekstra , Sergei Valerjewitsch Sawitzki
IPC分类号： H03M13/03 , G06F11/10
CPC分类号： H03M13/4176 , H03M13/4107 , H03M13/4169 , H03M13/6519
摘要： Various embodiments relate to a multi-standard Viterbi decoder. Based on programmable values for constraint length, generator polynomials, and code rate, the multi-standard Viterbi decoder may adhere to a specific convolutional code standard. At a given time, the multi-standard Viterbi decoder may receive a variety of convolutional codes through a channel and may process them using various forms of the trace back method. Various embodiments include a branch metric unit and path metric unit that include a variety of sub-units that may or may not be active based on the value of the programmable value. Various embodiments also enable the multi-standard Viterbi decoder to handle different forms of convolutional codes, such as tail-biting codes. In some embodiments, the multi-standard Viterbi decoder may also process at least two convolutional codes concurrently.
摘要翻译：各种实施例涉及多标准维特比解码器。基于约束长度，生成多项式和码率的可编程值，多标准维特比解码器可以遵循特定的卷积码标准。在给定时间，多标准维特比解码器可以通过信道接收各种卷积码，并且可以使用各种形式的追溯方法来处理它们。各种实施例包括分支度量单位和路径度量单位，其包括可基于可编程值的值而可能或可以不是活动的各种子单元。各种实施例还使得多标准维特比解码器能够处理不同形式的卷积码，例如尾巴码。在一些实施例中，多标准维特比解码器也可以同时处理至少两个卷积码。

3. 发明申请

US20120042228A1 BITWISE RELIABILITY INDICATORS FROM SURVIVOR BITS IN VITERBI DECODERS 有权
标题翻译： VITERBI解码器中的生存位置的可比性可靠性指标
公开(公告)号：US20120042228A1
公开(公告)日：2012-02-16
申请号：US12856143
申请日：2010-08-13
申请人： Andries Pieter Hekstra , Nur Engin
发明人： Andries Pieter Hekstra , Nur Engin
IPC分类号： H03M13/07 , G06F11/10 , G06F11/07
CPC分类号： H04L1/0054 , H03M13/09 , H03M13/2936 , H03M13/373 , H03M13/4138 , H03M13/4161 , H04L1/0059 , H04L1/0065
摘要： Various embodiments relate to the production of erasure flags to indicate errors resulting from decoding of convolutional codes. A Viterbi decoder may use a register exchange method to produce a plurality of survivor codes. At a defined index, a majority vote may take place comparing values of bits in each of the survivor codes. This majority vote may involve obtaining both the quantity of high-order bits and the quantity of low-order bits and obtaining the difference of the two quantities. The absolute value of the difference of high-order bits to low-order bits may be compared to a defined threshold. When the absolute value difference is below the defined quantity, an erasure flag may be produced and associated with the bits of the defined index, indicating that they are eligible for erasure. In some embodiments, a Reed-Solomon decoder may use the erasure flag to target specific survivor bits or survivor bytes for error-correction through erasure.
摘要翻译：各种实施例涉及擦除标志的产生，以指示由卷积码的解码产生的错误。维特比解码器可以使用寄存器交换方法来产生多个幸存代码。在定义的索引中，可以进行多数投票来比较每个幸存者代码中的比特值。这个多数投票可以涉及获得高阶位数量和低位数量，并获得两个数量的差。可以将高阶位与低位的差的绝对值与定义的阈值进行比较。当绝对值差低于定义的数量时，可以产生擦除标志并与定义的索引的位相关联，表示它们符合擦除条件。在一些实施例中，Reed-Solomon解码器可以使用擦除标志来针对特定的幸存者比特或幸存者字节来进行错误校正。

4. 发明授权

US08433975B2 Bitwise reliability indicators from survivor bits in Viterbi decoders 有权
标题翻译：维特比解码器中存活位的逐位可靠性指标
公开(公告)号：US08433975B2
公开(公告)日：2013-04-30
申请号：US12856143
申请日：2010-08-13
申请人： Andries Pieter Hekstra , Nur Engin
发明人： Andries Pieter Hekstra , Nur Engin
IPC分类号： H03M13/00
CPC分类号： H04L1/0054 , H03M13/09 , H03M13/2936 , H03M13/373 , H03M13/4138 , H03M13/4161 , H04L1/0059 , H04L1/0065
摘要： Various embodiments relate to the production of erasure flags to indicate errors resulting from decoding of convolutional codes. A Viterbi decoder may use a register exchange method to produce a plurality of survivor codes. At a defined index, a majority vote may take place comparing values of bits in each of the survivor codes. This majority vote may involve obtaining both the quantity of high-order bits and the quantity of low-order bits and obtaining the difference of the two quantities. The absolute value of the difference of high-order bits to low-order bits may be compared to a defined threshold. When the absolute value difference is below the defined quantity, an erasure flag may be produced and associated with the bits of the defined index, indicating that they are eligible for erasure. In some embodiments, a Reed-Solomon decoder may use the erasure flag to target specific survivor bits or survivor bytes for error-correction through erasure.
摘要翻译：各种实施例涉及擦除标志的产生，以指示由卷积码的解码产生的错误。维特比解码器可以使用寄存器交换方法来产生多个幸存代码。在定义的索引中，可以进行多数投票来比较每个幸存者代码中的比特值。这个多数投票可以涉及获得高阶位数量和低位数量，并获得两个数量的差。可以将高阶位与低位的差的绝对值与定义的阈值进行比较。当绝对值差低于定义的数量时，可以产生擦除标志并与定义的索引的位相关联，表示它们符合擦除条件。在一些实施例中，Reed-Solomon解码器可以使用擦除标志来针对特定的幸存者比特或幸存者字节来进行错误校正。

5. 发明申请

US20110161787A1 POWER-REDUCED PRELIMINARY DECODED BITS IN VITERBI DECODERS 有权
标题翻译： VITERBI解码器中的功率降低的初步解码器
公开(公告)号：US20110161787A1
公开(公告)日：2011-06-30
申请号：US12647885
申请日：2009-12-28
申请人： Andries Pieter Hekstra , Weihua Tang
发明人： Andries Pieter Hekstra , Weihua Tang
IPC分类号： H03M13/23 , G06F11/10 , H04L23/02
CPC分类号： H03M13/4184
摘要： Various embodiments relate to a storage unit and a related method in a Viterbi decoder for decoding a binary convolutional code with power efficiency. A storage unit for storing survivor paths may use a register exchange method to append additional information received from an add-compare-select unit onto the end of the survivor path. An exemplary method produces a prediction path after a specified depth in the survivor path processing history and subtracts the prediction path from the survivor path. This may cause a majority of bits that comprise the survivor path to be converted to a low-energy bit, such as a logical “0”. During subsequent copies of a differential survivor path using the register exchange method, less energy is consumed when copying the entire survivor path, as a majority of the bits in the survivor paths are a logical “0”.
摘要翻译：各种实施例涉及维特比解码器中的存储单元和相关方法，用于以功率效率对二进制卷积码进行解码。用于存储幸存路径的存储单元可以使用寄存器交换方法将从加法比较选择单元接收到的附加信息附加到幸存路径的末端。示例性方法在幸存路径处理历史中的指定深度之后产生预测路径，并从幸存路径中减去预测路径。这可能导致构成幸存者路径的大多数位被转换为低能量位，例如逻辑“0”。在使用寄存器交换方法的差分幸存者路径的随后复制期间，当复制整个幸存者路径时消耗较少的能量，因为幸存路径中的大多数位是逻辑“0”。

6. 发明授权

US08566683B2 Power-reduced preliminary decoded bits in viterbi decoders 有权
标题翻译：维特比解码器中功耗降低的初步解码位
公开(公告)号：US08566683B2
公开(公告)日：2013-10-22
申请号：US12647885
申请日：2009-12-28
申请人： Andries Pieter Hekstra , Weihua Tang
发明人： Andries Pieter Hekstra , Weihua Tang
IPC分类号： H03M13/03
CPC分类号： H03M13/4184
摘要： Various embodiments relate to a storage unit and a related method in a Viterbi decoder for decoding a binary convolutional code with power efficiency. A storage unit for storing survivor paths may use a register exchange method to append additional information received from an add-compare-select unit onto the end of the survivor path. An exemplary method produces a prediction path after a specified depth in the survivor path processing history and subtracts the prediction path from the survivor path. This may cause a majority of bits that comprise the survivor path to be converted to a low-energy bit, such as a logical “0”. During subsequent copies of a differential survivor path using the register exchange method, less energy is consumed when copying the entire survivor path, as a majority of the bits in the survivor paths are a logical “0”.
摘要翻译：各种实施例涉及维特比解码器中的存储单元和相关方法，用于以功率效率对二进制卷积码进行解码。用于存储幸存路径的存储单元可以使用寄存器交换方法将从加法比较选择单元接收到的附加信息附加到幸存路径的末端。示例性方法在幸存路径处理历史中的指定深度之后产生预测路径，并从幸存路径中减去预测路径。这可能导致构成幸存者路径的大多数位被转换为低能量位，例如逻辑“0”。在使用寄存器交换方法的差分幸存者路径的随后复制期间，当复制整个幸存者路径时消耗较少的能量，因为幸存路径中的大多数位是逻辑“0”。

7. 发明授权

US08253353B2 Driving a light source 有权
标题翻译：驾驶光源
公开(公告)号：US08253353B2
公开(公告)日：2012-08-28
申请号：US12668034
申请日：2008-07-14
申请人： Constant Paul Marie Jozef Baggen , Andries Pieter Hekstra , Johan Paul Marie Gerard Linnartz
发明人： Constant Paul Marie Jozef Baggen , Andries Pieter Hekstra , Johan Paul Marie Gerard Linnartz
IPC分类号： H05B37/02
CPC分类号： H05B37/0272 , H04B10/1141 , H04B10/116 , H04L25/4904 , H05B37/0245 , H05B37/0254
摘要： A method for driving a light source (11, 12, 13) is described, wherein the light source is alternately switched ON and OFF in an ON/OFF pattern, wherein the duty cycle of the ON/OFF pattern is varied to vary the average light intensity of the light source, and wherein the shape of the ON/OFF pattern is varied to transmit data. Thus, a control signal for the light source comprises data information as well as duty cycle information. The duty cycle is varied within a range from almost zero to almost 100%, and data is varied and transmitted without affecting the duty cycle.
摘要翻译：描述了用于驱动光源（11,12,13）的方法，其中在ON / OFF模式中光源被交替地接通和断开，其中ON / OFF模式的占空比被改变以改变平均值光源的光强度，并且其中ON / OFF图案的形状被改变以传输数据。因此，用于光源的控制信号包括数据信息以及占空比信息。占空比在几乎零到几乎100％的范围内变化，并且数据被变化和传输而不影响占空比。

8. 发明授权

US07849377B2 SISO decoder with sub-block processing and sub-block based stopping criterion 有权
标题翻译： SISO解码器采用子块处理和基于子块的停止标准
公开(公告)号：US07849377B2
公开(公告)日：2010-12-07
申请号：US10596543
申请日：2004-12-08
申请人： Andries Pieter Hekstra , Johannus Theodorus Matheus Hubertus Dielissen
发明人： Andries Pieter Hekstra , Johannus Theodorus Matheus Hubertus Dielissen
IPC分类号： H03M13/00
CPC分类号： H03M13/3905 , H03M13/2975 , H03M13/3972
摘要： The present invention relates to SISO decoder for iteratively decoding a block of received information symbols (r), in particular for use in a turbo decoder, said block being divided into a number of windows of information symbols. In order to achieve a significant reduction of power consumption a SISO decoder is proposed comprising at least one SISO decoding unit (17, 21) for SISO decoding of the received information symbols (r) of a window, wherein a stopping criterion is applied to each window. This allows to abort iterative decoding for each window individually once convergence of decoding is determined by marking a window or sub-block inactive (17,23). An inactive window is no longer SISO decoded in subsequent iterations.
摘要翻译：本发明涉及用于对接收的信息符号（r）的块进行迭代解码的SISO解码器，特别是在turbo解码器中使用，所述块被划分成多个信息符号窗口。为了实现功耗的显着降低，提出了一种SISO解码器，其包括至少一个SISO解码单元（17,21），用于对窗口的接收信息符号（r）进行SISO解码，其中停止标准被应用于每个窗口。这允许一旦通过标记窗口或子块无效来确定解码收敛，则每个窗口单独中止迭代解码（17,23）。在随后的迭代中，不活动的窗口不再被SISO解码。

9. 发明申请

US20090015446A1 Coder and a Method of Coding For Codes With a Parity-Complementary Word Assignment Having a Constraint of D1=,R=2 有权
标题翻译：编码器和编码代码的方法，其中具有约束D1 =，R = 2的奇偶互补字分配
公开(公告)号：US20090015446A1
公开(公告)日：2009-01-15
申请号：US12097570
申请日：2006-12-08
申请人： Willem Marie Julia Marcel Coene , Andries Pieter Hekstra , Hiroyuki Yamagishi , Makoto Noda
发明人： Willem Marie Julia Marcel Coene , Andries Pieter Hekstra , Hiroyuki Yamagishi , Makoto Noda
IPC分类号： H03M7/00
CPC分类号： G11B20/1426 , G11B20/10055 , G11B20/10296 , G11B2020/1453 , G11B2020/1457 , H03M5/145 , H03M7/40 , H03M13/29 , H03M13/31 , H03M13/3761 , H03M13/3972 , H03M13/41
摘要： Presently known d=1 codes have long trains consisting of consecutive 2T runs and an overall high frequency of occurrence of the shortest 2T runs that reduce the performance of the bit detector By using a code with an MTR constraint of 2 an improvement in the bit detection is achieved. A code constructed in a systematic way that provides an MTR constraint of 2 is presented. A variation of such a code is disclosed where one sub-code is used, where coding states are divided into coding classes and where code words are divided into code word types. Then, for a given sub-code, an code word of type t can be concatenated with an code word of the next sub-code if said subsequent code word of said next sub-code belongs to one of coding states of the coding class with index Tmax+1 t. In the code according to the invention the overall code has the property that the respective channel bit sequences that are encoded from the same message-bit sequence, starting from any possible state of the finite-state-machine, for each of the two values of a DC-control bit, that is part of a given user word have opposite parities for the sequences generated from the starting state up to the state where both encoder paths merge. For the case that the encoder paths do not merge, there is no such constraint. Finally, a new d=1, k=10 sliding-block decodable RLL code is disclosed with the following properties: (i) it has an r=2 constraint which is the lowest MTR value that is compatible with a rate R=⅔; (ii) it enables practical SISO-RLL decoding because of its compact 2-to-3 mapping; and (iii) the new code uses a parity-complementary word assignment4 (PCWA) for DC-control.
摘要翻译：目前已知的d = 1代码具有由连续的2T运行组成的长列，并且总体出现最短的2T运行的频率，从而降低位检测器的性能通过使用MTR约束为2的代码，改进了位检测已完成。提出了一种以系统方式构建的代码，其提供MTR约束为2的代码。公开了这样的代码的变型，其中使用一个子代码，其中编码状态被分为编码类别以及代码字被分成代码字类型。然后，对于给定子码，如果所述下一子码的所述后续码字属于编码类的编码状态之一，则可以将类型t的码字与下一子码的码字连接，指数Tmax + 1t。在根据本发明的代码中，总代码具有以下特性：从相同消息比特序列编码的各个信道比特序列，从有限状态机的任何可能状态开始，对于两个值的作为给定用户字的一部分的DC控制位对于从起始状态直到两个编码器路径合并的状态产生的序列具有相反的奇偶校验。对于编码器路径不合并的情况，没有这样的限制。最后，公开了一种新的d = 1，k = 10滑块可解码的RLL码，具有以下特性：（i）它具有r = 2约束，其是与速率R = 2 / 3; （ii）由于其紧凑的2对3映射，它使实用的SISO-RLL解码成为可能; 和（iii）新的代码使用奇偶互补字分配4（PCWA）进行DC控制。

10. 发明申请

US20080317140A1 Method of Converting a User Bitstream Into Coded Bitstream, Method for Detecting a Synchronization Pattern in a Signal, a Record Carier, a Signal, a Recording Device and a Playback Device 审中-公开
标题翻译：将用户比特流转换为编码比特流的方法，用于检测信号中的同步模式的方法，记录卡尔，信号，记录装置和播放装置
公开(公告)号：US20080317140A1
公开(公告)日：2008-12-25
申请号：US11575138
申请日：2005-09-12
申请人： Willem Marie Julia Marcel Coene , Andries Pieter Hekstra , Alexander Padiy
发明人： Willem Marie Julia Marcel Coene , Andries Pieter Hekstra , Alexander Padiy
IPC分类号： H04B14/04
CPC分类号： H03M5/145 , G11B20/10009 , G11B20/1426 , G11B27/105 , G11B27/3027 , G11B2020/1453
摘要： This ID proposes synchronization patterns for RLL codes with a (repeated) minimum transition run (RMTR) constraint, where the synchronization pattern comprises a synchronization pattern-body that contains a characteristic bit-pattern that represents a violation of the RMTR constraint. Using a violation of the RMTR constraint allows for short synchronization patterns.
摘要翻译：该ID提出具有（重复的）最小过渡运行（RMTR）约束的RLL代码的同步模式，其中同步模式包括包含表示违反RMTR约束的特征位模式的同步模式体。使用违反RMTR约束允许短同步模式。

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