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1. 发明授权

US08904266B2 Multi-standard viterbi processor 有权
标题翻译：多标准维特比处理器
公开(公告)号：US08904266B2
公开(公告)日：2014-12-02
申请号：US12853589
申请日：2010-08-10
申请人： Weihua Tang , Nur Engin , Frits Anthonie Steenhof , Marc Klaassen , Andries Pieter Hekstra , Sergie Valerjewitsch Sawitzki
发明人： Weihua Tang , Nur Engin , Frits Anthonie Steenhof , Marc Klaassen , Andries Pieter Hekstra , Sergie Valerjewitsch Sawitzki
IPC分类号： H03M13/17 , H03M13/00 , H03M13/41
CPC分类号： H03M13/4176 , H03M13/4107 , H03M13/4169 , H03M13/6519
摘要： Various embodiments relate to a multi-standard Viterbi decoder. Based on programmable values for constraint length, generator polynomials, and code rate, the multi-standard Viterbi decoder may adhere to a specific convolutional code standard. At a given time, the multi-standard Viterbi decoder may receive a variety of convolutional codes through a channel and may process them using various forms of the trace back method. Various embodiments include a branch metric unit and path metric unit that include a variety of sub-units that may or may not be active based on the value of the programmable value. Various embodiments also enable the multi-standard Viterbi decoder to handle different forms of convolutional codes, such as tail-biting codes. In some embodiments, the multi-standard Viterbi decoder may also process at least two convolutional codes concurrently.
摘要翻译：各种实施例涉及多标准维特比解码器。基于约束长度，生成多项式和码率的可编程值，多标准维特比解码器可以遵循特定的卷积码标准。在给定时间，多标准维特比解码器可以通过信道接收各种卷积码，并且可以使用各种形式的追溯方法来处理它们。各种实施例包括分支度量单位和路径度量单位，其包括可基于可编程值的值而可能或可以不是活动的各种子单元。各种实施例还使得多标准维特比解码器能够处理不同形式的卷积码，例如尾巴码。在一些实施例中，多标准维特比解码器也可以同时处理至少两个卷积码。

2. 发明申请

US20120042229A1 MULTI-STANDARD VITERBI PROCESSOR 有权
标题翻译：多标准VITERBI处理器
公开(公告)号：US20120042229A1
公开(公告)日：2012-02-16
申请号：US12853589
申请日：2010-08-10
申请人： Weihua Tang , Nur Engin , Frits Anthonie Steenhof , Marc Klaassen , Andries Pieter Hekstra , Sergei Valerjewitsch Sawitzki
发明人： Weihua Tang , Nur Engin , Frits Anthonie Steenhof , Marc Klaassen , Andries Pieter Hekstra , Sergei Valerjewitsch Sawitzki
IPC分类号： H03M13/03 , G06F11/10
CPC分类号： H03M13/4176 , H03M13/4107 , H03M13/4169 , H03M13/6519
摘要： Various embodiments relate to a multi-standard Viterbi decoder. Based on programmable values for constraint length, generator polynomials, and code rate, the multi-standard Viterbi decoder may adhere to a specific convolutional code standard. At a given time, the multi-standard Viterbi decoder may receive a variety of convolutional codes through a channel and may process them using various forms of the trace back method. Various embodiments include a branch metric unit and path metric unit that include a variety of sub-units that may or may not be active based on the value of the programmable value. Various embodiments also enable the multi-standard Viterbi decoder to handle different forms of convolutional codes, such as tail-biting codes. In some embodiments, the multi-standard Viterbi decoder may also process at least two convolutional codes concurrently.
摘要翻译：各种实施例涉及多标准维特比解码器。基于约束长度，生成多项式和码率的可编程值，多标准维特比解码器可以遵循特定的卷积码标准。在给定时间，多标准维特比解码器可以通过信道接收各种卷积码，并且可以使用各种形式的追溯方法来处理它们。各种实施例包括分支度量单位和路径度量单位，其包括可基于可编程值的值而可能或可以不是活动的各种子单元。各种实施例还使得多标准维特比解码器能够处理不同形式的卷积码，例如尾巴码。在一些实施例中，多标准维特比解码器也可以同时处理至少两个卷积码。

3. 发明授权

US08433975B2 Bitwise reliability indicators from survivor bits in Viterbi decoders 有权
标题翻译：维特比解码器中存活位的逐位可靠性指标
公开(公告)号：US08433975B2
公开(公告)日：2013-04-30
申请号：US12856143
申请日：2010-08-13
申请人： Andries Pieter Hekstra , Nur Engin
发明人： Andries Pieter Hekstra , Nur Engin
IPC分类号： H03M13/00
CPC分类号： H04L1/0054 , H03M13/09 , H03M13/2936 , H03M13/373 , H03M13/4138 , H03M13/4161 , H04L1/0059 , H04L1/0065
摘要： Various embodiments relate to the production of erasure flags to indicate errors resulting from decoding of convolutional codes. A Viterbi decoder may use a register exchange method to produce a plurality of survivor codes. At a defined index, a majority vote may take place comparing values of bits in each of the survivor codes. This majority vote may involve obtaining both the quantity of high-order bits and the quantity of low-order bits and obtaining the difference of the two quantities. The absolute value of the difference of high-order bits to low-order bits may be compared to a defined threshold. When the absolute value difference is below the defined quantity, an erasure flag may be produced and associated with the bits of the defined index, indicating that they are eligible for erasure. In some embodiments, a Reed-Solomon decoder may use the erasure flag to target specific survivor bits or survivor bytes for error-correction through erasure.
摘要翻译：各种实施例涉及擦除标志的产生，以指示由卷积码的解码产生的错误。维特比解码器可以使用寄存器交换方法来产生多个幸存代码。在定义的索引中，可以进行多数投票来比较每个幸存者代码中的比特值。这个多数投票可以涉及获得高阶位数量和低位数量，并获得两个数量的差。可以将高阶位与低位的差的绝对值与定义的阈值进行比较。当绝对值差低于定义的数量时，可以产生擦除标志并与定义的索引的位相关联，表示它们符合擦除条件。在一些实施例中，Reed-Solomon解码器可以使用擦除标志来针对特定的幸存者比特或幸存者字节来进行错误校正。

4. 发明申请

US20120042228A1 BITWISE RELIABILITY INDICATORS FROM SURVIVOR BITS IN VITERBI DECODERS 有权
标题翻译： VITERBI解码器中的生存位置的可比性可靠性指标
公开(公告)号：US20120042228A1
公开(公告)日：2012-02-16
申请号：US12856143
申请日：2010-08-13
申请人： Andries Pieter Hekstra , Nur Engin
发明人： Andries Pieter Hekstra , Nur Engin
IPC分类号： H03M13/07 , G06F11/10 , G06F11/07
CPC分类号： H04L1/0054 , H03M13/09 , H03M13/2936 , H03M13/373 , H03M13/4138 , H03M13/4161 , H04L1/0059 , H04L1/0065
摘要： Various embodiments relate to the production of erasure flags to indicate errors resulting from decoding of convolutional codes. A Viterbi decoder may use a register exchange method to produce a plurality of survivor codes. At a defined index, a majority vote may take place comparing values of bits in each of the survivor codes. This majority vote may involve obtaining both the quantity of high-order bits and the quantity of low-order bits and obtaining the difference of the two quantities. The absolute value of the difference of high-order bits to low-order bits may be compared to a defined threshold. When the absolute value difference is below the defined quantity, an erasure flag may be produced and associated with the bits of the defined index, indicating that they are eligible for erasure. In some embodiments, a Reed-Solomon decoder may use the erasure flag to target specific survivor bits or survivor bytes for error-correction through erasure.
摘要翻译：各种实施例涉及擦除标志的产生，以指示由卷积码的解码产生的错误。维特比解码器可以使用寄存器交换方法来产生多个幸存代码。在定义的索引中，可以进行多数投票来比较每个幸存者代码中的比特值。这个多数投票可以涉及获得高阶位数量和低位数量，并获得两个数量的差。可以将高阶位与低位的差的绝对值与定义的阈值进行比较。当绝对值差低于定义的数量时，可以产生擦除标志并与定义的索引的位相关联，表示它们符合擦除条件。在一些实施例中，Reed-Solomon解码器可以使用擦除标志来针对特定的幸存者比特或幸存者字节来进行错误校正。

5. 发明申请

US20050240644A1 Scalar/vector processor 有权
标题翻译：标量/矢量处理器
公开(公告)号：US20050240644A1
公开(公告)日：2005-10-27
申请号：US10515451
申请日：2003-05-22
申请人： Cornelis Van Berkel , Patrick Meuwissen , Nur Engin
发明人： Cornelis Van Berkel , Patrick Meuwissen , Nur Engin
IPC分类号： G06F9/30 , G06F9/38 , G06F15/78 , G06F17/16 , G06F7/38
CPC分类号： G06F9/3853 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/3824 , G06F9/3828 , G06F9/3834 , G06F9/3877 , G06F9/3885 , G06F9/3887 , G06F9/3893 , G06F15/8061
摘要： A scalar/vector processor includes a plurality of functional units (252, 260, 262, 264, 266, 268, 270). At least one of the functional units includes a vector section (210) for operating on at least one vector and a scalar section (220) for operating on at least one scalar. The vector section and scalar section of the functional unit co-operate by the scalar section being arranged to provide and/or consume at least one scalar required by and/or supplied by the vector section of the functional unit.
摘要翻译：标量/矢量处理器包括多个功能单元（252,260,262,264,266,268,270）。至少一个功能单元包括用于在至少一个矢量上操作的矢量部分（210）和用于在至少一个标量上操作的标量部分（220）。功能单元的矢量部分和标量部分由标量部分协作，被布置成提供和/或消耗由功能单元的向量部分所要求的和/或由其提供的至少一个标量。

6. 发明授权

US08510534B2 Scalar/vector processor that includes a functional unit with a vector section and a scalar section 有权
标题翻译：标量/向量处理器，其包括具有向量部分和标量部分的功能单元
公开(公告)号：US08510534B2
公开(公告)日：2013-08-13
申请号：US10515451
申请日：2003-05-22
申请人： Cornelis Hermanus Van Berkel , Patrick Peter Elizabeth Meuwissen , Nur Engin
发明人： Cornelis Hermanus Van Berkel , Patrick Peter Elizabeth Meuwissen , Nur Engin
IPC分类号： G06F15/00 , G06F15/76
CPC分类号： G06F9/3853 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/3824 , G06F9/3828 , G06F9/3834 , G06F9/3877 , G06F9/3885 , G06F9/3887 , G06F9/3893 , G06F15/8061
摘要： A scalar/vector processor includes a plurality of functional units (252, 260, 262, 264, 266, 268, 270). At least one of the functional units includes a vector section (210) for operating on at least one vector and a scalar section (220) for operating on at least one scalar. The vector section and scalar section of the functional unit co-operate by the scalar section being arranged to provide and/or consume at least one scalar required by and/or supplied by the vector section of the functional unit.
摘要翻译：标量/矢量处理器包括多个功能单元（252,260,262,264,266,268,270）。至少一个功能单元包括用于在至少一个矢量上操作的矢量部分（210）和用于在至少一个标量上操作的标量部分（220）。功能单元的矢量部分和标量部分由标量部分协作，被布置成提供和/或消耗由功能单元的向量部分所要求的和/或由其提供的至少一个标量。

7. 发明授权

US08438434B2 N-way parallel turbo decoder architecture 有权
标题翻译： N路并行turbo解码器架构
公开(公告)号：US08438434B2
公开(公告)日：2013-05-07
申请号：US12650072
申请日：2009-12-30
申请人： Nur Engin
发明人： Nur Engin
IPC分类号： G06F11/00
CPC分类号： H03M13/2987 , G11C7/1042 , G11C8/10 , G11C8/12 , H03M13/2978 , H03M13/6566
摘要： Various embodiments relate to a memory device in a turbo decoder and a related method for allocating data into the memory device. Different communications standards use data blocks of varying sizes when enacting block decoding of concatenated convolutional codes. The memory device efficiently minimizes space while enabling a higher throughput of the turbo decoder by enabling a plurality of memory banks of equal size. The number of memory banks may be limited by the amount of unused space in the memory banks, which may be a waste of area on an IC chip. Using the address associated with the maximum value of the data block, the memory may be split into a plurality of memory blocks according to the most-significant bits of the maximum address, with a number of parallel SISO decoders matching the number of memory banks. This may enable higher throughput while minimizing area on the IC chip.
摘要翻译：各种实施例涉及turbo解码器中的存储器件以及用于将数据分配到存储器件中的相关方法。不同的通信标准在采用级联卷积码的块解码时，使用不同大小的数据块。存储器件有效地使空间最小化，同时通过启用相同大小的多个存储体，能够实现turbo解码器的更高吞吐量。存储体的数量可能受到存储体中未使用空间的量的限制，这可能是IC芯片上的区域的浪费。使用与数据块的最大值相关联的地址，存储器可以根据最大地址的最高有效位被分割成多个存储器块，并且多个并行SISO解码器与存储器组的数量相匹配。这可以实现更高的吞吐量，同时最小化IC芯片上的面积。

8. 发明申请

US20110307673A1 RECONFIGURABLE INTERLEAVER HAVING RECONFIGURABLE COUNTERS 有权
标题翻译：具有可重构计数器的可重新配置的交换机
公开(公告)号：US20110307673A1
公开(公告)日：2011-12-15
申请号：US13157085
申请日：2011-06-09
申请人： Nur Engin
发明人： Nur Engin
IPC分类号： G06F12/06
CPC分类号： H03M13/2789 , H03M13/271 , H03M13/2725 , H03M13/2739 , H03M13/276 , H03M13/2764 , H03M13/2771 , H03M13/2775 , H03M13/6519 , H03M13/6525
摘要： A reconfigurable interleaver is provided, configured to produce a sequence of interleaved addresses, configurable for at least two different interleaving patterns. The reconfigurable interleaver comprises a plurality of reconfigurable counters. The number of values that the counters count is configurable as are their start values. The interleaver further comprises a plurality of memory in which the counters indicate memory positions so that values may be retrieved. Computational elements compute an interleaved sequence of addresses in dependency on the retrieved values. By reconfiguring the counters and possibly changing the content of the memories, the interleaver may be configured for a different interleaving pattern.
摘要翻译：提供可重构交错器，其被配置为产生可配置用于至少两个不同交织模式的交错地址序列。可重配置交织器包括多个可重配置计数器。计数器计数的值的数量可以是其起始值。交织器还包括多个存储器，其中计数器指示存储器位置，从而可以检索值。计算元素根据检索到的值计算交织的地址序列。通过重新配置计数器并且可能改变存储器的内容，交织器可以被配置为不同的交织模式。

9. 发明申请

US20110161782A1 N-WAY PARALLEL TURBO DECODER ARCHITECTURE 有权
标题翻译： N-WAY并行涡轮解码器架构
公开(公告)号：US20110161782A1
公开(公告)日：2011-06-30
申请号：US12650072
申请日：2009-12-30
申请人： Nur Engin
发明人： Nur Engin
IPC分类号： H03M13/05 , G06F12/00 , G06F11/10
CPC分类号： H03M13/2987 , G11C7/1042 , G11C8/10 , G11C8/12 , H03M13/2978 , H03M13/6566
摘要： Various embodiments relate to a memory device in a turbo decoder and a related method for allocating data into the memory device. Different communications standards use data blocks of varying sizes when enacting block decoding of concatenated convolutional codes. The memory device efficiently minimizes space while enabling a higher throughput of the turbo decoder by enabling a plurality of memory banks of equal size. The number of memory banks may be limited by the amount of unused space in the memory banks, which may be a waste of area on an IC chip. Using the address associated with the maximum value of the data block, the memory may be split into a plurality of memory blocks according to the most-significant bits of the maximum address, with a number of parallel SISO decoders matching the number of memory banks. This may enable higher throughput while minimizing area on the IC chip.
摘要翻译：各种实施例涉及turbo解码器中的存储器件以及用于将数据分配到存储器件中的相关方法。不同的通信标准在采用级联卷积码的块解码时，使用不同大小的数据块。存储器件有效地使空间最小化，同时通过启用相同大小的多个存储体，能够实现turbo解码器的更高吞吐量。存储体的数量可能受到存储体中未使用空间的量的限制，这可能是IC芯片上的区域的浪费。使用与数据块的最大值相关联的地址，存储器可以根据最大地址的最高有效位被分割成多个存储器块，并且多个并行SISO解码器与存储器组的数量相匹配。这可以实现更高的吞吐量，同时最小化IC芯片上的面积。

10. 发明授权

US08874858B2 Reconfigurable interleaver having reconfigurable counters 有权
标题翻译：具有可重配置计数器的可重构交错器
公开(公告)号：US08874858B2
公开(公告)日：2014-10-28
申请号：US13157085
申请日：2011-06-09
申请人： Nur Engin
发明人： Nur Engin
IPC分类号： H03M13/27 , G06F12/00 , H03M13/00
CPC分类号： H03M13/2789 , H03M13/271 , H03M13/2725 , H03M13/2739 , H03M13/276 , H03M13/2764 , H03M13/2771 , H03M13/2775 , H03M13/6519 , H03M13/6525
摘要： A reconfigurable interleaver is provided, configured to produce a sequence of interleaved addresses, configurable for at least two different interleaving patterns. The reconfigurable interleaver comprises a plurality of reconfigurable counters. The number of values that the counters count is configurable as are their start values. The interleaver further comprises a plurality of memory in which the counters indicate memory positions so that values may be retrieved. Computational elements compute an interleaved sequence of addresses in dependency on the retrieved values. By reconfiguring the counters and possibly changing the content of the memories, the interleaver may be configured for a different interleaving pattern.
摘要翻译：提供可重构交错器，其被配置为产生可配置用于至少两个不同交织模式的交错地址序列。可重配置交织器包括多个可重配置计数器。计数器计数的值的数量可以是其起始值。交织器还包括多个存储器，其中计数器指示存储器位置，从而可以检索值。计算元素根据检索到的值计算交织的地址序列。通过重新配置计数器并且可能改变存储器的内容，交织器可以被配置为不同的交织模式。

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