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1. 发明授权

US08458383B1 Flexible interface for stacked protocol in a programmable integrated circuit device 有权
标题翻译：可编程集成电路器件中堆叠协议的灵活接口
公开(公告)号：US08458383B1
公开(公告)日：2013-06-04
申请号：US11848016
申请日：2007-08-30
申请人： Curt Wortman , Chong H. Lee , Divya Vijayaraghavan , Ning Xue
发明人： Curt Wortman , Chong H. Lee , Divya Vijayaraghavan , Ning Xue
IPC分类号： G06F13/14 , G06F15/16
CPC分类号： G06F13/4059 , Y02D10/14 , Y02D10/151
摘要： On programmable device, each layer of a programmable interface, for a protocol which has a protocol stack including at least a physical layer, a data link layer and a transaction layer, is selectably bypassable. When a layer is bypassed, all other layers downstream of that layer also are bypassed. In addition, the interface may be divided into different clock domains running at different clock rates, reflecting clock rates within the programmable device and outside the programmable device. Layers may be bypassed to allow a user to substitute a custom layer in programmable logic, or to substitute an updated layer for debugging purposes.
摘要翻译：在可编程设备上，用于具有包括至少物理层，数据链路层和事务层的协议栈的协议的可编程接口的每层可选择地旁路。当旁路一层时，该层下游的所有其他层也被旁路。此外，该接口可以被划分为以不同的时钟速率运行的不同的时钟域，反映了可编程器件内部和可编程器件外部的时钟速率。可以绕过图层以允许用户替换可编程逻辑中的自定义层，或者替换更新的层进行调试。

2. 发明授权

US09531646B1 Multi-protocol configurable transceiver including configurable deskew in an integrated circuit 有权
标题翻译：多协议可配置收发器，包括集成电路中的可配置的偏移校正
公开(公告)号：US09531646B1
公开(公告)日：2016-12-27
申请号：US12632744
申请日：2009-12-07
申请人： Divya Vijayaraghavan , Curt Wortman , Chong H. Lee , Vinson Chan
发明人： Divya Vijayaraghavan , Curt Wortman , Chong H. Lee , Vinson Chan
IPC分类号： G06F3/00 , H04L12/861 , G06F5/10
CPC分类号： H04L49/90 , G06F5/10
摘要： Embodiments include a configurable multi-protocol transceiver including configurable deskew circuitry. In one embodiment, configurable circuitry is adapted to control an allowed data depth of a plurality of buffers. In another embodiment, configurable circuitry is adapted to control a deskew character transmit insertion frequency. In another embodiment, a programmable state machine is adapted to control read and write pointers in accordance with selectable conditions for achieving an alignment lock condition. In another embodiment, configurable circuitry is adaptable to select between logic and routing resources in the transceiver and logic and routing resources in a core of the IC in which the transceiver is implemented for controlling at least certain deskew operations. In another embodiment, configurable selection circuitry allows deskew processing to occur in a data path either before or after clock compensation processing depending on a communication protocol for which the transceiver is to be configured.
摘要翻译：实施例包括可配置的多协议收发器，包括可配置的偏移电路。在一个实施例中，可配置电路适于控制多个缓冲器的允许数据深度。在另一个实施例中，可配置电路适于控制偏斜字符传输插入频率。在另一个实施例中，可编程状态机适于根据用于实现对准锁定状态的可选条件来控制读取和写入指针。在另一个实施例中，可配置电路适于在收发器中的逻辑和路由资源之间选择逻辑，并且在IC的核心中布线资源，其中实现收发器用于控制至少某些去歪斜操作。在另一个实施例中，可配置的选择电路允许在时钟补偿处理之前或之后在数据路径中进行偏移处理，这取决于要配置收发器的通信协议。

3. 发明申请

US20100215086A1 Multi-protocol channel-aggregated configurable transceiver in an integrated circuit 有权
标题翻译：集成电路中的多协议通道聚合可配置收发器
公开(公告)号：US20100215086A1
公开(公告)日：2010-08-26
申请号：US12288178
申请日：2008-10-17
申请人： Divya Vijayaraghavan , Curt Wortman , Chong H. Lee
发明人： Divya Vijayaraghavan , Curt Wortman , Chong H. Lee
IPC分类号： H04B1/38
CPC分类号： H04B1/005 , G06F13/385 , H04L69/12 , H04L69/18
摘要： Embodiments in the disclosure include a multi-protocol transceiver including a configurable arrangement of receive and/or transmit circuitry. An exemplary transceiver can be selectively configured to effectively transmit and/or receive data communications corresponding to a select one of a plurality of high-speed communication protocols. Another more particular embodiment disclosed includes a configurable data path through link-wide Physical Coding Sub-layer (“PCS”) circuitry including link-wide clock compensation, encoding/decoding, and scrambling/descrambling circuitry and lane striping/de-striping circuitry; the configurable data path further includes lane-wide circuitry including clock compensation, encoding/decoding, receive block sync, and Physical Medium Access sub-layer (“PMA”) circuitry, and further includes bit muxing/de-muxing circuitry coupled to Physical Medium Dependent (“PMD”) sub-layer circuitry.
摘要翻译：本公开的实施例包括包括接收和/或发送电路的可配置布置的多协议收发器。可以选择性地配置示例性收发器以有效地发送和/或接收对应于多个高速通信协议中的选择一个的数据通信。所公开的另一更具体的实施例包括通过链路范围物理编码子层（“PCS”）电路的可配置数据路径，包括链路范围时钟补偿，编码/解码以及加扰/解扰频电路和通道条带/去条纹电路; 可配置数据路径还包括通道宽电路，包括时钟补偿，编码/解码，接收块同步和物理介质访问子层（“PMA”）电路，并且还包括耦合到物理介质的位复用/解复用电路从属（“PMD”）子层电路。

4. 发明授权

US08165191B2 Multi-protocol channel-aggregated configurable transceiver in an integrated circuit 有权
标题翻译：集成电路中的多协议通道聚合可配置收发器
公开(公告)号：US08165191B2
公开(公告)日：2012-04-24
申请号：US12288178
申请日：2008-10-17
申请人： Divya Vijayaraghavan , Curt Wortman , Chong H. Lee
发明人： Divya Vijayaraghavan , Curt Wortman , Chong H. Lee
IPC分类号： H04B1/38 , H04L5/16
CPC分类号： H04B1/005 , G06F13/385 , H04L69/12 , H04L69/18
摘要： Embodiments in the disclosure include a multi-protocol transceiver including a configurable arrangement of receive and/or transmit circuitry. An exemplary transceiver can be selectively configured to effectively transmit and/or receive data communications corresponding to a select one of a plurality of high-speed communication protocols. Another more particular embodiment disclosed includes a configurable data path through link-wide Physical Coding Sub-layer (“PCS”) circuitry including link-wide clock compensation, encoding/decoding, and scrambling/descrambling circuitry and lane striping/de-striping circuitry; the configurable data path further includes lane-wide circuitry including clock compensation, encoding/decoding, receive block sync, and Physical Medium Access sub-layer (“PMA”) circuitry, and further includes bit muxing/de-muxing circuitry coupled to Physical Medium Dependent (“PMD”) sub-layer circuitry.
摘要翻译：本公开的实施例包括包括接收和/或发送电路的可配置布置的多协议收发器。可以选择性地配置示例性收发器以有效地发送和/或接收对应于多个高速通信协议中的选择一个的数据通信。所公开的另一更具体的实施例包括通过链路范围物理编码子层（“PCS”）电路的可配置数据路径，包括链路范围时钟补偿，编码/解码以及加扰/解扰频电路和通道条带/去条纹电路; 可配置数据路径还包括通道宽电路，包括时钟补偿，编码/解码，接收块同步和物理介质访问子层（“PMA”）电路，并且还包括耦合到物理介质的位复用/解复用电路从属（“PMD”）子层电路。

5. 发明授权

US09736086B1 Multi-function, multi-protocol FIFO for high-speed communication 有权
公开(公告)号：US09736086B1
公开(公告)日：2017-08-15
申请号：US13098361
申请日：2011-04-29
申请人： Huy Ngo , Keith Duwel , Vinson Chan , Divya Vijayaraghavan , Curt Wortman
发明人： Huy Ngo , Keith Duwel , Vinson Chan , Divya Vijayaraghavan , Curt Wortman
IPC分类号： H04L12/861
CPC分类号： H04L49/90 , H04L47/6245
摘要： Systems and methods are disclosed for buffering data using a multi-function, multi-protocol first-in-first-out (FIFO) circuit. For example, a data buffering apparatus is provided that includes a mode selection input and a FIFO circuit that is operative to buffer a data signal between a FIFO circuit input and a FIFO circuit output, wherein the FIFO circuit is configured in an operating mode responsive to the mode selection signal.

6. 发明申请

US20100277201A1 EMBEDDED DIGITAL IP STRIP CHIP 审中-公开
标题翻译：嵌入式数字IP条带芯片
公开(公告)号：US20100277201A1
公开(公告)日：2010-11-04
申请号：US12434606
申请日：2009-05-01
申请人： Curt Wortman , Chong H. Lee , Richard G. Cliff
发明人： Curt Wortman , Chong H. Lee , Richard G. Cliff
IPC分类号： H03K19/173 , G06F17/50
CPC分类号： G06F17/5045 , G06F2217/84 , H03K19/17724 , H03K19/17732
摘要： An integrated circuit (IC) is provided. The IC includes a first region having an array of programmable logic cells. The IC also includes a second region incorporated into the IC and in communication with the first region. The second region includes standard logic cells and base cells. In one embodiment, the standard logic cells are assembled or interconnected to accommodate known protocols. The base cells include configurable logic to adapt to modifications to emerging communication protocols, which are supported by the base cells. The second region can be embedded in the first region in one embodiment. In another embodiment, the second region is defined around a perimeter of the first region. The configurable logic may be composed of hybrid logic elements that have metal mask programmable interconnections so that as emerging communication protocols evolve and are modified, the IC can be modified to accommodate to the changes in the protocol. In another embodiment, a generic device can be customized by replacing the original function with a completely new function targeting a specific application space, e.g., replacing the original function such as a PCI Express, used for computing based applications, with 40 G/100 G Ethernet and Interlaken, used in wireline applications. A method of designing an integrated circuit is also provided.
摘要翻译：提供集成电路（IC）。 IC包括具有可编程逻辑单元阵列的第一区域。 IC还包括结合到IC中并与第一区域通信的第二区域。第二区包括标准逻辑单元和基本单元。在一个实施例中，标准逻辑单元被组合或互连以适应已知协议。基本单元包括可配置逻辑以适应由基本单元支持的新兴通信协议的修改。在一个实施例中，第二区域可以嵌入第一区域。在另一个实施例中，第二区域围绕第一区域的周边限定。可配置逻辑可以由具有金属掩模可编程互连的混合逻辑元件组成，使得随着新兴通信协议的发展和修改，可以修改IC以适应协议的改变。在另一个实施例中，可以通过用针对特定应用空间的全新功能替换原始功能来定制通用设备，例如用40G / 100G替换用于基于计算的应用的诸如PCI Express的原始功能以太网和因特拉肯，用于有线应用。还提供了一种设计集成电路的方法。

7. 发明授权

US08949493B1 Configurable multi-lane scrambler for flexible protocol support 有权
标题翻译：可配置的多通道加扰器，用于灵活的协议支持
公开(公告)号：US08949493B1
公开(公告)日：2015-02-03
申请号：US12847761
申请日：2010-07-30
申请人： Curt Wortman , Chong H. Lee , Huy Ngo
发明人： Curt Wortman , Chong H. Lee , Huy Ngo
IPC分类号： G06F3/00 , G06F13/00 , G06F5/00 , G06F13/12 , G06M3/00 , G11C19/00 , G01R31/28 , G06F17/50 , G06F1/02 , G06F7/58 , H04L9/00
CPC分类号： H04L25/03866 , G06F3/00 , G06F5/00 , G06F7/58 , G06F13/00 , G06F13/12 , G06F13/40 , G06F13/4221 , G06F13/4282 , G11C7/1012 , G11C7/1036 , G11C19/00 , G11C19/285 , H04L9/00
摘要： Various structures and methods are disclosed related to configurable scrambling circuitry. Embodiments can be configured to support one of a plurality of protocols. Some embodiments relate to a configurable multilane scrambler that can be adapted either to combine scrambling circuits across a plurality of lanes or to provide independent lane-based scramblers. Some embodiments are configurable to select a scrambler type. Some embodiments are configurable to adapt to one of a plurality of protocol-specific scrambling polynomials. Some embodiments relate to selecting between least significant bit (“LSB”) and most significant bit (“MSB”) ordering of data. In some embodiments, scrambler circuits in each lane are adapted to handle data that is more than one bit wide.
摘要翻译：公开了与可配置加扰电路相关的各种结构和方法。实施例可以被配置为支持多个协议中的一个。一些实施例涉及可配置的多径扰频器，其可以适于组合跨越多个车道的加扰电路或者提供独立的基于车道的加扰器。一些实施例可配置为选择加扰器类型。一些实施例可配置为适应多个协议特定的加扰多项式之一。一些实施例涉及在数据的最低有效位（“LSB”）和最高有效位（“MSB”）排序之间进行选择。在一些实施例中，每个通道中的加扰器电路适于处理超过一位宽的数据。

8. 发明授权

US09436250B1 Apparatus for improving power consumption of communication circuitry and associated methods 有权
标题翻译：用于改善通信电路和相关方法的功耗的装置
公开(公告)号：US09436250B1
公开(公告)日：2016-09-06
申请号：US13330635
申请日：2011-12-19
申请人： Curt Wortman , Keith Duwel , Michael Menghui Zheng
发明人： Curt Wortman , Keith Duwel , Michael Menghui Zheng
IPC分类号： G06F1/00 , G06F1/32
CPC分类号： H03L7/0807 , G06F1/32 , G06F1/3278 , G06F1/3296 , G06F11/0736 , G06F11/076 , G06F11/079 , H03K19/0008 , H03K19/1737 , H03K19/17728 , H03K19/1776 , H04B17/309 , Y02D10/157
摘要： An integrated circuit (IC) includes communication circuitry, a body bias generator, and a controller. The communication circuitry includes a physical medium attachment (PMA) and a physical coding sublayer (PCS). The body bias generator provides body bias signals to the PMA and PCS. The controller controls the body bias generator such that the body bias signals are controlled to improve a power consumption of the communication circuitry.
摘要翻译：集成电路（IC）包括通信电路，体偏置发生器和控制器。通信电路包括物理介质连接（PMA）和物理编码子层（PCS）。身体偏置发生器向PMA和PCS提供身体偏置信号。控制器控制身体偏置发生器，使得身体偏置信号被控制以提高通信电路的功率消耗。

9. 发明授权

US08650447B1 Apparatus and methods for controlled error injection 有权
标题翻译：用于控制误差注入的装置和方法
公开(公告)号：US08650447B1
公开(公告)日：2014-02-11
申请号：US13183147
申请日：2011-07-14
申请人： Curt Wortman , Keith Duwel , Huy Ngo
发明人： Curt Wortman , Keith Duwel , Huy Ngo
IPC分类号： G01R31/28 , G01R27/28 , G01R31/00 , G01R31/14 , G11C7/00 , G11C29/00
CPC分类号： G11C29/54 , G01R31/318516 , G11C29/04
摘要： In accordance with an embodiment of the invention, precision control of error injection may be accomplished by way of synchronous error signals accompanying data transfers along various pipeline stages of a data path. The synchronous error signals may be used to trigger error events in a given protocol logic block (i.e. in a given sub-component of the data path). The protocol logic block is configurable to determine whether any action is to be taken upon the assertion of the error signal. Multiple error events may be triggered as the data signal (and its accompanying synchronous error signal) passes through pipelined functions of the data path so as to create complex error conditions. In addition, deterministic handling of created errors may be accomplished using a loopback path with bypassable blocks on both forward and reverse transformations. Other embodiments, aspects and features are also disclosed.
摘要翻译：根据本发明的实施例，错误注入的精确控制可以通过伴随数据路径的各个流水线级数据传输的同步误差信号来实现。同步误差信号可用于触发给定协议逻辑块（即在数据路径的给定子组件中）的错误事件。协议逻辑块是可配置的，以确定是否在断言错误信号时采取任何动作。随着数据信号（及其伴随的同步误差信号）通过数据路径的流水线功能，可能会触发多个错误事件，从而创建复杂的错误条件。此外，可以使用在正向和反向转换两者上具有可旁路块的环回路径来实现所创建的错误的确定性处理。还公开了其它实施例，方面和特征。

10. 发明授权

US07843216B2 Techniques for optimizing design of a hard intellectual property block for data transmission 有权
标题翻译：用于优化硬件知识产权块设计数据传输的技术
公开(公告)号：US07843216B2
公开(公告)日：2010-11-30
申请号：US12193532
申请日：2008-08-18
申请人： Darren van Wageningen , Curt Wortman , Boon-Jin Ang , Thow-Pang Chong , Dan Mansur , Ali Burney
发明人： Darren van Wageningen , Curt Wortman , Boon-Jin Ang , Thow-Pang Chong , Dan Mansur , Ali Burney
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： H04L25/14
摘要： Techniques are provided for implementing channel alignment for a data transmission interface in an HIP block on a programmable logic integrated circuit. The HIP block channel alignment logic can be run using a reduced number of parallel data paths, which consumes substantially less logic resources. Also, the HIP block channel alignment logic circuits can be processed at the higher HIP core clock rate in serial, decreasing lock latency time. Techniques are provided for implementing error handling for transmitted data in programmable logic circuits. The programmable logic circuits can be configured to implement error generation and error monitoring functions that are tailored for any application. Alternatively, the logic elements can be configured to perform other functions for applications that do not require error handling. The phase skew between data and clock signals on an integrated circuit are reduced by routing clock signals along with the data signals to each circuit block.
摘要翻译：提供了用于为可编程逻辑集成电路上的HIP块中的数据传输接口实现信道对准的技术。 HIP块信道对准逻辑可以使用减少数量的并行数据路径来运行，这消耗了相当少的逻辑资源。此外，HIP块通道对准逻辑电路可以以较高的HIP内核时钟速率串行处理，减少锁定延迟时间。提供了用于在可编程逻辑电路中实现发送数据的错误处理的技术。可编程逻辑电路可以配置为实现为任何应用定制的错误生成和错误监视功能。或者，可以将逻辑元件配置为对不需要错误处理的应用执行其他功能。通过将时钟信号与数据信号一起路由到每个电路块来减少集成电路上的数据和时钟信号之间的相位偏移。

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