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1. 发明授权

US06383863B1 Approach to integrate salicide gate for embedded DRAM devices 有权
标题翻译：为嵌入式DRAM设备集成自杀门的方法
公开(公告)号：US06383863B1
公开(公告)日：2002-05-07
申请号：US09963595
申请日：2001-09-27
申请人： Min-Hsiung Chiang , Hsiao-Hui Tseng , Hsien-Yuan Chang , Chung-Wei Chang , Kuo-Chyuan Tzeng
发明人： Min-Hsiung Chiang , Hsiao-Hui Tseng , Hsien-Yuan Chang , Chung-Wei Chang , Kuo-Chyuan Tzeng
IPC分类号： H01L218242
CPC分类号： H01L27/10852 , H01L21/76889 , H01L21/76897 , H01L27/10873 , H01L27/10888 , H01L28/84 , H01L28/90 , H01L29/66545
摘要： A process for integrating the formation of a salicide layer on DRAM word line structures, and on a bit line contact structure, has been developed. The process features selective etch back of the insulator layers embedding the tapered shaped bit line contact, and the tapered shape capacitor structures, exposing top surface portions of polysilicon word line structures. The selective etch back procedure also results in formation of insulator spacers on the sides of the tapered bit line contact, and capacitor structures, allowing a subsequent salicide procedure to form metal suicide layers only on the exposed top surfaces of the DRAM word line, bit line contact, and capacitor structures.
摘要翻译：已经开发了一种用于将自对准硅化物层形成在DRAM字线结构上以及位线接触结构上的过程。该工艺具有嵌入锥形位线接触件的绝缘体层的选择性回蚀和锥形形状电容器结构，暴露多晶硅字线结构的顶表面部分。选择性回蚀程序还导致在锥形位线接触和电容器结构的侧面上形成绝缘体间隔物，并且允许随后的自对准硅化物程序仅在DRAM字线，位线的暴露的顶表面上形成金属硅化物层接触和电容器结构。

2. 发明授权

US06436762B1 Method for improving bit line to capacitor electrical failures on DRAM circuits using a wet etch-back to improve the bit-line-to-capacitor overlay margins 有权
标题翻译：使用湿式回蚀技术改善DRAM电路上电容器电气故障的位线的方法，以改善位线电容器覆盖边界
公开(公告)号：US06436762B1
公开(公告)日：2002-08-20
申请号：US09855238
申请日：2001-05-14
申请人： Kuo-Chyuan Tzeng , Tse-Liang Ying , Min-Hsiung Chiang , Hsiao-Hui Tseng , Chung-Wei Chang
发明人： Kuo-Chyuan Tzeng , Tse-Liang Ying , Min-Hsiung Chiang , Hsiao-Hui Tseng , Chung-Wei Chang
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108 , H01L21/8234 , H01L21/20
CPC分类号： H01L27/10888 , H01L27/10811 , H01L28/91
摘要： A method is described for making capacitor-under-bit line (CUB) DRAM cells with improved overlay margins between bit lines and capacitor top electrodes. After forming FETs for the memory cells, an interpolysilicon oxide (IPO) layer is deposited, and first and second plug contacts are formed in the IPO to the FET source/drain areas for capacitors and bit line contacts, respectively. A capacitor node oxide is deposited, and first openings are etched in which crown capacitor bottom electrodes are formed. After etching back the node oxide a thin interelectrode dielectric layer is formed and a conformal conducting layer is deposited to form capacitor top electrodes. A photoresist mask is used to etch openings in the conducting layer over the second plug contacts, and an isotropic etch is used to recess the openings under the mask to increase the spacing between the capacitor top electrodes and the bit line contacts to improve the overlay margin. The photoresist mask is removed and an interlevel dielectric (ILD) layer is deposited. Bit-line contact openings are etched in the ILD layer aligned over the recessed openings and in the node oxide to the second contact plugs. Bit-line contact plugs are formed extending through the recessed openings, and a first conducting layer is deposited and patterned to form bit lines and to complete the memory cells for the DRAM.
摘要翻译：描述了一种用于制造具有改进的位线和电容器顶部电极之间的覆盖边缘的电容器下位线（CUB）DRAM单元的方法。在形成用于存储单元的FET之后，沉积多晶硅氧化物（IPO）层，并且在IPO中分别将第一和第二插头触点形成到用于电容器和位线触点的FET源极/漏极区域。沉积电容器节点氧化物，并且蚀刻第一开口，其中形成冠电容器底部电极。在蚀刻回节点氧化物之后，形成薄的电极间电介质层，并且淀积保形导电层以形成电容器顶部电极。使用光致抗蚀剂掩模来蚀刻导电层上的第二插头触点上的开口，并且使用各向同性蚀刻来凹陷掩模下方的开口以增加电容器顶部电极和位线触点之间的间隔，以改善覆盖边缘。去除光致抗蚀剂掩模并沉积层间电介质（ILD）层。在ILD层中蚀刻位线接触开口，其在凹入的开口上以及在节点氧化物中对齐到第二接触插塞。位线接触插塞形成为延伸穿过凹入的开口，并且第一导电层被沉积和图案化以形成位线并且完成用于DRAM的存储单元。

3. 发明授权

US06656786B2 MIM process for logic-based embedded RAM having front end manufacturing operation 有权
标题翻译：用于具有前端制造操作的基于逻辑的嵌入式RAM的MIM工艺
公开(公告)号：US06656786B2
公开(公告)日：2003-12-02
申请号：US10000896
申请日：2001-11-02
申请人： Min-Hsiung Chiang , Hsiao-Hui Tseng , Hsien-Yuan Chang , Tazy-Schiuan Yang
发明人： Min-Hsiung Chiang , Hsiao-Hui Tseng , Hsien-Yuan Chang , Tazy-Schiuan Yang
IPC分类号： H01L218242
CPC分类号： H01L27/10852 , H01L27/10814 , H01L27/10894 , H01L28/60 , Y10S977/888
摘要： A method and system for manufacturing an MIM capacitor for utilization with a logic-based embedded DRAM device. At least one transistor, an interlayer dielectric, at least one contact and at least one metal one layer are generally formed on a substrate during a front end manufacturing operation of the capacitor on the substrate. An inter-metal dielectric layer is deposited upon the substrate, followed thereafter by a chemical mechanical polishing operation. Additionally, a lithographic operation is performed upon the substrate. Also, at least one dielectric deposition layer is generally on the substrate, followed thereafter by a chemical mechanical polishing operation and a stop on an oxide layer formed on the substrate. At least one metal two layer may then be formed on substrate and associated layers thereof, thereby resulting in the formation of a capacitor fully compatible with logic-based devices and processes thereof.
摘要翻译：一种制造用于利用基于逻辑的嵌入式DRAM器件的MIM电容器的方法和系统。在基板上的电容器的前端制造操作期间，通常在基板上形成至少一个晶体管，层间电介质，至少一个触点和至少一个金属层。金属介电层沉积在基板上，其后通过化学机械抛光操作。另外，在基板上执行光刻操作。此外，至少一个电介质沉积层通常在衬底上，随后通过化学机械抛光操作和在形成在衬底上的氧化物层上的停止。然后可以在衬底及其相关层上形成至少一个金属二层，从而形成与基于逻辑的器件及其工艺完全兼容的电容器。

4. 发明授权

US06656785B2 MIM process for logic-based embedded RAM 有权
标题翻译：基于逻辑的嵌入式RAM的MIM过程
公开(公告)号：US06656785B2
公开(公告)日：2003-12-02
申请号：US09978421
申请日：2001-10-15
申请人： Min-Hsiung Chiang , Hsiao-Hui Tseng , Hsien-Yuan Chang
发明人： Min-Hsiung Chiang , Hsiao-Hui Tseng , Hsien-Yuan Chang
IPC分类号： H01L218242
CPC分类号： H01L27/10852 , H01L21/31604 , H01L27/10855 , H01L27/10894 , H01L28/55 , H01L28/91
摘要： A method for forming a metal-interlayer-metal (MIM) device in an embedded memory device, including semiconductor devices thereof. An MIM device can be formed upon a semiconductor substrate utilizing no more than one additional photo mask layer prior to the implementation of a back-end-of-line (BEOL) semiconductor fabrication operation, such that the MIM device can be configured as a low temperature MIM device that is fully compatible with logical semiconductor devices, thereby reducing associated manufacturing costs. The MIM device may be configured as an MIM capacitor for logic-based embedded DRAM devices, resulting in a high capacitance performed via an effective area extension of DRAM cell capacitors. Additonally, a low-temperature MIM capacitor thereof may be readily integrated for both Cu (Copper) and AlCu (Aluminum Copper) BEOL fabrication processes.
摘要翻译：一种在包括其半导体器件的嵌入式存储器件中形成金属 - 层间金属（MIM）器件的方法。 MIM器件可以在实施后端（BEOL）半导体制造操作之前利用不超过一个附加光掩模层在半导体衬底上形成，使得MIM器件可以被配置为低与逻辑半导体器件完全兼容，从而降低相关的制造成本。 MIM器件可以被配置为用于基于逻辑的嵌入式DRAM器件的MIM电容器，导致通过DRAM单元电容器的有效区域扩展来执行高电容。此外，其中的低温MIM电容器可以容易地集成在Cu（铜）和AlCu（Aluminum Copper）BEOL制造工艺中。

5. 发明授权

US06833578B1 Method and structure improving isolation between memory cell passing gate and capacitor 有权
标题翻译：存储单元通过栅极和电容器之间的隔离方法和结构
公开(公告)号：US06833578B1
公开(公告)日：2004-12-21
申请号：US10733216
申请日：2003-12-11
申请人： Kuo-Chi Tu , Chun-Yao Chen , Huey-Chi Chu , Chung-Wei Chang , Tien-Lu Lin , Kuo-Ching Huang , Wen-Cheng Chen , Tsung-Hsun Huang , Hsiao-Hui Tseng
发明人： Kuo-Chi Tu , Chun-Yao Chen , Huey-Chi Chu , Chung-Wei Chang , Tien-Lu Lin , Kuo-Ching Huang , Wen-Cheng Chen , Tsung-Hsun Huang , Hsiao-Hui Tseng
IPC分类号： H01L27108
CPC分类号： H01L28/57 , H01L27/11 , H01L28/90
摘要： A memory cell comprising a capacitor having a dielectric layer interposing first and second vertically disposed electrodes, an insulating lining located over the capacitor, and a transistor gate extension passing over the capacitor. A spacer isolates an end of one of the capacitor electrodes from the transistor gate extension. In one embodiment, the spacer includes a first non-planar profile configured to engage a second non-planar profile comprising ends of the one of the capacitor electrodes and the insulating lining.
摘要翻译：一种存储单元，包括具有插入第一和第二垂直设置的电极的介电层的电容器，位于电容器上方的绝缘衬垫，以及通过电容器的晶体管栅极延伸。间隔件将电容器电极之一的端部与晶体管栅极延伸部隔离。在一个实施例中，间隔件包括构造成接合包括电容器电极之一和绝缘衬里的端部的第二非平面轮廓的第一非平面轮廓。

6. 发明授权

US08685820B2 Multiple gate dielectric structures and methods of forming the same 有权
标题翻译：多栅电介质结构及其形成方法
公开(公告)号：US08685820B2
公开(公告)日：2014-04-01
申请号：US13207643
申请日：2011-08-11
申请人： Hsiao-Hui Tseng , Dun-Nian Yaung , Jen-Cheng Liu , Wen-I Hsu , Min-Feng Kao
发明人： Hsiao-Hui Tseng , Dun-Nian Yaung , Jen-Cheng Liu , Wen-I Hsu , Min-Feng Kao
IPC分类号： H01L21/336
CPC分类号： H01L27/14614 , H01L27/14689
摘要： The present disclosure provides for multiple gate dielectric semiconductor structures and methods of forming such structures. In one embodiment, a method of forming a semiconductor structure includes providing a substrate including a pixel array region, an input/output (I/O) region, and a core region. The method further includes forming a first gate dielectric layer over the pixel array region, forming a second gate dielectric layer over the I/O region, and forming a third gate dielectric layer over the core region, wherein the first gate dielectric layer, the second gate dielectric layer, and the third gate dielectric layer are each formed to be comprised of a different material and to have a different thickness.
摘要翻译：本公开提供了多栅极电介质半导体结构和形成这种结构的方法。在一个实施例中，形成半导体结构的方法包括提供包括像素阵列区域，输入/输出（I / O）区域和核心区域的衬底。该方法还包括在像素阵列区域上形成第一栅极电介质层，在I / O区域上形成第二栅极电介质层，以及在芯区域上形成第三栅极电介质层，其中第一栅极介电层，第二栅极电介质层栅极电介质层和第三栅极电介质层各自形成为由不同的材料构成并且具有不同的厚度。

7. 发明申请

US20130320420A1 CMOS Image Sensors and Methods for Forming the Same 有权
标题翻译： CMOS图像传感器及其形成方法
公开(公告)号：US20130320420A1
公开(公告)日：2013-12-05
申请号：US13615071
申请日：2012-09-13
申请人： Min-Feng Kao , Dun-Nian Yaung , Jen-Cheng Liu , Chun-Chieh Chuang , Hsiao-Hui Tseng , Tzu-Hsuan Hsu
发明人： Min-Feng Kao , Dun-Nian Yaung , Jen-Cheng Liu , Chun-Chieh Chuang , Hsiao-Hui Tseng , Tzu-Hsuan Hsu
IPC分类号： H01L31/02 , H01L31/18
CPC分类号： H01L31/18 , H01L27/1461 , H01L27/14621 , H01L27/14627 , H01L27/1464 , H01L27/14689 , H01L31/02 , H01L31/103 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： A device includes a diode, which includes a first, a second, and a third doped region in a semiconductor substrate. The first doped region is of a first conductivity type, and has a first impurity concentration. The second doped region is of the first conductivity type, and has a second impurity concentration lower than the first impurity concentration. The second doped region encircles the first doped region. The third doped region is of a second conductivity type opposite the first conductivity type, wherein the third doped region overlaps a portion of the first doped region and a portion of the second doped region.
摘要翻译：一种器件包括二极管，其包括半导体衬底中的第一，第二和第三掺杂区域。第一掺杂区域是第一导电类型，并具有第一杂质浓度。第二掺杂区域是第一导电类型，并且具有低于第一杂质浓度的第二杂质浓度。第二掺杂区域包围第一掺杂区域。第三掺杂区域具有与第一导电类型相反的第二导电类型，其中第三掺杂区域与第一掺杂区域的一部分和第二掺杂区域的一部分重叠。

8. 发明授权

US09048162B2 CMOS image sensors and methods for forming the same 有权
标题翻译： CMOS图像传感器及其形成方法
公开(公告)号：US09048162B2
公开(公告)日：2015-06-02
申请号：US13615071
申请日：2012-09-13
申请人： Min-Feng Kao , Dun-Nian Yaung , Jen-Cheng Liu , Chun-Chieh Chuang , Hsiao-Hui Tseng , Tzu-Hsuan Hsu
发明人： Min-Feng Kao , Dun-Nian Yaung , Jen-Cheng Liu , Chun-Chieh Chuang , Hsiao-Hui Tseng , Tzu-Hsuan Hsu
IPC分类号： H01L31/02 , H01L27/146 , H01L31/18 , H01L31/103
CPC分类号： H01L31/18 , H01L27/1461 , H01L27/14621 , H01L27/14627 , H01L27/1464 , H01L27/14689 , H01L31/02 , H01L31/103 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： A device includes a diode, which includes a first, a second, and a third doped region in a semiconductor substrate. The first doped region is of a first conductivity type, and has a first impurity concentration. The second doped region is of the first conductivity type, and has a second impurity concentration lower than the first impurity concentration. The second doped region encircles the first doped region. The third doped region is of a second conductivity type opposite the first conductivity type, wherein the third doped region overlaps a portion of the first doped region and a portion of the second doped region.
摘要翻译：一种器件包括二极管，其包括半导体衬底中的第一，第二和第三掺杂区域。第一掺杂区域是第一导电类型，并具有第一杂质浓度。第二掺杂区域是第一导电类型，并且具有低于第一杂质浓度的第二杂质浓度。第二掺杂区域包围第一掺杂区域。第三掺杂区域具有与第一导电类型相反的第二导电类型，其中第三掺杂区域与第一掺杂区域的一部分和第二掺杂区域的一部分重叠。

9. 发明授权

US08513587B2 Image sensor with anti-reflection layer and method of manufacturing the same 有权
标题翻译：具有防反射层的图像传感器及其制造方法
公开(公告)号：US08513587B2
公开(公告)日：2013-08-20
申请号：US13012067
申请日：2011-01-24
申请人： Tzu-Jui Wang , Hsiao-Hui Tseng , Wei-Cheng Hsu , Dun-Nian Yaung , Jen-Cheng Liu
发明人： Tzu-Jui Wang , Hsiao-Hui Tseng , Wei-Cheng Hsu , Dun-Nian Yaung , Jen-Cheng Liu
IPC分类号： H01L27/00 , H01L31/00 , H01L29/80 , H01L21/02
CPC分类号： H01L27/1464 , H01L27/1461 , H01L27/14629
摘要： An image sensor the image sensor comprising an absorption layer disposed on a silicon substrate, the absorption layer having at least one of SiGe or Ge, and an antireflection layer disposed directly thereon.
摘要翻译：图像传感器包括设置在硅衬底上的吸收层，所述吸收层具有SiGe或Ge中的至少一种，以及直接设置在其上的抗反射层。

10. 发明申请

US20130037890A1 MULTIPLE GATE DIELECTRIC STRUCTURES AND METHODS OF FORMING THE SAME 有权
标题翻译：多栅型电介质结构及其形成方法
公开(公告)号：US20130037890A1
公开(公告)日：2013-02-14
申请号：US13207643
申请日：2011-08-11
申请人： Hsiao-Hui Tseng , Dun-Nian Yaung , Jen-Cheng Liu , Wen-I Hsu , Min-Feng Kao
发明人： Hsiao-Hui Tseng , Dun-Nian Yaung , Jen-Cheng Liu , Wen-I Hsu , Min-Feng Kao
IPC分类号： H01L21/28 , H01L29/78
CPC分类号： H01L27/14614 , H01L27/14689
摘要： The present disclosure provides for multiple gate dielectric semiconductor structures and methods of forming such structures. In one embodiment, a method of forming a semiconductor structure includes providing a substrate including a pixel array region, an input/output (I/O) region, and a core region. The method further includes forming a first gate dielectric layer over the pixel array region, forming a second gate dielectric layer over the I/O region, and forming a third gate dielectric layer over the core region, wherein the first gate dielectric layer, the second gate dielectric layer, and the third gate dielectric layer are each formed to be comprised of a different material and to have a different thickness.
摘要翻译：本公开提供了多栅极电介质半导体结构和形成这种结构的方法。在一个实施例中，形成半导体结构的方法包括提供包括像素阵列区域，输入/输出（I / O）区域和核心区域的衬底。该方法还包括在像素阵列区域上形成第一栅极电介质层，在I / O区域上形成第二栅极电介质层，以及在芯区域上形成第三栅极电介质层，其中第一栅极介电层，第二栅极电介质层栅极电介质层和第三栅极电介质层各自形成为由不同的材料构成并且具有不同的厚度。

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