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1. 发明授权

US06383863B1 Approach to integrate salicide gate for embedded DRAM devices 有权
标题翻译：为嵌入式DRAM设备集成自杀门的方法
公开(公告)号：US06383863B1
公开(公告)日：2002-05-07
申请号：US09963595
申请日：2001-09-27
申请人： Min-Hsiung Chiang , Hsiao-Hui Tseng , Hsien-Yuan Chang , Chung-Wei Chang , Kuo-Chyuan Tzeng
发明人： Min-Hsiung Chiang , Hsiao-Hui Tseng , Hsien-Yuan Chang , Chung-Wei Chang , Kuo-Chyuan Tzeng
IPC分类号： H01L218242
CPC分类号： H01L27/10852 , H01L21/76889 , H01L21/76897 , H01L27/10873 , H01L27/10888 , H01L28/84 , H01L28/90 , H01L29/66545
摘要： A process for integrating the formation of a salicide layer on DRAM word line structures, and on a bit line contact structure, has been developed. The process features selective etch back of the insulator layers embedding the tapered shaped bit line contact, and the tapered shape capacitor structures, exposing top surface portions of polysilicon word line structures. The selective etch back procedure also results in formation of insulator spacers on the sides of the tapered bit line contact, and capacitor structures, allowing a subsequent salicide procedure to form metal suicide layers only on the exposed top surfaces of the DRAM word line, bit line contact, and capacitor structures.
摘要翻译：已经开发了一种用于将自对准硅化物层形成在DRAM字线结构上以及位线接触结构上的过程。该工艺具有嵌入锥形位线接触件的绝缘体层的选择性回蚀和锥形形状电容器结构，暴露多晶硅字线结构的顶表面部分。选择性回蚀程序还导致在锥形位线接触和电容器结构的侧面上形成绝缘体间隔物，并且允许随后的自对准硅化物程序仅在DRAM字线，位线的暴露的顶表面上形成金属硅化物层接触和电容器结构。

2. 发明授权

US06436762B1 Method for improving bit line to capacitor electrical failures on DRAM circuits using a wet etch-back to improve the bit-line-to-capacitor overlay margins 有权
标题翻译：使用湿式回蚀技术改善DRAM电路上电容器电气故障的位线的方法，以改善位线电容器覆盖边界
公开(公告)号：US06436762B1
公开(公告)日：2002-08-20
申请号：US09855238
申请日：2001-05-14
申请人： Kuo-Chyuan Tzeng , Tse-Liang Ying , Min-Hsiung Chiang , Hsiao-Hui Tseng , Chung-Wei Chang
发明人： Kuo-Chyuan Tzeng , Tse-Liang Ying , Min-Hsiung Chiang , Hsiao-Hui Tseng , Chung-Wei Chang
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108 , H01L21/8234 , H01L21/20
CPC分类号： H01L27/10888 , H01L27/10811 , H01L28/91
摘要： A method is described for making capacitor-under-bit line (CUB) DRAM cells with improved overlay margins between bit lines and capacitor top electrodes. After forming FETs for the memory cells, an interpolysilicon oxide (IPO) layer is deposited, and first and second plug contacts are formed in the IPO to the FET source/drain areas for capacitors and bit line contacts, respectively. A capacitor node oxide is deposited, and first openings are etched in which crown capacitor bottom electrodes are formed. After etching back the node oxide a thin interelectrode dielectric layer is formed and a conformal conducting layer is deposited to form capacitor top electrodes. A photoresist mask is used to etch openings in the conducting layer over the second plug contacts, and an isotropic etch is used to recess the openings under the mask to increase the spacing between the capacitor top electrodes and the bit line contacts to improve the overlay margin. The photoresist mask is removed and an interlevel dielectric (ILD) layer is deposited. Bit-line contact openings are etched in the ILD layer aligned over the recessed openings and in the node oxide to the second contact plugs. Bit-line contact plugs are formed extending through the recessed openings, and a first conducting layer is deposited and patterned to form bit lines and to complete the memory cells for the DRAM.
摘要翻译：描述了一种用于制造具有改进的位线和电容器顶部电极之间的覆盖边缘的电容器下位线（CUB）DRAM单元的方法。在形成用于存储单元的FET之后，沉积多晶硅氧化物（IPO）层，并且在IPO中分别将第一和第二插头触点形成到用于电容器和位线触点的FET源极/漏极区域。沉积电容器节点氧化物，并且蚀刻第一开口，其中形成冠电容器底部电极。在蚀刻回节点氧化物之后，形成薄的电极间电介质层，并且淀积保形导电层以形成电容器顶部电极。使用光致抗蚀剂掩模来蚀刻导电层上的第二插头触点上的开口，并且使用各向同性蚀刻来凹陷掩模下方的开口以增加电容器顶部电极和位线触点之间的间隔，以改善覆盖边缘。去除光致抗蚀剂掩模并沉积层间电介质（ILD）层。在ILD层中蚀刻位线接触开口，其在凹入的开口上以及在节点氧化物中对齐到第二接触插塞。位线接触插塞形成为延伸穿过凹入的开口，并且第一导电层被沉积和图案化以形成位线并且完成用于DRAM的存储单元。

3. 发明授权

US06569732B1 Integrated process sequence allowing elimination of polysilicon residue and silicon damage during the fabrication of a buried stack capacitor structure in a SRAM cell 有权
标题翻译：在SRAM单元中制造埋层堆叠电容器结构期间，能够消除多晶硅残渣和硅损伤的集成工艺顺序
公开(公告)号：US06569732B1
公开(公告)日：2003-05-27
申请号：US10262926
申请日：2002-10-02
申请人： Min-Hsiung Chiang , Chung-Wei Chang , Kuo-Chyuan Tzeng
发明人： Min-Hsiung Chiang , Chung-Wei Chang , Kuo-Chyuan Tzeng
IPC分类号： H01L218242
CPC分类号： H01L28/40 , H01L27/11
摘要： A process sequence for fabricating a buried stack capacitor structure, to be used as a component in a memory cell such as a one transistor SRAM cell, has been developed. The process features formation of a self-aligned opening used to accommodate a subsequent buried stack capacitor structure, with the self-aligned opening defined via selective dry and wet etch procedures, employed to avoid damage to regions of a semiconductor substrate which become exposed at the conclusion of the definition procedure. In addition the process sequence allows a smooth, top surface topography to be present during definition of a polysilicon storage node structure in the self-aligned opening, allowing unwanted portions of polysilicon to be easily removed, reducing the risk of polysilicon stringers.
摘要翻译：已经开发了用于制造用作诸如一晶体管SRAM单元的存储单元中的组件的掩埋叠层电容器结构的工艺顺序。该工艺特征是形成自对准开口，用于容纳随后的掩埋堆叠电容器结构，其中采用经由选择性干法和湿式蚀刻工艺限定的自对准开口，以避免损坏在该位置处露出的半导体衬底的区域定义程序的结论。此外，工艺顺序允许在自对准开口中的多晶硅存储节点结构的定义期间存在平滑的顶表面形貌，从而允许容易去除多晶硅的不希望的部分，从而降低多晶硅桁架的风险。

4. 发明授权

US06613690B1 Approach for forming a buried stack capacitor structure featuring reduced polysilicon stringers 有权
标题翻译：用于形成具有减少的多晶硅桁架的掩埋堆叠电容器结构的方法
公开(公告)号：US06613690B1
公开(公告)日：2003-09-02
申请号：US10197318
申请日：2002-07-17
申请人： Chung-Wei Chang , Kuo-Chyuan Tzeng , Chen-Jong Wang , Min-Hsiang Chiang , Chi-Hsing Lo
发明人： Chung-Wei Chang , Kuo-Chyuan Tzeng , Chen-Jong Wang , Min-Hsiang Chiang , Chi-Hsing Lo
IPC分类号： H01L21302
CPC分类号： H01L27/1087 , H01L21/32139 , H01L27/10835 , H01L28/91
摘要： A process for forming a buried stack capacitor structure in a recessed region of a shallow trench isolation (STI) region, has been developed. The process features a unique sequence of procedures eliminating possible polysilicon stringers or residuals which if left remaining would result in leakage or shorts between conductive elements. The unique sequence of procedures include: deposition of a silicon oxide layer on the polysilicon layer from which the storage node structure will be defined from; photoresist plugs used to protect the portions of the silicon oxide and the underlying polysilicon layer located in the recessed region, during definition of the polysilicon storage node structure; and definition of the polysilicon storage node structure via a wet etch procedure, using the silicon oxide layer for protection of the underlying polysilicon storage node structure.
摘要翻译：已经开发了在浅沟槽隔离（STI）区域的凹陷区域中形成掩埋堆叠电容器结构的工艺。该方法具有唯一的程序序列，可以消除可能的多晶硅桁条或残余物，如果留下剩余物会导致导电元件之间的泄漏或短路。独特的程序顺序包括：在多晶硅层上沉积氧化硅层，从其上定义存储节点结构; 用于在多晶硅存储节点结构的定义期间用于保护位于凹陷区域中的氧化硅部分和下面的多晶硅层的光阻胶塞; 以及通过湿蚀刻程序定义多晶硅存储节点结构，使用氧化硅层来保护下面的多晶硅存储节点结构。

5. 发明授权

US06638813B1 Method of forming a composite spacer to eliminate polysilicon stringers between elements in a pseudo SRAM cell 有权
标题翻译：形成复合间隔物以消除伪SRAM单元中的元件之间的多晶硅桁条的方法
公开(公告)号：US06638813B1
公开(公告)日：2003-10-28
申请号：US10059825
申请日：2002-01-29
申请人： Kuo-Chyuan Tzeng , Chen-Jong Wang , Chung-Wei Chang , Wen-Chuan Chiang , Wen-Cheng Chen , Kuo-Ching Huang
发明人： Kuo-Chyuan Tzeng , Chen-Jong Wang , Chung-Wei Chang , Wen-Chuan Chiang , Wen-Cheng Chen , Kuo-Ching Huang
IPC分类号： H01L218242
CPC分类号： H01L28/60 , H01L21/31111 , H01L21/31116 , H01L21/32137 , H01L21/76232 , H01L27/11
摘要： A process for forming a composite insulator spacer on the sides of a buried stack capacitor structure, wherein the buried stack capacitor structure is located overlying a portion of an insulator filled, shallow trench isolation (STI) region, has been developed. A thin silicon nitride spacer is first formed on the sides of the completed buried stack capacitor structure, followed by deposition of a silicon oxide layer. An anisotropic dry etch procedure is next employed removing a top portion of the silicon oxide layer, and resulting in a partially defined silicon oxide spacer. A critical wet etch procedure is next used to remove the bottom portion of the silicon oxide layer, defining the final silicon oxide spacer of the composite insulator spacer, now comprised of a silicon oxide spacer on an underlying silicon nitride spacer. The wet etch procedure allows a gradual slope to be created at the composite insulator spacer—STI region interface, reducing the risk of leaving, or forming polysilicon residuals or stringers on the underlying surface, which can occur during definition of a MOSFET gate structure. The elimination of the polysilicon stringers reduces the risk of leakage between SRAM cell elements, such as buried stack capacitor structures, and MOSFET devices.
摘要翻译：已经开发了一种用于在掩埋叠层电容器结构的侧面上形成复合绝缘体间隔物的方法，其中埋层叠层电容器结构位于绝缘体填充的浅沟槽隔离（STI）区域的一部分上方。首先在完成的掩埋堆叠电容器结构的侧面上形成薄的氮化硅间隔物，然后沉积氧化硅层。接下来，使用各向异性干蚀刻工艺去除氧化硅层的顶部，并产生部分限定的氧化硅间隔物。接下来使用关键的湿法蚀刻工艺来去除氧化硅层的底部，限定复合绝缘垫片的最终氧化硅隔离物，现在由下面的氮化硅间隔物上的氧化硅间隔物构成。湿蚀刻工艺允许在复合绝缘体间隔件-ST区域界面处产生逐渐的斜率，从而降低在MOSFET栅极结构的定义期间可能发生的在下表面上的离开风险或形成多晶硅残余物或桁条。多晶硅桁架的消除降低了诸如掩埋堆叠电容器结构的SRAM单元元件和MOSFET器件之间的泄漏的风险。

6. 发明授权

US06661050B2 Memory cell structure with trench capacitor and method for fabrication thereof 有权
标题翻译：具有沟槽电容器的存储单元结构及其制造方法
公开(公告)号：US06661050B2
公开(公告)日：2003-12-09
申请号：US10102280
申请日：2002-03-20
申请人： Kuo-Chyuan Tzeng , Chen-Jong Wang , Chung-Wei Chang
发明人： Kuo-Chyuan Tzeng , Chen-Jong Wang , Chung-Wei Chang
IPC分类号： H01L27108
CPC分类号： H01L27/10861 , H01L27/10829 , H01L27/11 , H01L29/66181 , Y10S257/906
摘要： Within both a memory cell structure and a method for fabricating the memory cell structure there is employed a storage capacitor formed within a trench adjoining an active region of a semiconductor substrate. Within the memory cell structure and the method for fabrication thereof, both the active region of the semiconductor substrate and the trench are contained within a doped well within the semiconductor substrate.
摘要翻译：在存储单元结构和用于制造存储单元结构的方法中，采用在与半导体衬底的有源区相邻的沟槽内形成的存储电容器。在存储单元结构及其制造方法中，半导体衬底的有源区和沟槽都包含在半导体衬底内的掺杂阱中。

7. 发明授权

US06661049B2 Microelectronic capacitor structure embedded within microelectronic isolation region 有权
公开(公告)号：US06661049B2
公开(公告)日：2003-12-09
申请号：US09947793
申请日：2001-09-06
申请人： Kuo-Chyuan Tzeng , Chen-Jong Wang , Chung-Wei Chang
发明人： Kuo-Chyuan Tzeng , Chen-Jong Wang , Chung-Wei Chang
IPC分类号： H01L29772
CPC分类号： H01L27/10861 , H01L27/10829 , H01L27/10867 , H01L28/91 , H01L29/945
摘要： Within a method for fabricating a capacitor structure, and a capacitor structure fabricated employing the method, there is formed within an isolation region adjoining an active region of a semiconductor substrate a laterally asymmetric trench which leaves exposed an upper sidewall portion of the active region of the semiconductor substrate. There is then formed within the laterally asymmetric trench a capacitor node layer which contacts the exposed upper sidewall portion of the active region of the semiconductor substrate and extends above the active region of the semiconductor substrate. The capacitor may be a storage capacitor with increased capacitance fabricated within a memory cell structure of decreased dimensions.

8. 发明授权

US06833578B1 Method and structure improving isolation between memory cell passing gate and capacitor 有权
标题翻译：存储单元通过栅极和电容器之间的隔离方法和结构
公开(公告)号：US06833578B1
公开(公告)日：2004-12-21
申请号：US10733216
申请日：2003-12-11
申请人： Kuo-Chi Tu , Chun-Yao Chen , Huey-Chi Chu , Chung-Wei Chang , Tien-Lu Lin , Kuo-Ching Huang , Wen-Cheng Chen , Tsung-Hsun Huang , Hsiao-Hui Tseng
发明人： Kuo-Chi Tu , Chun-Yao Chen , Huey-Chi Chu , Chung-Wei Chang , Tien-Lu Lin , Kuo-Ching Huang , Wen-Cheng Chen , Tsung-Hsun Huang , Hsiao-Hui Tseng
IPC分类号： H01L27108
CPC分类号： H01L28/57 , H01L27/11 , H01L28/90
摘要： A memory cell comprising a capacitor having a dielectric layer interposing first and second vertically disposed electrodes, an insulating lining located over the capacitor, and a transistor gate extension passing over the capacitor. A spacer isolates an end of one of the capacitor electrodes from the transistor gate extension. In one embodiment, the spacer includes a first non-planar profile configured to engage a second non-planar profile comprising ends of the one of the capacitor electrodes and the insulating lining.
摘要翻译：一种存储单元，包括具有插入第一和第二垂直设置的电极的介电层的电容器，位于电容器上方的绝缘衬垫，以及通过电容器的晶体管栅极延伸。间隔件将电容器电极之一的端部与晶体管栅极延伸部隔离。在一个实施例中，间隔件包括构造成接合包括电容器电极之一和绝缘衬里的端部的第二非平面轮廓的第一非平面轮廓。

9. 发明授权

US08368160B2 Image sensing device and fabrication thereof 有权
标题翻译：图像感测装置及其制造
公开(公告)号：US08368160B2
公开(公告)日：2013-02-05
申请号：US12898419
申请日：2010-10-05
申请人： Chung-Wei Chang , Fang-Ming Huang , Chi-Shao Lin , Yu-Ping Hu
发明人： Chung-Wei Chang , Fang-Ming Huang , Chi-Shao Lin , Yu-Ping Hu
IPC分类号： H01L31/042
CPC分类号： H01L31/18 , H01L27/14621 , H01L27/1463 , H01L27/14645 , H01L27/14689
摘要： An image sensing device is disclosed, including an epitaxy layer having the a conductivity type, including a first pixel area corresponding to a first incident light, a second pixel area corresponding to a second incident light, and a third pixel area corresponding to a third incident light, wherein the wavelength of the first incident light is longer than that of the second incident light and the wavelength of the second incident light is longer than that of the third incident light. A photodiode is disposed in an upper portion of the epitaxy layer, and a first deep well for reducing pixel-to-pixel talk of the image sensing device is disposed in a lower portion of the epitaxy layer in the second pixel area and the third pixel area, wherein at least a portion of the epitaxy layer in first pixel area does not include the first deep well.
摘要翻译：公开了一种图像感测装置，包括具有导电类型的外延层，包括对应于第一入射光的第一像素区域，对应于第二入射光的第二像素区域和对应于第三入射光的第三像素区域光，其中第一入射光的波长比第二入射光的波长长，第二入射光的波长比第三入射光的波长长。光电二极管设置在外延层的上部，并且用于减少图像感测装置的像素到像素的通话的第一深阱设置在第二像素区域中的外延层的下部和第三像素区域，其中第一像素区域中的外延层的至少一部分不包括第一深孔。

10. 发明申请

US20110278687A1 BACKSIDE-ILLUMINATED SENSOR WITH NOISE REDUCTION 审中-公开
标题翻译：带噪声的背光照明传感器
公开(公告)号：US20110278687A1
公开(公告)日：2011-11-17
申请号：US12781785
申请日：2010-05-17
申请人： Fang-Ming Huang , Ping-Hung Yin , Chung-Wei Chang
发明人： Fang-Ming Huang , Ping-Hung Yin , Chung-Wei Chang
IPC分类号： H01L31/0232 , H01L31/00
CPC分类号： H01L27/14643 , H01L27/14621 , H01L27/14627 , H01L27/14636 , H01L27/1464 , H01L27/14641 , H01L28/86
摘要： A backside-illuminated sensor includes a substrate, at least one lens and at least one pixel structure. The substrate has a front surface and a backside surface, and the lens is formed on the backside surface of the substrate and the pixel structure is formed on a pixel area included in the front surface of the substrate, where a projected area of the pixel area on the backside surface in a thickness direction of the substrate is covered by the lens. The pixel structure includes a first power node for receiving a first supply voltage, a second power node for receiving a second supply voltage different from the first supply voltage, a sensing element and a capacitor for noise reduction. The sensing element generates a sensing signal according to an incident luminance from the lens.
摘要翻译：背面照明传感器包括基底，至少一个透镜和至少一个像素结构。基板具有前表面和背面，透镜形成在基板的背面，并且像素结构形成在基板前表面的像素区域上，像素区域的投影面积在基板的厚度方向的背面上被透镜覆盖。像素结构包括用于接收第一电源电压的第一电源节点，用于接收不同于第一电源电压的第二电源电压的第二电源节点，用于降噪的电容器。感测元件根据来自透镜的入射亮度产生感测信号。

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