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1. 发明授权

US07092043B2 Fully integrated tuner architecture 有权
标题翻译：完全集成的调谐器架构
公开(公告)号：US07092043B2
公开(公告)日：2006-08-15
申请号：US09439101
申请日：1999-11-12
申请人： Pieter Vorenkamp , Klaas Bult , Frank Carr , Christopher M. Ward , Ralph Duncan , Tom W. Kwan , James Y. C. Chang , Haideh Khorramabadi
发明人： Pieter Vorenkamp , Klaas Bult , Frank Carr , Christopher M. Ward , Ralph Duncan , Tom W. Kwan , James Y. C. Chang , Haideh Khorramabadi
IPC分类号： H04N5/455
CPC分类号： H03D3/18 , H01F17/0006 , H01F17/0013 , H01F27/34 , H01F27/40 , H01F27/42 , H01F2017/0053 , H01F2021/125 , H01L23/5227 , H01L27/0248 , H01L27/0251 , H01L27/08 , H01L2924/0002 , H01L2924/3011 , H03B5/04 , H03B5/364 , H03D7/161 , H03D7/18 , H03F1/26 , H03F1/3211 , H03F3/195 , H03F3/45183 , H03F3/45188 , H03F3/68 , H03F3/72 , H03F2200/111 , H03F2200/294 , H03F2200/372 , H03F2200/447 , H03F2200/63 , H03F2203/45264 , H03F2203/45286 , H03G1/0023 , H03G1/0029 , H03G3/3052 , H03H7/25 , H03H11/04 , H03H11/1291 , H03H11/53 , H03H11/54 , H03H19/004 , H03J1/0075 , H03J3/04 , H03J3/08 , H03J3/185 , H03J2200/10 , H03L7/10 , H03L7/183 , H03L7/23 , H03L2207/06 , H01L2924/00
摘要： An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver.
摘要翻译：描述了基本上在单个CMOS集成电路上实现的具有信道选择和图像抑制的集成接收机。接收机前端提供可编程衰减和可编程增益低噪声放大器。频率转换电路有利地使用集成到衬底上的LC滤波器与图像抑制混合器结合，以提供足够的图像频率抑制。过滤器调谐和电感Q补偿温度在芯片上执行。滤波器采用多轨螺旋电感。使用本地振荡器调整滤波器以调整替代滤波器，以及滤波器组件值期间的频率缩放与被调谐的滤波器的频率缩放。结合滤波，频率规划提供了额外的镜像抑制。片上本地振荡器信号产生方法的有利选择是通过PLL带外本地振荡和通过频带本地振荡器的直接合成。 PLL中的VCO使用控制电路居中，使调谐电容范围居中。差分晶体振荡器有利地用作频率参考。差分信号传输有利地用于整个接收机。

2. 发明授权

US08045066B2 Fully integrated tuner architecture 有权
标题翻译：完全集成的调谐器架构
公开(公告)号：US08045066B2
公开(公告)日：2011-10-25
申请号：US12883575
申请日：2010-09-16
申请人： Pieter Vorenkamp , Klaas Bult , Frank Carr , Christopher M. Ward , Ralph Duncan , Tom W. Kwan , James Y. C. Chang , Haideh Khorramabadi
发明人： Pieter Vorenkamp , Klaas Bult , Frank Carr , Christopher M. Ward , Ralph Duncan , Tom W. Kwan , James Y. C. Chang , Haideh Khorramabadi
IPC分类号： H04N5/455 , H04N5/44
CPC分类号： H03D3/18 , H01F17/0006 , H01F17/0013 , H01F27/34 , H01F27/40 , H01F27/42 , H01F2017/0053 , H01F2021/125 , H01L23/5227 , H01L27/0248 , H01L27/0251 , H01L27/08 , H01L2924/0002 , H01L2924/3011 , H03B5/04 , H03B5/364 , H03D7/161 , H03D7/18 , H03F1/26 , H03F1/3211 , H03F3/195 , H03F3/45183 , H03F3/45188 , H03F3/68 , H03F3/72 , H03F2200/111 , H03F2200/294 , H03F2200/372 , H03F2200/447 , H03F2200/63 , H03F2203/45264 , H03F2203/45286 , H03G1/0023 , H03G1/0029 , H03G3/3052 , H03H7/25 , H03H11/04 , H03H11/1291 , H03H11/53 , H03H11/54 , H03H19/004 , H03J1/0075 , H03J3/04 , H03J3/08 , H03J3/185 , H03J2200/10 , H03L7/10 , H03L7/183 , H03L7/23 , H03L2207/06 , H01L2924/00
摘要： An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver.
摘要翻译：描述了基本上在单个CMOS集成电路上实现的具有信道选择和图像抑制的集成接收机。接收机前端提供可编程衰减和可编程增益低噪声放大器。频率转换电路有利地使用集成到衬底上的LC滤波器与图像抑制混合器结合，以提供足够的图像频率抑制。过滤器调谐和电感Q补偿温度在芯片上执行。滤波器采用多轨螺旋电感。使用本地振荡器调整滤波器以调整替代滤波器，以及滤波器组件值期间的频率缩放与被调谐的滤波器的频率缩放。结合滤波，频率规划提供了额外的镜像抑制。片上本地振荡器信号产生方法的有利选择是通过PLL带外本地振荡和通过频带本地振荡器的直接合成。 PLL中的VCO使用控制电路居中，使调谐电容范围居中。差分晶体振荡器有利地用作频率参考。差分信号传输有利地用于整个接收机。

3. 发明授权

US07821581B2 Fully integrated tuner architecture 有权
标题翻译：完全集成的调谐器架构
公开(公告)号：US07821581B2
公开(公告)日：2010-10-26
申请号：US12219925
申请日：2008-07-30
申请人： Pieter Vorenkamp , Klaas Bult , Frank Carr , Christopher M. Ward , Ralph Duncan , Tom W. Kwan , James Y. C. Chang , Haideh Khorramabadi
发明人： Pieter Vorenkamp , Klaas Bult , Frank Carr , Christopher M. Ward , Ralph Duncan , Tom W. Kwan , James Y. C. Chang , Haideh Khorramabadi
IPC分类号： H04N5/455
CPC分类号： H03D3/18 , H01F17/0006 , H01F17/0013 , H01F27/34 , H01F27/40 , H01F27/42 , H01F2017/0053 , H01F2021/125 , H01L23/5227 , H01L27/0248 , H01L27/0251 , H01L27/08 , H01L2924/0002 , H01L2924/3011 , H03B5/04 , H03B5/364 , H03D7/161 , H03D7/18 , H03F1/26 , H03F1/3211 , H03F3/195 , H03F3/45183 , H03F3/45188 , H03F3/68 , H03F3/72 , H03F2200/111 , H03F2200/294 , H03F2200/372 , H03F2200/447 , H03F2200/63 , H03F2203/45264 , H03F2203/45286 , H03G1/0023 , H03G1/0029 , H03G3/3052 , H03H7/25 , H03H11/04 , H03H11/1291 , H03H11/53 , H03H11/54 , H03H19/004 , H03J1/0075 , H03J3/04 , H03J3/08 , H03J3/185 , H03J2200/10 , H03L7/10 , H03L7/183 , H03L7/23 , H03L2207/06 , H01L2924/00
摘要： An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver.
摘要翻译：描述了基本上在单个CMOS集成电路上实现的具有信道选择和图像抑制的集成接收机。接收机前端提供可编程衰减和可编程增益低噪声放大器。频率转换电路有利地使用集成到衬底上的LC滤波器与图像抑制混合器结合，以提供足够的图像频率抑制。过滤器调谐和电感Q补偿温度在芯片上执行。滤波器采用多轨螺旋电感。使用本地振荡器调整滤波器以调整替代滤波器，以及滤波器组件值期间的频率缩放与被调谐的滤波器的频率缩放。结合滤波，频率规划提供了额外的镜像抑制。片上本地振荡器信号产生方法的有利选择是通过PLL带外本地振荡和通过频带本地振荡器的直接合成。 PLL中的VCO使用控制电路居中，使调谐电容范围居中。差分晶体振荡器有利地用作频率参考。差分信号传输有利地用于整个接收机。

4. 发明授权

US07423699B2 Fully integrated tuner architecture 有权
标题翻译：完全集成的调谐器架构
公开(公告)号：US07423699B2
公开(公告)日：2008-09-09
申请号：US11393899
申请日：2006-03-31
申请人： Pieter Vorenkamp , Klaas Bult , Frank Carr , Christopher M. Ward , Ralph Duncan , Tom W. Kwan , James Y. C. Chang , Haideh Khorramabadi
发明人： Pieter Vorenkamp , Klaas Bult , Frank Carr , Christopher M. Ward , Ralph Duncan , Tom W. Kwan , James Y. C. Chang , Haideh Khorramabadi
IPC分类号： H04N5/455
CPC分类号： H03D3/18 , H01F17/0006 , H01F17/0013 , H01F27/34 , H01F27/40 , H01F27/42 , H01F2017/0053 , H01F2021/125 , H01L23/5227 , H01L27/0248 , H01L27/0251 , H01L27/08 , H01L2924/0002 , H01L2924/3011 , H03B5/04 , H03B5/364 , H03D7/161 , H03D7/18 , H03F1/26 , H03F1/3211 , H03F3/195 , H03F3/45183 , H03F3/45188 , H03F3/68 , H03F3/72 , H03F2200/111 , H03F2200/294 , H03F2200/372 , H03F2200/447 , H03F2200/63 , H03F2203/45264 , H03F2203/45286 , H03G1/0023 , H03G1/0029 , H03G3/3052 , H03H7/25 , H03H11/04 , H03H11/1291 , H03H11/53 , H03H11/54 , H03H19/004 , H03J1/0075 , H03J3/04 , H03J3/08 , H03J3/185 , H03J2200/10 , H03L7/10 , H03L7/183 , H03L7/23 , H03L2207/06 , H01L2924/00
摘要： An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver.
摘要翻译：描述了基本上在单个CMOS集成电路上实现的具有信道选择和图像抑制的集成接收机。接收机前端提供可编程衰减和可编程增益低噪声放大器。频率转换电路有利地使用集成到衬底上的LC滤波器与图像抑制混合器结合，以提供足够的图像频率抑制。过滤器调谐和电感Q补偿温度在芯片上执行。滤波器采用多轨螺旋电感。使用本地振荡器调整滤波器以调整替代滤波器，以及滤波器组件值期间的频率缩放与被调谐的滤波器的频率缩放。结合滤波，频率规划提供了额外的镜像抑制。片上本地振荡器信号产生方法的有利选择是通过PLL带外本地振荡和通过频带本地振荡器的直接合成。 PLL中的VCO使用控制电路居中，使调谐电容范围居中。差分晶体振荡器有利地用作频率参考。差分信号传输有利地用于整个接收机。

5. 发明申请

US20080284919A1 Fully integrated tuner architecture 有权
标题翻译：完全集成的调谐器架构
公开(公告)号：US20080284919A1
公开(公告)日：2008-11-20
申请号：US12219925
申请日：2008-07-30
申请人： Pieter Vorenkamp , Klaas Bult , Frank Carr , Christopher M. Ward , Ralph Duncan , Tom W. Kwan , James Y.C. Chang , Haideh Khorramabadi
发明人： Pieter Vorenkamp , Klaas Bult , Frank Carr , Christopher M. Ward , Ralph Duncan , Tom W. Kwan , James Y.C. Chang , Haideh Khorramabadi
IPC分类号： H04N5/50 , H04N5/44
CPC分类号： H03D3/18 , H01F17/0006 , H01F17/0013 , H01F27/34 , H01F27/40 , H01F27/42 , H01F2017/0053 , H01F2021/125 , H01L23/5227 , H01L27/0248 , H01L27/0251 , H01L27/08 , H01L2924/0002 , H01L2924/3011 , H03B5/04 , H03B5/364 , H03D7/161 , H03D7/18 , H03F1/26 , H03F1/3211 , H03F3/195 , H03F3/45183 , H03F3/45188 , H03F3/68 , H03F3/72 , H03F2200/111 , H03F2200/294 , H03F2200/372 , H03F2200/447 , H03F2200/63 , H03F2203/45264 , H03F2203/45286 , H03G1/0023 , H03G1/0029 , H03G3/3052 , H03H7/25 , H03H11/04 , H03H11/1291 , H03H11/53 , H03H11/54 , H03H19/004 , H03J1/0075 , H03J3/04 , H03J3/08 , H03J3/185 , H03J2200/10 , H03L7/10 , H03L7/183 , H03L7/23 , H03L2207/06 , H01L2924/00
摘要： An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver.
摘要翻译：描述了基本上在单个CMOS集成电路上实现的具有信道选择和图像抑制的集成接收机。接收机前端提供可编程衰减和可编程增益低噪声放大器。频率转换电路有利地使用集成到衬底上的LC滤波器与图像抑制混合器结合，以提供足够的图像频率抑制。过滤器调谐和电感Q补偿温度在芯片上执行。滤波器采用多轨螺旋电感。使用本地振荡器调整滤波器以调整替代滤波器，以及滤波器组件值期间的频率缩放与被调谐的滤波器的频率缩放。结合滤波，频率规划提供了额外的镜像抑制。片上本地振荡器信号产生方法的有利选择是通过PLL带外本地振荡和通过频带本地振荡器的直接合成。 PLL中的VCO使用控制电路居中，使调谐电容范围居中。差分晶体振荡器有利地用作频率参考。差分信号传输有利地用于整个接收机。

6. 发明申请

US20110067083A1 Fully Integrated Tuner Architecture 有权
标题翻译：完全集成的调谐器架构
公开(公告)号：US20110067083A1
公开(公告)日：2011-03-17
申请号：US12883575
申请日：2010-09-16
申请人： Pieter Vorenkamp , Klaas Bult , Frank Carr , Christopher M. Ward , Ralph Duncan , Tom W. Kwan , James Y.C. Chang , Haideh Khorramabadi
发明人： Pieter Vorenkamp , Klaas Bult , Frank Carr , Christopher M. Ward , Ralph Duncan , Tom W. Kwan , James Y.C. Chang , Haideh Khorramabadi
IPC分类号： H04N5/50 , H04N7/173
CPC分类号： H03D3/18 , H01F17/0006 , H01F17/0013 , H01F27/34 , H01F27/40 , H01F27/42 , H01F2017/0053 , H01F2021/125 , H01L23/5227 , H01L27/0248 , H01L27/0251 , H01L27/08 , H01L2924/0002 , H01L2924/3011 , H03B5/04 , H03B5/364 , H03D7/161 , H03D7/18 , H03F1/26 , H03F1/3211 , H03F3/195 , H03F3/45183 , H03F3/45188 , H03F3/68 , H03F3/72 , H03F2200/111 , H03F2200/294 , H03F2200/372 , H03F2200/447 , H03F2200/63 , H03F2203/45264 , H03F2203/45286 , H03G1/0023 , H03G1/0029 , H03G3/3052 , H03H7/25 , H03H11/04 , H03H11/1291 , H03H11/53 , H03H11/54 , H03H19/004 , H03J1/0075 , H03J3/04 , H03J3/08 , H03J3/185 , H03J2200/10 , H03L7/10 , H03L7/183 , H03L7/23 , H03L2207/06 , H01L2924/00
摘要： An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver.
摘要翻译：描述了基本上在单个CMOS集成电路上实现的具有信道选择和图像抑制的集成接收机。接收机前端提供可编程衰减和可编程增益低噪声放大器。频率转换电路有利地使用集成到衬底上的LC滤波器与图像抑制混合器结合，以提供足够的图像频率抑制。过滤器调谐和电感Q补偿温度在芯片上执行。滤波器采用多轨螺旋电感。使用本地振荡器调整滤波器以调整替代滤波器，以及滤波器组件值期间的频率缩放与被调谐的滤波器的频率缩放。结合滤波，频率规划提供了额外的镜像抑制。片上本地振荡器信号产生方法的有利选择是通过PLL带外本地振荡和通过频带本地振荡器的直接合成。 PLL中的VCO使用控制电路居中，使调谐电容范围居中。差分晶体振荡器有利地用作频率参考。差分信号传输有利地用于整个接收机。

7. 发明申请

US20070077908A1 Fully integrated tuner architecture 有权
标题翻译：完全集成的调谐器架构
公开(公告)号：US20070077908A1
公开(公告)日：2007-04-05
申请号：US11393899
申请日：2006-03-31
申请人： Pieter Vorenkamp , Klaas Bult , Frank Carr , Christopher Ward , Ralph Duncan , Tom Kwan , James Chang , Haideh Khorramabadi
发明人： Pieter Vorenkamp , Klaas Bult , Frank Carr , Christopher Ward , Ralph Duncan , Tom Kwan , James Chang , Haideh Khorramabadi
IPC分类号： H04B1/10 , H04B1/26 , H04N5/455
CPC分类号： H03D3/18 , H01F17/0006 , H01F17/0013 , H01F27/34 , H01F27/40 , H01F27/42 , H01F2017/0053 , H01F2021/125 , H01L23/5227 , H01L27/0248 , H01L27/0251 , H01L27/08 , H01L2924/0002 , H01L2924/3011 , H03B5/04 , H03B5/364 , H03D7/161 , H03D7/18 , H03F1/26 , H03F1/3211 , H03F3/195 , H03F3/45183 , H03F3/45188 , H03F3/68 , H03F3/72 , H03F2200/111 , H03F2200/294 , H03F2200/372 , H03F2200/447 , H03F2200/63 , H03F2203/45264 , H03F2203/45286 , H03G1/0023 , H03G1/0029 , H03G3/3052 , H03H7/25 , H03H11/04 , H03H11/1291 , H03H11/53 , H03H11/54 , H03H19/004 , H03J1/0075 , H03J3/04 , H03J3/08 , H03J3/185 , H03J2200/10 , H03L7/10 , H03L7/183 , H03L7/23 , H03L2207/06 , H01L2924/00
摘要： An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver.
摘要翻译：描述了基本上在单个CMOS集成电路上实现的具有信道选择和图像抑制的集成接收机。接收机前端提供可编程衰减和可编程增益低噪声放大器。频率转换电路有利地使用集成到衬底上的LC滤波器与图像抑制混合器结合，以提供足够的图像频率抑制。过滤器调谐和电感Q补偿温度在芯片上执行。滤波器采用多轨螺旋电感。使用本地振荡器调整滤波器以调整替代滤波器，以及滤波器组件值期间的频率缩放与被调谐的滤波器的频率缩放。结合滤波，频率规划提供了额外的镜像抑制。片上本地振荡器信号产生方法的有利选择是通过PLL带外本地振荡和通过频带本地振荡器的直接合成。 PLL中的VCO使用控制电路居中，使调谐电容范围居中。差分晶体振荡器有利地用作频率参考。差分信号传输有利地用于整个接收机。

8. 发明授权

US07696823B2 System and method for linearizing a CMOS differential pair 有权
标题翻译：用于线性化CMOS差分对的系统和方法
公开(公告)号：US07696823B2
公开(公告)日：2010-04-13
申请号：US11889939
申请日：2007-08-17
申请人： Haideh Khorramabadi
发明人： Haideh Khorramabadi
IPC分类号： H03F3/45
CPC分类号： H03F1/3211 , H01F17/0013 , H01F2017/0053 , H01L23/5227 , H01L2924/0002 , H01L2924/3011 , H03B5/1209 , H03B5/1212 , H03B5/1228 , H03F1/52 , H03F1/523 , H03F3/191 , H03F3/195 , H03F3/24 , H03F3/45188 , H03F3/45192 , H03F3/4521 , H03F3/45475 , H03F2200/336 , H03F2200/451 , H03F2200/453 , H03F2200/456 , H03F2203/45241 , H03F2203/45318 , H03F2203/45356 , H03F2203/45366 , H03F2203/45466 , H03F2203/45641 , H03F2203/45702 , H03F2203/45704 , H03H7/24 , H03H11/04 , H03H11/1291 , H03H11/24 , H03H11/54 , H03L7/10 , H03L7/18 , H01L2924/00
摘要： An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. LC filters integrated onto the substrate in conjunction with image reject mixers provide image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. Active filters utilize multi track spiral inductors with shields to increase circuit Q. The filters incorporate a gain stage that provides improved dynamic range through the use of cross coupled auxiliary differential pair CMOS amplifiers to cancel distortion in a main linearized differential pair amplifier. Frequency planning provides additional image rejection. Local oscillator signal generation methods on chip reduce distortion. A PLL generates needed out of band LO signals. Direct synthesis generates in band LO signals. PLL VCOs are centered automatically. A differential crystal oscillator provides a frequency reference. Differential signal transmission throughout the receiver is used. ESD protection is provided by a pad ring and ESD clamping structure. Shunts utilize a gate boosting at each pin to discharge ESD build up. An IF VGA utilizes distortion cancellation achieved with cross coupled differential pair amplifiers having their Vds dynamically modified in conjunction with current steering of the differential pairs sources.
摘要翻译：具有通道选择和图像抑制的集成接收器基本上在单个CMOS集成电路上实现。接收机前端提供可编程衰减和可编程增益低噪声放大器。与图像抑制混合器一起集成到衬底上的LC滤波器提供图像频率抑制。过滤器调谐和电感Q补偿温度在芯片上执行。有源滤波器利用具有屏蔽的多轨螺旋电感器来增加电路Q.滤波器包括增益级，其通过使用交叉耦合辅助差分对CMOS放大器来消除主线性化差分对放大器中的失真而提供改进的动态范围。频率规划提供额外的镜像抑制。本地振荡器信号产生方法在芯片上减少失真。 PLL产生所需的带外LO信号。直接合成产生带内LO信号。 PLL VCO自动居中。差分晶体振荡器提供频率参考。使用整个接收机的差分信号传输。 ESD保护由衬垫环和ESD夹紧结构提供。分流器利用每个引脚上的门极升压来放电ESD积聚。 IF VGA利用交叉耦合差分对放大器实现的失真消除，其具有与差分对源的电流转向结合动态修改的Vds。

9. 发明授权

US07276970B2 System and method for linearizing a CMOS differential pair 有权
标题翻译：用于线性化CMOS差分对的系统和方法
公开(公告)号：US07276970B2
公开(公告)日：2007-10-02
申请号：US11131281
申请日：2005-05-18
申请人： Haideh Khorramabadi
发明人： Haideh Khorramabadi
IPC分类号： H03F3/45
CPC分类号： H03L7/23 , H01F17/0006 , H01F17/0013 , H01F2017/0053 , H01F2021/125 , H01L23/5227 , H01L27/0248 , H01L27/08 , H01L2924/0002 , H01L2924/3011 , H03B5/1215 , H03B5/1228 , H03B5/364 , H03B2201/025 , H03B2201/0266 , H03D7/161 , H03D7/18 , H03F1/3211 , H03F1/52 , H03F3/191 , H03F3/45183 , H03F3/45188 , H03F3/45475 , H03F2200/294 , H03F2203/45318 , H03F2203/45704 , H03G1/0029 , H03H11/1291 , H03J1/0075 , H03J3/04 , H03J3/08 , H03J3/185 , H03J2200/10 , H03L1/023 , H03L7/10 , H03L7/18 , H01L2924/00
摘要： An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit. A receiver front end provides programable attenuation and a programable gain low noise amplifier. LC filters integrated onto the substrate in conjunction with image reject mixers provide image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. Active filters utilize multi track spiral inductors with shields to increase circuit Q. The filters incorporate a gain stage that provides improved dynamic range through the use of cross coupled auxiliary differential pair CMOS amplifiers to cancel distortion in a main linearized differential pair amplifier. Frequency planning provides additional image rejection. Local oscillator signal generation methods on chip reduce distortion. A PLL generates needed out of band LO signals. Direct synthesis generates in band LO signals. PLL VCOs are centered automatically. A differential crystal oscillator provides a frequency reference. Differential signal transmission throughout the receiver is used. ESD protection is provided by a pad ring and ESD clamping structure. Shunts utilize a gate boosting at each pin to discharge ESD build up. An IF VGA utilizes distortion cancellation achieved with cross coupled differential pair amplifiers having their Vds dynamically modified in conjunction with current steering of the differential pairs sources.
摘要翻译：具有通道选择和图像抑制的集成接收器基本上在单个CMOS集成电路上实现。接收机前端提供可编程衰减和可编程增益低噪声放大器。与图像抑制混合器一起集成到衬底上的LC滤波器提供图像频率抑制。过滤器调谐和电感Q补偿温度在芯片上执行。有源滤波器利用具有屏蔽的多轨螺旋电感器来增加电路Q.滤波器包括增益级，其通过使用交叉耦合辅助差分对CMOS放大器来消除主线性化差分对放大器中的失真而提供改进的动态范围。频率规划提供额外的镜像抑制。本地振荡器信号产生方法在芯片上减少失真。 PLL产生所需的带外LO信号。直接合成产生带内LO信号。 PLL VCO自动居中。差分晶体振荡器提供频率参考。使用整个接收机的差分信号传输。 ESD保护由衬垫环和ESD夹紧结构提供。分流器利用每个引脚上的门极升压来放电ESD积聚。 IF VGA利用交叉耦合的差分对放大器实现的失真消除，其具有与差分对源的当前转向结合动态修改的V ds。

10. 发明申请

US20050258901A1 System and method for linearizing a CMOS differential pair 有权
标题翻译：用于线性化CMOS差分对的系统和方法
公开(公告)号：US20050258901A1
公开(公告)日：2005-11-24
申请号：US11131281
申请日：2005-05-18
申请人： Haideh Khorramabadi
发明人： Haideh Khorramabadi
IPC分类号： H01F17/00 , H01L23/522 , H01L27/02 , H01L27/08 , H03B1/00 , H03B5/12 , H03B5/36 , H03D7/16 , H03D7/18 , H03G1/00 , H03H11/12 , H03J1/00 , H03J3/04 , H03J3/08 , H03J3/18 , H03L1/02 , H03L7/10 , H03L7/23 , H03F3/45
CPC分类号： H03L7/23 , H01F17/0006 , H01F17/0013 , H01F2017/0053 , H01F2021/125 , H01L23/5227 , H01L27/0248 , H01L27/08 , H01L2924/0002 , H01L2924/3011 , H03B5/1215 , H03B5/1228 , H03B5/364 , H03B2201/025 , H03B2201/0266 , H03D7/161 , H03D7/18 , H03F1/3211 , H03F1/52 , H03F3/191 , H03F3/45183 , H03F3/45188 , H03F3/45475 , H03F2200/294 , H03F2203/45318 , H03F2203/45704 , H03G1/0029 , H03H11/1291 , H03J1/0075 , H03J3/04 , H03J3/08 , H03J3/185 , H03J2200/10 , H03L1/023 , H03L7/10 , H03L7/18 , H01L2924/00
摘要： An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit. A receiver front end provides programable attenuation and a programable gain low noise amplifier. LC filters integrated onto the substrate in conjunction with image reject mixers provide image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. Active filters utilize multi track spiral inductors with shields to increase circuit Q. The filters incorporate a gain stage that provides improved dynamic range through the use of cross coupled auxiliary differential pair CMOS amplifiers to cancel distortion in a main linearized differential pair amplifier. Frequency planning provides additional image rejection. Local oscillator signal generation methods on chip reduce distortion. A PLL generates needed out of band LO signals. Direct synthesis generates in band LO signals. PLL VCOs are centered automatically. A differential crystal oscillator provides a frequency reference. Differential signal transmission throughout the receiver is used. ESD protection is provided by a pad ring and ESD clamping structure. Shunts utilize a gate boosting at each pin to discharge ESD build up. An IF VGA utilizes distortion cancellation achieved with cross coupled differential pair amplifiers having their Vds dynamically modified in conjunction with current steering of the differential pairs sources.
摘要翻译：具有通道选择和图像抑制的集成接收器基本上在单个CMOS集成电路上实现。接收机前端提供可编程衰减和可编程增益低噪声放大器。与图像抑制混合器一起集成到衬底上的LC滤波器提供图像频率抑制。过滤器调谐和电感Q补偿温度在芯片上执行。有源滤波器利用具有屏蔽的多轨螺旋电感器来增加电路Q.滤波器包括增益级，其通过使用交叉耦合辅助差分对CMOS放大器来消除主线性化差分对放大器中的失真而提供改进的动态范围。频率规划提供额外的镜像抑制。本地振荡器信号产生方法在芯片上减少失真。 PLL产生所需的带外LO信号。直接合成产生带内LO信号。 PLL VCO自动居中。差分晶体振荡器提供频率参考。使用整个接收机的差分信号传输。 ESD保护由衬垫环和ESD夹紧结构提供。分流器利用每个引脚上的门极升压来放电ESD积聚。 IF VGA利用交叉耦合的差分对放大器实现的失真消除，其具有与差分对源的当前转向结合动态修改的V ds。

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