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1. 发明申请

US20180183391A1 Method and Apparatus of an Input Resistance of a Passive Mixer to Broaden the Input Matching Bandwidth of a Common Source/Gate LNA 审中-公开
公开(公告)号：US20180183391A1
公开(公告)日：2018-06-28
申请号：US15884966
申请日：2018-01-31
申请人： Tensorcom, Inc.
发明人： Zaw Soe
IPC分类号： H03F1/42 , H03F3/387 , H03D7/14 , H03D7/16 , H03F1/22 , H03F3/45 , H03D7/12 , H03F3/193
CPC分类号： H03F1/42 , H03D7/125 , H03D7/1441 , H03D7/1466 , H03D7/165 , H03F1/223 , H03F3/193 , H03F3/387 , H03F3/45071 , H03F3/45179 , H03F2200/108 , H03F2200/294 , H03F2200/451 , H03F2200/492 , H03F2200/72 , H03F2200/75 , H04L27/38
摘要： A common-source Low Noise Amplifier (LNA) comprises a first spiral inductor coupled to a source of a first transistor, a second spiral inductor coupled to a drain of a second transistor, and a third inductor connecting the first transistor to the second transistor. The third inductor is configurable to enable a first capacitance to be coupled in parallel to form a bandpass filter. The first spiral inductor is configurable to enable a second capacitance to be coupled in parallel to form a resonant circuit. A variation of the LNA further includes a drain of a third transistor coupled to a gate of a fourth transistor with a first width, a source of the third transistor coupled to the resonant circuit, and an oscillator clock configured to operate at a first frequency that enables the third transistor, wherein the third transistor presents a first impedance to the resonant circuit, causing the resonant circuit to have a first bandwidth.

2. 发明授权

US09484941B2 Method and apparatus for an active negative-capacitor circuit to cancel the input capacitance of comparators 有权
标题翻译：用于消除比较器的输入电容的有源负电容电路的方法和装置
公开(公告)号：US09484941B2
公开(公告)日：2016-11-01
申请号：US14995471
申请日：2016-01-14
申请人： Tensorcom, Inc.
发明人： Dai Dai
IPC分类号： H03M1/06 , H03M1/00 , H03H11/48 , H03K5/24 , H03M1/08 , H03M1/18
CPC分类号： H03K5/2481 , H03H11/481 , H03M1/002 , H03M1/0836 , H03M1/0845 , H03M1/183
摘要： A negative-capacitance circuit comprises a first node coupled to a drain of a first transistor and a gate of a second transistor; a second node coupled to a drain of the second transistor and a gate of the first transistor; a capacitor coupled between a source of the first transistor and a source of the second transistor; a first current mirror coupled between a supply voltage and the source of the first transistor; and a second current mirror coupled between the supply voltage and the source of the second transistor. The circuit can be configured to drive the differential capacitive load between the first and second nodes in a shorter time period, thereby increasing the transfer bandwidth of the differential signal.
摘要翻译：负电容电路包括耦合到第一晶体管的漏极和第二晶体管的栅极的第一节点; 耦合到所述第二晶体管的漏极和所述第一晶体管的栅极的第二节点; 耦合在所述第一晶体管的源极和所述第二晶体管的源极之间的电容器; 耦合在电源电压和第一晶体管的源极之间的第一电流镜; 以及耦合在所述电源电压和所述第二晶体管的源极之间的第二电流镜。电路可以被配置为在较短的时间段内驱动第一和第二节点之间的差分电容性负载，从而增加差分信号的传输带宽。

3. 发明授权

US09418047B2 Method and apparatus of a fully-pipelined FFT 有权
标题翻译：全流水线FFT的方法和装置
公开(公告)号：US09418047B2
公开(公告)日：2016-08-16
申请号：US14192725
申请日：2014-02-27
申请人： Tensorcom, Inc.
发明人： Bo Lu , Ricky Lap Kei Cheung , Bo Xia
IPC分类号： G06F17/14
CPC分类号： G06F17/142
摘要： A plurality of three bit units (called triplets) are permuted by a shuffler to shuffle the positions of the triplets into different patterns which are used to specific the read/write operation of a memory. For example, the least significant triplet in a conventional counter can be placed in the most significant position of a permuted three triplet pattern. The count of this permuted counter triplet generates addresses that jump 64 positions each clock cycle. These permutations can then be used to generate read and write control information to read from/write to memory banks conducive for efficient Radix-8 Butterfly operation. In addition, one or more triplets can also determine if a barrel shifter or right circular shift is required to shift data from one data lane to a second data lane. The triplets allow efficient FFT operation in a pipelined structure.
摘要翻译：多个三位单元（称为三元组）由洗牌器置换，以将三元组的位置洗牌到用于特定存储器的读/写操作的不同模式中。例如，常规计数器中的最低有效三重态可以被置于置换的三重态图案的最重要位置。这个置换的计数器三元组的计数产生每个时钟周期跳转64个位置的地址。然后可以使用这些排列来产生读/写控制信息，从而有助于高效的“八只蝴蝶”操作从存储器库读/写。此外，一个或多个三元组还可以确定是否需要桶形移位器或右循环移位来将数据从一个数据通道移动到第二数据通道。三元组允许在流水线结构中进行有效的FFT运算。

4. 发明申请

US20160156320A1 Method and Apparatus of an Input Resistance of a Passive Mixer to Broaden the Input Matching Bandwidth of a Common Source/Gate LNA 有权
标题翻译：无源混频器的输入电阻的方法和装置，以扩大公共源/门LNA的输入匹配带宽
公开(公告)号：US20160156320A1
公开(公告)日：2016-06-02
申请号：US15016714
申请日：2016-02-05
申请人： Tensorcom, Inc.
发明人： Zaw Soe
IPC分类号： H03F1/42 , H03F3/45 , H03F3/193
CPC分类号： H03F1/42 , H03D7/125 , H03D7/1441 , H03D7/1466 , H03D7/165 , H03F1/223 , H03F3/193 , H03F3/387 , H03F3/45071 , H03F3/45179 , H03F2200/108 , H03F2200/294 , H03F2200/451 , H03F2200/492 , H03F2200/72 , H03F2200/75 , H04L27/38
摘要： A cascode amplifier circuit comprises a first spiral inductor coupled to a source of a first transistor; a second spiral inductor coupled to a drain of a second transistor; a third inductor connecting the first transistor to the second transistor; a first capacitor coupled in parallel to the third inductor forming a bandpass filter; and a second capacitor coupled in parallel to the second spiral inductor forming a resonant circuit, wherein the resonant circuit oscillates at a center frequency.
摘要翻译：一个共源共栅放大器电路包括耦合到第一晶体管源极的第一螺旋电感器; 耦合到第二晶体管的漏极的第二螺旋电感器; 将所述第一晶体管连接到所述第二晶体管的第三电感器; 与形成带通滤波器的第三电感器并联耦合的第一电容器; 以及并联耦合到形成谐振电路的第二螺旋电感器的第二电容器，其中所述谐振电路以中心频率振荡。

5. 发明申请

US20150270993A1 Method and Apparatus of an Architecture to Switch Equalization Based on Signal Delay Spread 有权
标题翻译：基于信号延迟传播的开关均衡的架构方法与装置
公开(公告)号：US20150270993A1
公开(公告)日：2015-09-24
申请号：US14223516
申请日：2014-03-24
申请人： Tensorcom, Inc.
发明人： Ricky Lap Kei Cheung
IPC分类号： H04L25/03 , H04L27/26
CPC分类号： H04L25/03159 , H04L25/0212 , H04L25/03019 , H04L27/2647 , H04L2025/03414
摘要： The 60 GHz channel between the transmitter and receiver can have AWGN characteristics allowing a Time Domain Equalizer (TDE) to be used at the receiver instead of a Frequency Domain Equalizer (FDE). The complexity of performing matrix inversion on a received signal is reduced when directional antennas are used in a 60 GHz system. Incorporating the TDE in place of the FDE saves almost an order of magnitude in power dissipation. For portable units, such a savings is beneficial since the battery life can be extended. The signal quality of wireless channel is based on the characteristics of the received signal to switch the equalization operation from a system performing FDE to TDE and vice versa. The receiver adapts to the received signal to reduce the power dissipation of the system.
摘要翻译：发射机和接收机之间的60 GHz信道可以具有AWGN特性，允许在接收机而不是频域均衡器（FDE）使用时域均衡器（TDE）。当在60GHz系统中使用定向天线时，对接收信号执行矩阵反演的复杂度降低。结合TDE代替FDE节省了功耗的几乎一个数量级。对于便携式设备，这样的节省是有益的，因为电池寿命可以延长。无线信道的信号质量基于接收信号的特性，以将均衡操作从执行FDE的系统切换到TDE，反之亦然。接收机适应接收到的信号，以减少系统的功耗。

6. 发明授权

US09088308B2 Frequency pulling reduction in wide-band direct conversion transmitters 有权
标题翻译：宽带直接转换发射机降频
公开(公告)号：US09088308B2
公开(公告)日：2015-07-21
申请号：US13789682
申请日：2013-03-08
申请人： Tensorcom, Inc.
发明人： Zaw Soe
IPC分类号： H04L27/00 , H04B1/02
CPC分类号： H04B1/02 , H03D7/165
摘要： In an up-converter path of a transmitter, wide-band signal system like direct conversion WiGig, a high pass filter (HPF) is placed in the baseband path after the low pass filter (LPF) but before the mixers. The baseband signal of WiGig can have a bandwidth of 800 MHz. The HPF removes the frequencies from 0-40 MHz from the baseband signal and degrades the overall signal of the baseband by a dB or so. However, the frequency pulling is significantly reduced since oscillator frequency and Radio frequency (RF) transmitter frequencies after conversion become further separated when compared a system using to the conventional approach. This causes the injected signal to fall outside the locking range of the oscillator. The concern of substrate coupling is reduced and allows for a reduction in the physical distance between the oscillator and the mixer and reduces a shift in the desired target frequency of operation.
摘要翻译：在发射机的上转换器路径中，像直接转换WiGig这样的宽带信号系统，高通滤波器（HPF）在低通滤波器（LPF）之后但在混频器之前被置于基带路径中。 WiGig的基带信号可以具有800 MHz的带宽。 HPF从基带信号中删除0-40 MHz的频率，并将基带的整体信号降低dB左右。然而，与使用传统方法的系统进行比较时，振荡器频率和转换后的射频（RF）发射机频率变得更加分离时，频率牵引显着减少。这会使注入的信号落在振荡器的锁定范围之外。衬底耦合的问题被减少并且允许减小振荡器和混频器之间的物理距离，并减少所需目标操作频率的偏移。

7. 发明授权

US09007272B2 Method and apparatus for the alignment of a 60 GHz endfire antenna 有权
标题翻译：用于60 GHz终端天线对准的方法和装置
公开(公告)号：US09007272B2
公开(公告)日：2015-04-14
申请号：US13552955
申请日：2012-07-19
申请人： Joel Abe Balbien , HungYu David Yang , Thaddeus John Gabara
发明人： Joel Abe Balbien , HungYu David Yang , Thaddeus John Gabara
IPC分类号： H01Q21/00 , H01Q9/16 , H01Q1/12 , H01Q1/24 , H01Q1/38 , H01Q1/52 , H01Q3/24 , H01Q21/28 , H01Q25/00
CPC分类号： H01Q21/293 , H01Q1/1257 , H01Q1/243 , H01Q1/38 , H01Q1/525 , H01Q3/04 , H01Q3/242 , H01Q9/16 , H01Q21/28 , H01Q25/00 , H01Q25/005 , H04B7/024
摘要： A portable unit with an endfire antenna and operating at 60 GHz makes an optimum communication channel with an endfire antenna in an array of antennas distributed over the area of a ceiling. The portable unit is pointed towards the ceiling and the system controlling the ceiling units selects and adjusts the positioning of an endfire antenna mounted on a 3-D adjustable rotatable unit. Several transceivers can be mounted together, offset from one another, to provide a wide coverage in both azimuth direction and elevation direction. These units can be rigidly mounted as an array in a ceiling apparatus. The system controlling the ceiling array selects one of the transceivers in one of the units to make the optimum communication channel to the portable unit. The system includes the integration of power management features by switching between Wi-Fi in favor of the 60 GHz channel.
摘要翻译：具有端射天线并以60GHz操作的便携式单元与分布在天花板区域上的天线阵列中的端射天线形成最佳通信信道。便携式设备被指向天花板，并且控制天花板单元的系统选择并调节安装在3-D可调节可旋转单元上的端面天线的定位。几个收发器可以一起安装在一起，彼此偏移，以便在方位方向和仰角方向上提供广泛的覆盖。这些单元可以作为阵列刚性地安装在天花板装置中。控制天花板阵列的系统选择其中一个单元中的一个收发器，以将便携式单元的最佳通信信道。该系统包括通过在支持60 GHz频道的Wi-Fi之间切换来集成电源管理功能。

8. 发明授权

US08724679B2 Method and apparatus of transceiver calibration using substrate coupling 有权
标题翻译：使用基板耦合的收发器校准方法和装置
公开(公告)号：US08724679B2
公开(公告)日：2014-05-13
申请号：US13442387
申请日：2012-04-09
申请人： Ismail Lakkis
发明人： Ismail Lakkis
IPC分类号： H04B1/38
CPC分类号： H04B1/525 , H04B1/123 , H04B1/30
摘要： Transceiver calibration is a critical issue for proper transceiver operation. The transceiver comprises at least one RF transmit chain and one RF receive chain. A closed loop path is formed from the digital block, the RF transmit chain, the substrate coupling, the RF receive chain back to the digital block and is used to estimate and calibrate the transceiver parameters over the operating range of frequencies. The substrate coupling eliminates the need for the additional circuitry saving area, power, and performance. In place of the additional circuitry, the digital block which performs baseband operations can be reconfigured into a software or/and hardware mode to calibrate the transceiver. The digital block comprises a processor and memory and is coupled to the front end of the RF transmit chain and the tail end of the RF receive chain.
摘要翻译：收发器校准是正确的收发器操作的关键问题。收发器包括至少一个RF发射链和一个RF接收链。从数字模块，RF发射链，衬底耦合，RF接收链回到数字模块形成闭环路径，并用于在频率的工作范围内估计和校准收发器参数。基板耦合消除了额外的电路节省面积，功率和性能的需要。代替附加电路，执行基带操作的数字模块可以重新配置成软件或/和硬件模式，以校准收发器。数字模块包括处理器和存储器，并且耦合到RF发射链的前端和RF接收链的尾端。

9. 发明申请

US20140062545A1 Method and Apparatus for Reducing the Clock Kick-Back of ADC Comparators While Maintaining Transistor Matching Behavior 审中-公开
标题翻译：在保持晶体管匹配行为的同时减少ADC比较器的时钟反馈的方法和装置
公开(公告)号：US20140062545A1
公开(公告)日：2014-03-06
申请号：US13602215
申请日：2012-09-03
申请人： Dai Dai
发明人： Dai Dai
IPC分类号： H03L7/00
CPC分类号： H03M1/0818 , H03M1/365
摘要： The core concept of this ADC is the high-speed fully-differential comparators which are clocked at 2.64 GHz and used in a 60 GHz transceiver. The comparator consists of a pre-amplifier stage, a capture stage, a regeneration cell and an output latch. The pre-amplifier stage is not clocked; therefore, the pre-amplifier stage does not suffer initialization and transient behavior effects when the clock signal switches state. The transient response of being enabled and disabled is eliminated. Instead, a capture stage transfers the contents of the pre-amplifier stage into a memory regeneration stage. The capture stage is clocked by pulses that are timed to minimize the clock kick-back generated by the memory regeneration stage. The clock kick-back is reduced even when many comparators are coupled to the PGA. The comparators, instead of having extra dummy fingers, are also aligned right next to each other to minimize the mismatching layout effect.
摘要翻译：该ADC的核心概念是高速全差分比较器，时钟频率为2.64 GHz，用于60 GHz收发器。比较器由前置放大器级，捕获级，再生单元和输出锁存器构成。前置放大器级没有计时; 因此，当时钟信号切换状态时，前置放大器级不会受到初始化和瞬态特性的影响。消除了启用和禁用的瞬态响应。相反，捕获级将前置放大器级的内容传送到存储器再生级。捕获级由定时的脉冲计时，以最小化由存储器再生阶段产生的时钟反冲。即使许多比较器耦合到PGA，时钟反转也减少。比较器而不是具有额外的虚拟手指，也彼此对准，以最小化不匹配的布局效果。

10. 发明授权

US08638252B2 Low power high speed A/D converter 有权
标题翻译：低功率高速A / D转换器
公开(公告)号：US08638252B2
公开(公告)日：2014-01-28
申请号：US13306982
申请日：2011-11-30
申请人： Mahdi Davoodabadi
发明人： Mahdi Davoodabadi
IPC分类号： H03M1/16
CPC分类号： H03M1/002 , H03M1/146 , H03M1/365
摘要： An analog-to-digital converter comprises a first set of comparators configured for generating a coarse digital measurement of an analog input signal, and a second set of comparators for performing a fine digital measurement of the analog input signal. The second set comprises a plurality of dynamic comparators, wherein each dynamic comparator is configurable for being activated by a clock signal. An activation circuit processes the coarse measurement and an input clock signal for generating a set of activation signals, which activate a subset of the dynamic comparators to generate the fine digital measurement.
摘要翻译：模数转换器包括被配置用于产生模拟输入信号的粗略数字测量的第一组比较器和用于执行模拟输入信号的精细数字测量的第二组比较器。第二组包括多个动态比较器，其中每个动态比较器可配置为由时钟信号激活。激活电路处理粗略测量和输入时钟信号以产生一组激活信号，其激活动态比较器的子集以产生精细数字测量。

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