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1. 发明授权

US07773622B2 Deferred queuing in a buffered switch 有权
标题翻译：在缓冲交换机中延迟排队
公开(公告)号：US07773622B2
公开(公告)日：2010-08-10
申请号：US10873430
申请日：2004-06-21
申请人： Steven G. Schmidt , Anthony G. Tornetta , Harry V. Paul , Henry J. Gonzalez
发明人： Steven G. Schmidt , Anthony G. Tornetta , Harry V. Paul , Henry J. Gonzalez
IPC分类号： H04L12/56
CPC分类号： H04L49/3009 , H04L49/30 , H04L2012/5683
摘要： A method and apparatus is disclosed for temporarily deferring transmission of frames to a destination in a data switch. When a request for transmission of a frame to the destination port is received, the congestion status of that destination is determined. If the destination is congested, the frame is stored in a deferred queue. When the status of a destination changes from congested to non-congested, the deferred queue is examined to see if any deferred frames can now be forwarded to their destination. While examining the deferred queue, incoming frames are placed on a backup queue. When the deferred queue is fully analyzed, the backup queue is emptied by either sending those frames to their destination or storing the frames in the deferred queue. While examining the deferred queue, the congested states of the destinations are not allowed to change from congested to non-congested.
摘要翻译：公开了一种用于在数据交换机中暂时推迟到目的地传送帧的方法和装置。当接收到向目的地端口发送帧的请求时，确定该目的地的拥塞状态。如果目的地拥塞，则将帧存储在延迟队列中。当目的地状态从拥塞状态改变为非拥塞状态时，会检查延迟队列，以查看是否有任何延迟帧现在可以转发到其目的地。在检查延迟队列时，传入帧将放置在备份队列中。当延迟队列被完全分析时，通过将这些帧发送到其目的地或将帧存储在延迟队列中，备份队列将被清空。在检查延期队列时，目的地的拥塞状态不允许从拥塞状态改为非拥塞状态。

2. 发明授权

US07260104B2 Deferred queuing in a buffered switch 有权
标题翻译：在缓冲交换机中延迟排队
公开(公告)号：US07260104B2
公开(公告)日：2007-08-21
申请号：US10020968
申请日：2001-12-19
申请人： Steven G. Schmidt
发明人： Steven G. Schmidt
IPC分类号： H04L12/56
CPC分类号： H04L49/3009 , H04L49/30 , H04L2012/5683
摘要： A method and apparatus for temporarily deferring transmission of packets/frames to a destination port in a buffered switch is disclosed. When a request for transmission of at least one packet/frame to the destination port is received, it is determined whether the destination port is available to receive the at least one packet/frame. The transmission of the at least one packet/frame is deferred when the destination port is not available to receive the at least one packet/frame. The packet/frame identifier and memory location for each deferred packet/frame is stored in a deferred queue and the process then repeats for the next packet/frame. Periodically, the apparatus attempts to transmit the packets/frames in the deferred queue to their respective destination ports.
摘要翻译：公开了一种用于暂时将缓存的交换机中的分组/帧传输到目的地端口的方法和装置。当接收到至少一个分组/帧到目的地端口的传输请求时，确定目的端口是否可用于接收至少一个分组/帧。当目的地端口不可用于接收至少一个分组/帧时，延迟至少一个分组/帧的传输。每个延迟分组/帧的分组/帧标识符和存储器位置被存储在延迟队列中，然后该过程重复下一个分组/帧。周期性地，设备尝试将延迟队列中的分组/帧传送到它们各自的目的端口。

3. 发明申请

US20060262791A1 Network switching architecture with multiple table synchronization, and forwarding of both IP and IPX packets 失效
公开(公告)号：US20060262791A1
公开(公告)日：2006-11-23
申请号：US11495739
申请日：2006-07-31
申请人： Shiri Kadambi , Shekhar Ambe
发明人： Shiri Kadambi , Shekhar Ambe
IPC分类号： H04L12/56
CPC分类号： H04L12/5601 , H04L12/18 , H04L12/42 , H04L12/46 , H04L12/4625 , H04L12/4641 , H04L12/4645 , H04L12/467 , H04L12/56 , H04L12/5602 , H04L29/06 , H04L45/00 , H04L45/24 , H04L45/245 , H04L45/742 , H04L47/10 , H04L47/125 , H04L47/2408 , H04L47/2441 , H04L47/2458 , H04L47/30 , H04L47/50 , H04L47/522 , H04L47/525 , H04L47/6205 , H04L47/6215 , H04L47/6225 , H04L47/623 , H04L49/102 , H04L49/103 , H04L49/107 , H04L49/108 , H04L49/109 , H04L49/201 , H04L49/205 , H04L49/254 , H04L49/3009 , H04L49/3036 , H04L49/3072 , H04L49/3081 , H04L49/309 , H04L49/351 , H04L49/352 , H04L49/354 , H04L49/602 , H04L49/606 , H04L49/90 , H04L49/901 , H04L49/9047 , H04L49/9057 , H04L49/9073 , H04L67/10 , H04L69/14 , H04L69/16 , H04L69/161 , H04L69/323 , H04L69/329 , H04L2012/5651 , H04L2012/5665 , H04L2012/5667 , H04L2012/5679 , H04L2012/568 , H04L2012/5682 , H04L2012/5683 , Y02D50/30 , Y10S707/99931 , Y10S707/99945
摘要： A network switch for network communications includes a first data port interface. The first data port interface supports a plurality of data ports transmitting and receiving data at a first data rate. A second data port interface is provided; the second data port interface supports a plurality of data ports transmitting and receiving data at a second data rate. A CPU interface is provided, with the CPU interface configured to communicate with a CPU. An internal memory is provided, and communicates with the first data port interface and the at least one second data port interface. A memory management unit is provided, and includes an external memory interface for communicating data from at least one of the first data port interface and the second data port interface and an external memory. A communication channel is provided, with the communication channel communicating data and messaging information between the first data port interface, the second data port interface, the internal memory, and the memory management unit. A plurality of semiconductor-implemented lookup tables are provided, with the lookup tables including an address resolution lookup/layer three lookup, rules tables, and VLAN tables. One of the data port interfaces is configured to update the address resolution table based on newly learned layer to addresses. An update to an address table associated with an initial data port interface of the first and second data port interfaces results in the initial data port interface sending a synchronization signal to the other address resolution tables in the network switch. As a result, all address resolution tables on the network switch are synchronized on a per entry basis.

4. 发明授权

US07106734B2 Network switching architecture with multiple table synchronization, and forwarding of both IP and IPX packets 失效
标题翻译：具有多表同步的网络交换架构，以及IP和IPX数据包的转发
公开(公告)号：US07106734B2
公开(公告)日：2006-09-12
申请号：US10418280
申请日：2003-04-18
申请人： Shiri Kadambi , Shekhar Ambe
发明人： Shiri Kadambi , Shekhar Ambe
IPC分类号： H04L12/28 , H04J3/16
CPC分类号： H04L12/5601 , H04L12/18 , H04L12/42 , H04L12/46 , H04L12/4625 , H04L12/4641 , H04L12/4645 , H04L12/467 , H04L12/56 , H04L12/5602 , H04L29/06 , H04L45/00 , H04L45/24 , H04L45/245 , H04L45/742 , H04L47/10 , H04L47/125 , H04L47/2408 , H04L47/2441 , H04L47/2458 , H04L47/30 , H04L47/50 , H04L47/522 , H04L47/525 , H04L47/6205 , H04L47/6215 , H04L47/6225 , H04L47/623 , H04L49/102 , H04L49/103 , H04L49/107 , H04L49/108 , H04L49/109 , H04L49/201 , H04L49/205 , H04L49/254 , H04L49/3009 , H04L49/3036 , H04L49/3072 , H04L49/3081 , H04L49/309 , H04L49/351 , H04L49/352 , H04L49/354 , H04L49/602 , H04L49/606 , H04L49/90 , H04L49/901 , H04L49/9047 , H04L49/9057 , H04L49/9073 , H04L67/10 , H04L69/14 , H04L69/16 , H04L69/161 , H04L69/323 , H04L69/329 , H04L2012/5651 , H04L2012/5665 , H04L2012/5667 , H04L2012/5679 , H04L2012/568 , H04L2012/5682 , H04L2012/5683 , Y02D50/30 , Y10S707/99931 , Y10S707/99945
摘要： A network switch for network communications includes a first data port interface, supporting a plurality of data ports transmitting and receiving data at a first data rate. A second data port interface supporting a plurality of data ports transmitting and receiving data at a second data rate. A CPU interface communicating with a CPU, an internal memory, a memory management having an external memory interface, and a communication channel are provided. A plurality of lookup tables having address resolution lookup/layer three lookup, rules tables, and VLAN tables are provided. One of the data port interfaces is configured to update the address resolution table based on newly learned layer to addresses and a synchronization process per entry is provided.
摘要翻译：用于网络通信的网络交换机包括第一数据端口接口，支持以第一数据速率发送和接收数据的多个数据端口。第二数据端口接口，支持以第二数据速率发送和接收数据的多个数据端口。提供了与CPU通信的CPU接口，内部存储器，具有外部存储器接口的存储器管理和通信信道。提供了具有地址解析查找/第三层查找，规则表和VLAN表的多个查找表。其中一个数据端口接口被配置为基于新学习的层到地址来更新地址解析表，并提供每个条目的同步过程。

5. 发明授权

US07002978B2 Scheduling techniques for data cells in a data switch 失效
标题翻译：数据交换机中数据单元的调度技术
公开(公告)号：US07002978B2
公开(公告)日：2006-02-21
申请号：US09780054
申请日：2001-02-09
申请人： Bidyut Parruck , Chetan V. Sanghvi , Vinay Kumar Bhasin , Makarand Dharmapurikar , Uday Govind Joshi
发明人： Bidyut Parruck , Chetan V. Sanghvi , Vinay Kumar Bhasin , Makarand Dharmapurikar , Uday Govind Joshi
IPC分类号： H04L12/56
CPC分类号： H04L12/5601 , H04L49/106 , H04L49/1553 , H04L49/1576 , H04L2012/5635 , H04L2012/5651 , H04L2012/5679 , H04L2012/5681 , H04L2012/5682 , H04L2012/5683
摘要： A computer-implemented method for scheduling cells output on an output path of a data switch. The data switch is configured for switching the cells from a plurality of input paths to the output path. The method includes providing a plurality of queues, each queue of the plurality of queues having an assigned weight, respective ones of the plurality of input paths being coupled to respective ones of the plurality of queues. The method further includes providing a plurality of queues of queues. The plurality of queues being coupled to the plurality of queues of queues with queues of the plurality of queues having a similar weight being coupled a same queue of queues of the plurality of queues of queues. There is further included providing a scheduler, the plurality of queues of queues being input into the scheduler, the scheduler being coupled to the output path.
摘要翻译：一种用于在数据交换机的输出路径上调度小区输出的计算机实现的方法。数据开关被配置用于将单元从多个输入路径切换到输出路径。所述方法包括提供多个队列，所述多个队列中的每个队列具有分配权重，所述多个输入路径中的相应输入路径被耦合到所述多个队列中的相应队列。该方法还包括提供多个队列队列。多个队列被耦合到队列的多个队列，其中具有相似权重的多个队列的队列被耦合在队列的多个队列的相同队列中。还包括提供调度器，多个队列队列被输入到调度器中，调度器被耦合到输出路径。

6. 发明申请

US20030189924A1 Network switching architecture with multiple table synchronization, and forwarding of both IP and IPX packets 失效
公开(公告)号：US20030189924A1
公开(公告)日：2003-10-09
申请号：US10418280
申请日：2003-04-18
申请人： Broadcom Corporation
发明人： Shiri Kadambi , Shekhar Ambe
IPC分类号： H04L012/66
CPC分类号： H04L12/5601 , H04L12/18 , H04L12/42 , H04L12/46 , H04L12/4625 , H04L12/4641 , H04L12/4645 , H04L12/467 , H04L12/56 , H04L12/5602 , H04L29/06 , H04L45/00 , H04L45/24 , H04L45/245 , H04L45/742 , H04L47/10 , H04L47/125 , H04L47/2408 , H04L47/2441 , H04L47/2458 , H04L47/30 , H04L47/50 , H04L47/522 , H04L47/525 , H04L47/6205 , H04L47/6215 , H04L47/6225 , H04L47/623 , H04L49/102 , H04L49/103 , H04L49/107 , H04L49/108 , H04L49/109 , H04L49/201 , H04L49/205 , H04L49/254 , H04L49/3009 , H04L49/3036 , H04L49/3072 , H04L49/3081 , H04L49/309 , H04L49/351 , H04L49/352 , H04L49/354 , H04L49/602 , H04L49/606 , H04L49/90 , H04L49/901 , H04L49/9047 , H04L49/9057 , H04L49/9073 , H04L67/10 , H04L69/14 , H04L69/16 , H04L69/161 , H04L69/323 , H04L69/329 , H04L2012/5651 , H04L2012/5665 , H04L2012/5667 , H04L2012/5679 , H04L2012/568 , H04L2012/5682 , H04L2012/5683 , Y02D50/30 , Y10S707/99931 , Y10S707/99945
摘要： A network switch for network communications includes a first data port interface. The first data port interface supports a plurality of data ports transmitting and receiving data at a first data rate. A second data port interface is provided; the second data port interface supports a plurality of data ports transmitting and receiving data at a second data rate. A CPU interface is provided, with the CPU interface configured to communicate with a CPU. An internal memory is provided, and communicates with the first data port interface and the at least one second data port interface. A memory management unit is provided, and includes an external memory interface for communicating data from at least one of the first data port interface and the second data port interface and an external memory. A communication channel is provided, with the communication channel communicating data and messaging information between the first data port interface, the second data port interface, the internal memory, and the memory management unit. A plurality of semiconductor-implemented lookup tables are provided, with the lookup tables including an address resolution lookup/layer three lookup, rules tables, and VLAN tables. One of the data port interfaces is configured to update the address resolution table based on newly learned layer to addresses. An update to an address table associated with an initial data port interface of the first and second data port interfaces results in the initial data port interface sending a synchronization signal to the other address resolution tables in the network switch. As a result, all address resolution tables on the network switch are synchronized on a per entry basis.

7. 发明授权

US06426957B1 Asynchronous transfer mode based service consolidation switch 失效
标题翻译：基于异步传输模式的服务整合开关
公开(公告)号：US06426957B1
公开(公告)日：2002-07-30
申请号：US09209526
申请日：1998-12-11
申请人： Stephen A. Hauser , Stephen A. Caldara , Thomas A. Manning
发明人： Stephen A. Hauser , Stephen A. Caldara , Thomas A. Manning
IPC分类号： H04L1228
CPC分类号： H04L47/18 , G06F15/17375 , H04J3/0682 , H04J3/0685 , H04L7/046 , H04L12/4608 , H04L12/5601 , H04L12/5602 , H04L12/64 , H04L12/6402 , H04L41/00 , H04L41/0896 , H04L47/10 , H04L47/11 , H04L47/15 , H04L47/16 , H04L47/26 , H04L47/266 , H04L47/29 , H04L47/30 , H04L47/50 , H04L47/52 , H04L47/521 , H04L47/522 , H04L47/525 , H04L47/56 , H04L47/621 , H04L47/6215 , H04L47/6225 , H04L47/627 , H04L47/70 , H04L47/722 , H04L47/743 , H04L47/745 , H04L47/762 , H04L47/782 , H04L47/805 , H04L47/822 , H04L49/101 , H04L49/103 , H04L49/106 , H04L49/107 , H04L49/108 , H04L49/153 , H04L49/1553 , H04L49/1576 , H04L49/20 , H04L49/201 , H04L49/203 , H04L49/205 , H04L49/25 , H04L49/253 , H04L49/254 , H04L49/255 , H04L49/256 , H04L49/30 , H04L49/3009 , H04L49/3081 , H04L49/309 , H04L49/455 , H04L49/503 , H04L49/505 , H04L49/506 , H04L49/508 , H04L49/55 , H04L49/552 , H04L49/555 , H04L49/90 , H04L49/901 , H04L49/9047 , H04L49/9078 , H04L69/32 , H04L69/324 , H04L2012/5614 , H04L2012/5616 , H04L2012/5627 , H04L2012/5628 , H04L2012/5629 , H04L2012/5631 , H04L2012/5632 , H04L2012/5634 , H04L2012/5635 , H04L2012/5642 , H04L2012/5643 , H04L2012/5647 , H04L2012/5648 , H04L2012/5649 , H04L2012/565 , H04L2012/5651 , H04L2012/5652 , H04L2012/5672 , H04L2012/5679 , H04L2012/5681 , H04L2012/5682 , H04L2012/5683 , H04L2012/5684 , H04L2012/5685 , H04Q11/0478 , H04W28/14 , Y10S370/902 , Y10S370/905
摘要： An asynchronous transfer mode (ATM) based service consolidation switch (10) includes an input/output module (22) having a to-switch port (TSPP) processor (90) and a from-switch port processor (FSPP) (92). The TSPP (90) and the FSPP (92) communicate with a bandwidth arbiter (114), multipoint topology controllers (116), and a data crossbar (117) on a switch control module (32). The TSPP (90) receives traffic over links for conversion into an internal cell format. Internal cells are buffered until allowed to transfer to an appropriate FSPP (92). Multipoint topology controllers (116) performs translations for internal switch flow control through interactions between the TSPPs (90), FSPPs (92), and the bandwidth arbiter (114). The bandwidth arbiter (114) performs appropriate bandwidth arbitration to allow internal cells to flow from TSPPs (90) to FSPPs (92) over the data crossbar (117).
摘要翻译：基于异步传输模式（ATM）的服务合并开关（10）包括具有交换机端口（TSPP）处理器（90）和从交换机端口处理器（FSPP）（92））的输入/输出模块（22）。 TSPP（90）和FSPP（92）与开关控制模块（32）上的带宽仲裁器（114），多点拓扑控制器（116）和数据交叉开关（117）通信。 TSPP（90）通过链路接收流量以转换为内部小区格式。内部细胞被缓冲直到允许转移到适当的FSPP（92）。多点拓扑控制器（116）通过TSPP（90），FSPP（92）和带宽仲裁器（114）之间的交互来执行用于内部交换机流控制的转换。带宽仲裁器（114）执行适当的带宽仲裁以允许内部小区从数据交叉开关（117）从TSPP（90）流向FSPP（92）。

8. 发明申请

US20020093974A1 High performance self balancing low cost network switching architecture based on distributed hierarchical shared memory 有权
公开(公告)号：US20020093974A1
公开(公告)日：2002-07-18
申请号：US10100078
申请日：2002-03-19
申请人： Broadcom Corporation
发明人： Shiri Kadambi , Shekhar Ambe
IPC分类号： H04L012/56 , H04L012/28
CPC分类号： H04L12/5601 , H04L12/18 , H04L12/42 , H04L12/46 , H04L12/4625 , H04L12/4641 , H04L12/4645 , H04L12/467 , H04L12/56 , H04L12/5602 , H04L29/06 , H04L45/00 , H04L45/24 , H04L45/245 , H04L45/742 , H04L47/10 , H04L47/125 , H04L47/2408 , H04L47/2441 , H04L47/2458 , H04L47/30 , H04L47/50 , H04L47/522 , H04L47/525 , H04L47/6205 , H04L47/6215 , H04L47/6225 , H04L47/623 , H04L49/102 , H04L49/103 , H04L49/107 , H04L49/108 , H04L49/109 , H04L49/201 , H04L49/205 , H04L49/254 , H04L49/3009 , H04L49/3036 , H04L49/3072 , H04L49/3081 , H04L49/309 , H04L49/351 , H04L49/352 , H04L49/354 , H04L49/602 , H04L49/606 , H04L49/90 , H04L49/901 , H04L49/9047 , H04L49/9057 , H04L49/9073 , H04L67/10 , H04L69/14 , H04L69/16 , H04L69/161 , H04L69/323 , H04L69/329 , H04L2012/5651 , H04L2012/5665 , H04L2012/5667 , H04L2012/5679 , H04L2012/568 , H04L2012/5682 , H04L2012/5683 , Y02D50/30 , Y10S707/99931 , Y10S707/99945
摘要： A data switch for network communications includes at least one first data port interface which supports a plurality of data ports which transmit and receive data at a first data rate. At least one second data port interface is provided; the at least one second data port interface supports a plurality of data ports transmitting and receiving data at a second data rate. A CPU interface is provided, with the CPU interface configured to communicate with a CPU. An internal memory is provided, and communicates with the at least one first data port interface and the at least one second data port interface. A memory management unit is provided, and includes an external memory interface for communicating data from at least one of the first data port interface and the second data port interface and an external memory. A communication channel is provided, with the communication channel communicating data and messaging information between the at least one first data port interface, the at least one second data port interface, the internal memory, and the memory management unit. The memory management unit directs data from one of the first data port and the second data port to one of the internal memory and the external memory interface, according to a predetermined algorithm.

9. 发明申请

US20020027908A1 Switch fabric with path redundancy 有权
标题翻译：交换结构具有路径冗余
公开(公告)号：US20020027908A1
公开(公告)日：2002-03-07
申请号：US09883212
申请日：2001-06-19
申请人： BROADCOM CORPORATION
发明人： Mohan Kalkunte , Srinivas Sampath , Daniel Tai , Soma Pullela , Kevin Cameron
IPC分类号： H04L012/28
CPC分类号： H04L12/5601 , H04L12/18 , H04L12/1881 , H04L45/00 , H04L45/245 , H04L45/54 , H04L45/745 , H04L47/10 , H04L47/2408 , H04L47/2425 , H04L47/2441 , H04L47/245 , H04L47/286 , H04L47/30 , H04L47/32 , H04L47/6205 , H04L47/6215 , H04L47/6225 , H04L49/101 , H04L49/201 , H04L49/203 , H04L49/205 , H04L49/25 , H04L49/254 , H04L49/30 , H04L49/309 , H04L49/352 , H04L49/608 , H04L49/90 , H04L49/901 , H04L49/9094 , H04L2012/5651 , H04L2012/5665 , H04L2012/5679 , H04L2012/5681 , H04L2012/5683 , Y02D50/30
摘要： A method of forwarding data in a network switch fabric is disclosed. An incoming data packet is received at a first port of the fabric and a first packet portion, less than a full packet length, is read to determine particular packet information, the particular packet information including a source address and a destination address. An egress port bitmap is determined based on a lookup in a forwarding table and it is determined if the destination address belongs to a trunk group of trunked ports. The incoming data packet is forwarded based on the egress port bitmap, when the destination address does not belong to the trunk group. When the destination address does belong to the trunk group, a particular trunked port of the trunk group is determined and the incoming data packet is forwarded thereto. More specifically, the particular trunked port of the trunk group may be determined by calculating a hash value based on the source address and the destination value and selecting the particular trunked port based on the hash value. Additionally, a class of service for the incoming data packet is also determined from the particular packet information and a priority for forwarding is set based on the class of service.
摘要翻译：公开了一种在网络交换结构中转发数据的方法。在结构的第一端口处接收输入数据分组，并且读取小于全分组长度的第一分组部分以确定特定分组信息，所述特定分组信息包括源地址和目的地地址。基于转发表中的查找来确定出口端口位图，并且确定目的地址是否属于中继端口的中继线群组。输入的数据包根据出口端口位图转发，当目的地址不属于中继线群组时。当目的地址属于中继组时，确定中继组的特定中继端口，并将传入的数据包转发到其中。更具体地，可以通过基于源地址和目的地值计算哈希值并基于哈希值来选择特定中继端口来确定中继线群组的特定中继端口。此外，还根据特定分组信息确定用于输入数据分组的一类服务，并且基于服务等级设置用于转发的优先级。

10. 发明授权

US6335935B2 Network switching architecture with fast filtering processor 失效
公开(公告)号：US6335935B2
公开(公告)日：2002-01-01
申请号：US34341199
申请日：1999-06-30
申请人： BROADCOM CORP
发明人： KADAMBI SHIRI , AMBE SHEKHAR
IPC分类号： G06F17/30 , H04L12/18 , H04L12/28 , H04L12/42 , H04L12/46 , H04L12/50 , H04L12/56 , H04L29/06 , H04L29/08
CPC分类号： H04L12/5601 , H04L12/18 , H04L12/42 , H04L12/46 , H04L12/4625 , H04L12/4641 , H04L12/4645 , H04L12/467 , H04L12/56 , H04L12/5602 , H04L29/06 , H04L45/00 , H04L45/24 , H04L45/245 , H04L45/742 , H04L47/10 , H04L47/125 , H04L47/2408 , H04L47/2441 , H04L47/2458 , H04L47/30 , H04L47/50 , H04L47/522 , H04L47/525 , H04L47/6205 , H04L47/6215 , H04L47/6225 , H04L47/623 , H04L49/102 , H04L49/103 , H04L49/107 , H04L49/108 , H04L49/109 , H04L49/201 , H04L49/205 , H04L49/254 , H04L49/3009 , H04L49/3036 , H04L49/3072 , H04L49/3081 , H04L49/309 , H04L49/351 , H04L49/352 , H04L49/354 , H04L49/602 , H04L49/606 , H04L49/90 , H04L49/901 , H04L49/9047 , H04L49/9057 , H04L49/9073 , H04L67/10 , H04L69/14 , H04L69/16 , H04L69/161 , H04L69/323 , H04L69/329 , H04L2012/5651 , H04L2012/5665 , H04L2012/5667 , H04L2012/5679 , H04L2012/568 , H04L2012/5682 , H04L2012/5683 , Y02D50/30 , Y10S707/99931 , Y10S707/99945
摘要： A network switch for network communications includes a first data port interface supporting a plurality of data ports transmitting and receiving data at a first data rate. A second data port interface supports a plurality of data ports transmitting and receiving data at a second data rate. A CPU interface is configured to communicate with a CPU, and an internal memory communicates with the first data port interface and the second data port interface. A memory management unit is provided, including an external memory interface, for communicating data from at least one of the first data port interface and the second data port interface and an external memory. A communication channel is provided, for communicating data and messaging information between the first data port interface, the second data port interface, the internal memory, and the memory management unit. One data port interface of the first data port interface and the second data port interface includes a fast filtering process, with the fast filtering processor filtering packets coming into the one data port interface. Selective filter action is taken based upon a filtering result.

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