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31. 发明授权

US5424881A Synchronous read channel 失效
公开(公告)号：US5424881A
公开(公告)日：1995-06-13
申请号：US12266
申请日：1993-02-01
申请人： Richard T. Behrens , Kent D. Anderson , Alan Armstrong , Trent Dudley , Bill Foland , Neal Glover , Larry King
发明人： Richard T. Behrens , Kent D. Anderson , Alan Armstrong , Trent Dudley , Bill Foland , Neal Glover , Larry King
IPC分类号： G11B5/012 , G11B5/09 , G11B20/10 , G11B20/12 , G11B20/14 , G11B20/18 , G11B27/30 , H03M13/31 , G06F11/10 , G11B20/16
CPC分类号： G11B20/10055 , G11B20/10 , G11B20/10009 , G11B20/1403 , G11B20/1426 , G11B20/18 , G11B27/3027 , G11B5/012 , G11B5/09 , H03M13/31 , G11B20/1258 , G11B2020/1476
摘要： A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(1,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, together with the error-tolerant sync mark detection and the ability to recover data when the sync mark is obliterated, allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery. Various embodiments, including an embodiment incorporating the analog functions as well as the primary digital functions of the read channel in a single integrated circuit, and preferred embodiments utilizing a reduced complexity, programmable modified Viterbi detector supporting a broad class of partial response channels are disclosed.

32. 发明申请

US20110230158A1 Partitioned radio-frequency apparatus and associated methods 有权
公开(公告)号：US20110230158A1
公开(公告)日：2011-09-22
申请号：US13104822
申请日：2011-05-10
申请人： Donald A. Kerth , Richard T. Behrens , Jeffrey W. Scott , G. Diwakar Vishakhadatta , G. Tyson Tuttle , Vishnu Shankar Srinivasan
发明人： Donald A. Kerth , Richard T. Behrens , Jeffrey W. Scott , G. Diwakar Vishakhadatta , G. Tyson Tuttle , Vishnu Shankar Srinivasan
IPC分类号： H04B1/16
CPC分类号： H04B1/109 , H04B1/0003 , H04B1/28 , H04B1/406 , H04B15/02 , H04B15/04 , H04B2215/064 , H04L27/2649
摘要： Radio-frequency (RF) apparatus includes receiver analog circuitry that receives an RF signal and provides at least one digital signal to receiver digital circuitry that functions in cooperation with the receiver analog circuitry. The receiver analog circuitry and the receiver digital circuitry are partitioned so that interference effects between the receiver analog circuitry and the receiver digital circuitry tend to be reduced.

33. 发明授权

US07228109B2 DC offset reduction in radio-frequency apparatus and associated methods 有权
标题翻译：射频设备的DC偏移减少和相关方法
公开(公告)号：US07228109B2
公开(公告)日：2007-06-05
申请号：US10074676
申请日：2002-02-12
申请人： Tod Paulus , Donald A. Kerth , Richard T. Behrens , Jeffrey W. Scott , G. Diwakar Vishakhadatta , G. Tyson Tuttle , Vishnu S. Srinivasan
发明人： Tod Paulus , Donald A. Kerth , Richard T. Behrens , Jeffrey W. Scott , G. Diwakar Vishakhadatta , G. Tyson Tuttle , Vishnu S. Srinivasan
IPC分类号： H04B1/40
CPC分类号： H04L25/061 , H04B1/0003 , H04B1/28 , H04B1/406 , H04B15/02 , H04B15/04 , H04B2215/064
摘要： A radio-frequency receiver circuitry includes a down-converter circuitry, an analog-to-digital converter circuitry, and a DC offset reduction circuitry. The down-converter circuitry accepts a received radio-frequency signal and processes the radio-frequency signal to provide an in-phase down-converted signal and a quadrature down-converted signal to the analog-to-digital converter circuitry. The analog-to-digital converter circuitry converts the in-phase and quadrature down-converted signals to an in-phase digital output signal and a quadrature digital output signal, respectively. The DC offset reduction circuitry couples to the analog-to-digital converter circuitry, and tends to reduce a DC offset transmitted to the in-phase and quadrature digital output signals.
摘要翻译：射频接收器电路包括下变频器电路，模数转换器电路和DC偏移减小电路。下变换器电路接收接收的射频信号并处理射频信号以向模数转换器电路提供同相下变频信号和正交下变频信号。模数转换器电路将同相和正交下变频信号分别转换为同相数字输出信号和正交数字输出信号。 DC偏移降低电路耦合到模数转换器电路，并且倾向于减少传输到同相和正交数字输出信号的DC偏移。

34. 发明授权

US07024221B2 Notch filter for DC offset reduction in radio-frequency apparatus and associated methods 有权
公开(公告)号：US07024221B2
公开(公告)日：2006-04-04
申请号：US10075099
申请日：2002-02-12
申请人： Tod Paulus , Richard T. Behrens , Vishnu S. Srinivasan , Mark S. Spurbeck , Donald A. Kerth , Jeffrey W. Scott , G. Tyson Tuttle , G. Diwakar Vishakhadatta
发明人： Tod Paulus , Richard T. Behrens , Vishnu S. Srinivasan , Mark S. Spurbeck , Donald A. Kerth , Jeffrey W. Scott , G. Tyson Tuttle , G. Diwakar Vishakhadatta
IPC分类号： H04B1/38 , H04M1/00
CPC分类号： H04B1/0003 , H04B1/28 , H04B1/406 , H04B15/02 , H04B15/04 , H04B2215/064
摘要： A radio-frequency (RF) receiver includes a receiver analog circuitry and a receiver digital circuitry coupled together. The receiver analog circuitry receives an RF signal. The receiver analog circuitry processes the received RF signal and generates a digital signal that it provides to the receiver digital circuitry. The receiver digital circuitry includes a digital down-converter circuitry that mixes the digital signal provided by a receiver analog circuitry with a digital intermediate frequency (IF) local oscillator signal to generate a digital down-converted signal. The receiver digital circuitry also includes a digital filter circuitry that filters the digital down-converted signal to generate a filtered digital signal. The digital filter circuitry provides a notch at a frequency that corresponds to a residual DC offset of the receiver analog circuitry.

35. 发明授权

US06993314B2 Apparatus for generating multiple radio frequencies in communication circuitry and associated methods 有权
公开(公告)号：US06993314B2
公开(公告)日：2006-01-31
申请号：US10074591
申请日：2002-02-13
申请人： Lysander Lim , Caiyi Wang , David R. Welland , Donald A. Kerth , Richard T. Behrens , Jeffrey W. Scott , G. Diwakar Vishakhadatta , G. Tyson Tuttle , Vishnu S. Srinivasan
发明人： Lysander Lim , Caiyi Wang , David R. Welland , Donald A. Kerth , Richard T. Behrens , Jeffrey W. Scott , G. Diwakar Vishakhadatta , G. Tyson Tuttle , Vishnu S. Srinivasan
IPC分类号： H04N1/28
CPC分类号： H04B1/0003 , H03L7/085 , H03L7/087 , H03L7/091 , H03L7/099 , H03L7/187 , H03L7/199 , H03L7/23 , H04B1/28 , H04B1/406 , H04B15/02 , H04B15/04 , H04B2215/064
摘要： A radio-frequency (RF) apparatus capable of transmitting RF signals includes transmitter path circuitry. The transmitter path circuitry includes a voltage-controlled oscillator (VCO) circuitry. The VCO circuitry generates a first signal that has a first frequency. A divider circuitry couples to the VCO circuitry and, in response to the first signal, the divider circuitry generates a second signal that has a second frequency. The frequency of the second signal equals the frequency of the first signal divided by a number.

36. 发明授权

US6108151A Sampled amplitude read channel for reading user data and embedded servo data from a magnetic medium 失效
标题翻译：采样幅度读通道，用于从磁介质读取用户数据和嵌入式伺服数据
公开(公告)号：US6108151A
公开(公告)日：2000-08-22
申请号：US846140
申请日：1997-04-25
申请人： Tyson Tuttle , Diwakar Vishakhadatta , Jerrel P. Hein , David R. Welland , David E. Reed , Richard T. Behrens , William G. Bliss , Paul M. Romano , Trent O. Dudley , Christopher P. Zook
发明人： Tyson Tuttle , Diwakar Vishakhadatta , Jerrel P. Hein , David R. Welland , David E. Reed , Richard T. Behrens , William G. Bliss , Paul M. Romano , Trent O. Dudley , Christopher P. Zook
IPC分类号： G11B5/012 , G11B5/09 , G11B5/55 , G11B5/58 , G11B5/596 , G11B19/28 , G11B20/10 , G11B20/12 , G11B20/14 , G11B15/12 , G11B21/02
CPC分类号： G11B20/10055 , G11B19/28 , G11B20/10009 , G11B20/10037 , G11B20/1403 , G11B5/012 , G11B5/09 , G11B5/5526 , G11B5/553 , G11B5/5547 , G11B5/58 , G11B5/59605 , G11B5/59622 , G11B5/59633 , G11B5/59688 , G11B20/1258 , G11B5/5534 , G11B5/5965
摘要： A sampled amplitude read channel is disclosed for reading data recorded on a disk storage medium by detecting an estimated binary sequence from a sequence of discrete time sample values generated by sampling pulses in an analog read signal from a read head positioned over the disk storage medium. The read channel comprises a sampling device, such as an analog-to-digital converter (A/D), for sampling the analog read signal to generate the discrete time sample values and for sampling at least one other auxillary analog input signal, such as a servo control signal. In this manner, performance characteristics of the read channel can be measured, such as the driving current applied to the servo control voice coil motor (VCM), without requiring additional hardware.
摘要翻译：公开了一种采样幅度读取通道，用于通过从位于盘存储介质上的读取头的模拟读取信号中通过采样脉冲产生的离散时间采样值序列检测估计的二进制序列来读取记录在盘存储介质上的数据。读取通道包括采样装置，例如模拟 - 数字转换器（A / D），用于对模拟读取信号进行采样以产生离散时间采样值，并用于对至少一个其他辅助模拟输入信号进行采样，例如伺服控制信号。以这种方式，可以测量读取通道的性能特性，例如施加到伺服控制音圈电机（VCM）的驱动电流，而不需要额外的硬件。

37. 发明授权

US5991107A Sychronous read channel 失效
标题翻译：同步读通道
公开(公告)号：US5991107A
公开(公告)日：1999-11-23
申请号：US822173
申请日：1997-03-21
申请人： Richard T. Behrens , Trent O. Dudley , Neal Glover , David R. Welland
发明人： Richard T. Behrens , Trent O. Dudley , Neal Glover , David R. Welland
IPC分类号： G11B5/012 , G11B5/09 , G11B20/10 , G11B20/12 , G11B20/14 , G11B20/18 , G11B27/30 , H03M13/31 , G11B5/035
CPC分类号： G11B20/10055 , G11B20/10 , G11B20/10009 , G11B20/1403 , G11B20/1426 , G11B20/18 , G11B27/3027 , G11B5/012 , G11B5/09 , H03M13/31 , G11B20/1258 , G11B2020/1476
摘要： A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, computes a DC offset in the sample values in real time, and subtracts the DC offset from the read signal. This attenuates the deleterious affect a DC offset has on the detection algorithm used to detect the recorded data, such as the Viterbi detection algorithm.
摘要翻译：公开了一种同步读取通道，其从位于磁盘介质上的磁读头读取模拟读取信号，实时计算样本值中的DC偏移量，并从读取信号中减去DC偏移。这减弱了DC偏移对用于检测记录数据的检测算法（如维特比检测算法）的有害影响。

38. 发明授权

US5917668A Synchronous read channel employing a frequency synthesizer for locking a timing recovery phase-lock loop to a reference frequency 失效
标题翻译：采用频率合成器的同步读通道，用于将定时恢复锁相环锁定到参考频率
公开(公告)号：US5917668A
公开(公告)日：1999-06-29
申请号：US822174
申请日：1997-03-21
申请人： Richard T. Behrens , Trent Dudley , Neal Glover , David R. Welland
发明人： Richard T. Behrens , Trent Dudley , Neal Glover , David R. Welland
IPC分类号： G11B5/012 , G11B5/09 , G11B20/10 , G11B20/12 , G11B20/14 , G11B20/18 , G11B27/30 , H03M13/31
CPC分类号： G11B20/10055 , G11B20/10 , G11B20/10009 , G11B20/1403 , G11B20/1426 , G11B20/18 , G11B27/3027 , G11B5/012 , G11B5/09 , H03M13/31 , G11B20/1258 , G11B2020/1476
摘要： A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a discrete time sequence detector. To ensure a small frequency error when timing recovery acquisition mode is entered, the timing recovery phase-lock loop (PLL) is first locked to a nominal read frequency which is the same as the write frequency. This is accomplished by multiplexing the output of the write frequency synthesizer into the timing recovery PLL in a lock-to-reference mode. Thereafter, the analog signal from the read head is multiplexed into the timing recovery PLL in order to acquire the actual frequency and phase of an acquisition preamble recorded prior to the user data.
摘要翻译：公开了一种同步读通道，其从位于磁盘介质上的磁读头读取模拟读信号，根据所需的部分响应对采样值进行滤波，从滤波后的采样值中提取定时信息，并检测估计数据序列使用离散时间序列检测器从滤波后的样本值。为了在进入定时恢复采集模式时确保小的频率误差，定时恢复锁相环（PLL）首先被锁定到与写入频率相同的标称读取频率。这是通过将写入频率合成器的输出以锁定参考模式复用到定时恢复PLL来实现的。此后，来自读取头的模拟信号被多路复用到定时恢复PLL中，以便获取在用户数据之前记录的获取前导码的实际频率和相位。

39. 发明授权

US5909332A Sampled amplitude read channel employing interpolated timing recovery 失效
标题翻译：采用内插时序恢复的采样幅度读取通道
公开(公告)号：US5909332A
公开(公告)日：1999-06-01
申请号：US834354
申请日：1997-04-16
申请人： Mark S. Spurbeck , Richard T. Behrens
发明人： Mark S. Spurbeck , Richard T. Behrens
IPC分类号： G11B20/10 , G11B20/12 , G11B20/14 , H04L7/02 , H04L7/04 , G11B5/09
CPC分类号： G11B20/10009 , G11B20/10037 , G11B20/10055 , G11B20/1403 , H04L7/0029 , G11B20/1258 , H04L2007/047 , H04L7/04
摘要： A sampled amplitude read channel for reading information stored on a magnetic medium by detecting digital data from a sequence of discrete time interpolated sample values, the interpolated sample values generated by interpolating a sequence of discrete time channel sample values generated by sampling pulses in an analog read signal from a magnetic read head positioned over the magnetic medium. A write VFO generates a write clock for writing digital data to the magnetic medium at a predetermined baud rate for a selected zone, and upon read back, the write VFO generates a sampling clock at a frequency slightly higher than the write frequency. A sampling device samples the analog read signal at the sampling clock rate to generate a sequence of discrete time channel samples that are not synchronized to the baud rate. The channel samples are equalized by a discrete time equalizing filter according to a predetermined partial response (PR4, EPR4, EEPR4, etc.). An interpolating timing recovery circuit, responsive to the equalized channel samples, computes an interpolation interval .tau. and, in response thereto, generates interpolated sample values substantially synchronized to the baud rate. The timing recovery circuit also generates a data clock for clocking a discrete time sequence detector for detecting the digital data from the interpolated sample values.
摘要翻译：一种采样振幅读通道，用于通过从离散时间内插样本值序列中检测数字数据来读取存储在磁介质上的信息，该内插样本值是通过内插由模拟读取中的采样脉冲产生的离散时间通道采样值序列而产生的来自位于磁介质上的磁读头的信号。写入VFO产生写入时钟，用于以预定的波特率为所选区域将数字数据写入磁介质，并且在读回时，写入VFO以略高于写入频率的频率产生采样时钟。采样设备以采样时钟速率对模拟读取信号进行采样，以产生不与波特率同步的离散时间通道采样序列。信道样本根据预定的部分响应（PR4，EPR4，EEPR4等）由离散时间均衡滤波器进行均衡。内插定时恢复电路响应于均衡信道采样，计算内插间隔τ，并且响应于此产生基本上与波特率同步的内插采样值。定时恢复电路还产生用于对离散时间序列检测器进行计时的数据时钟，用于从内插样本值检测数字数据。

40. 发明授权

US5844738A Synchronous read channel employing a sequence detector with programmable detector levels 失效
标题翻译：采用具有可编程检测器电平的序列检测器的同步读通道
公开(公告)号：US5844738A
公开(公告)日：1998-12-01
申请号：US821175
申请日：1997-03-19
申请人： Richard T. Behrens , Kent D. Anderson , Alan J. Armstrong , Trent Dudley , Bill R. Foland , Neal Glover , Larry D. King
发明人： Richard T. Behrens , Kent D. Anderson , Alan J. Armstrong , Trent Dudley , Bill R. Foland , Neal Glover , Larry D. King
IPC分类号： G11B5/012 , G11B5/09 , G11B20/10 , G11B20/12 , G11B20/14 , G11B20/18 , G11B27/30 , H03M13/31
CPC分类号： G11B20/10055 , G11B20/10 , G11B20/10009 , G11B20/1403 , G11B20/1426 , G11B20/18 , G11B27/3027 , G11B5/012 , G11B5/09 , H03M13/31 , G11B20/1258 , G11B2020/1476
摘要： A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a trellis type sequence detector matched to the partial response. The trellis sequence detector comprises programmable detector levels which allows for maximum flexibility in matching the sequence detector to the partial response.
摘要翻译：公开了一种同步读通道，其从位于磁盘介质上的磁读头读取模拟读信号，根据所需的部分响应对采样值进行滤波，从滤波后的采样值中提取定时信息，并检测估计数据序列从使用与部分响应匹配的格子型序列检测器的滤波样本值。网格序列检测器包括可编程检测器级别，其允许在将序列检测器与部分响应匹配时具有最大的灵活性。

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