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1. 发明申请

US20100309470A1 ALIGNMENT MARK ARRANGEMENT AND ALIGNMENT MARK STRUCTURE 有权
标题翻译：对齐标记布置和对齐标记结构
公开(公告)号：US20100309470A1
公开(公告)日：2010-12-09
申请号：US12478778
申请日：2009-06-05
申请人： An-Hsiung Liu , Chun-Yen Huang , Ming-Hung Hsieh
发明人： An-Hsiung Liu , Chun-Yen Huang , Ming-Hung Hsieh
IPC分类号： G01B11/26 , H01L23/544
CPC分类号： G03F9/7084 , G03F9/7076
摘要： An alignment mark arrangement includes: a first alignment pattern comprising a plurality of parallel first stripes on a substrate, wherein each of the first stripes includes a first dimension; and a second alignment pattern positioned directly above and overlapping with the first alignment pattern, the second alignment pattern including a plurality of parallel second stripes, wherein each of the second stripes of the second alignment pattern has a second dimension that is larger than the first dimension of each of the first stripes of the first alignment pattern.
摘要翻译：对准标记布置包括：第一对准图案，其包括在基板上的多个平行的第一条纹，其中每个第一条纹包括第一尺寸; 以及第二对准图案，其位于所述第一对准图案的正上方并与之重叠，所述第二对准图案包括多个平行的第二条纹，其中所述第二对准图案中的每个所述第二条纹具有大于所述第一尺寸的第二尺寸的第一对准图案的每个第一条纹。

2. 发明授权

US08164753B2 Alignment mark arrangement and alignment mark structure 有权
标题翻译：对齐标记布置和对准标记结构
公开(公告)号：US08164753B2
公开(公告)日：2012-04-24
申请号：US12478778
申请日：2009-06-05
申请人： An-Hsiung Liu , Chun-Yen Huang , Ming-Hung Hsieh
发明人： An-Hsiung Liu , Chun-Yen Huang , Ming-Hung Hsieh
IPC分类号： G01B11/00
CPC分类号： G03F9/7084 , G03F9/7076
摘要： An alignment mark arrangement includes: a first alignment pattern comprising a plurality of parallel first stripes on a substrate, wherein each of the first stripes includes a first dimension; and a second alignment pattern positioned directly above and overlapping with the first alignment pattern, the second alignment pattern including a plurality of parallel second stripes, wherein each of the second stripes of the second alignment pattern has a second dimension that is larger than the first dimension of each of the first stripes of the first alignment pattern.
摘要翻译：对准标记布置包括：第一对准图案，其包括在基板上的多个平行的第一条纹，其中每个第一条纹包括第一尺寸; 以及第二对准图案，其位于所述第一对准图案的正上方并与之重叠，所述第二对准图案包括多个平行的第二条纹，其中所述第二对准图案中的每个所述第二条纹具有大于所述第一尺寸的第二尺寸的第一对准图案的每个第一条纹。

3. 发明授权

US08174673B2 Method for wafer alignment 有权
标题翻译：晶圆对准方法
公开(公告)号：US08174673B2
公开(公告)日：2012-05-08
申请号：US12406951
申请日：2009-03-18
申请人： An-Hsiung Liu
发明人： An-Hsiung Liu
IPC分类号： G03B27/42
CPC分类号： G03B27/32
摘要： A method for wafer alignment includes the following steps. First, a wafer including a first material layer and a second material layer on the top of the first material layer is provided, wherein the first material layer includes a first alignment mark. Then, the wafer is aligned in an exposure tool. After that, the second material layer is patterned to form a second alignment mark. Finally, an offset distance between the first alignment mark and the second alignment mark is measured in the exposure tool.
摘要翻译：晶片对准的方法包括以下步骤。首先，提供在第一材料层的顶部包括第一材料层和第二材料层的晶片，其中第一材料层包括第一对准标记。然后，晶片在曝光工具中对准。之后，将第二材料层图案化以形成第二对准标记。最后，在曝光工具中测量第一对准标记和第二对准标记之间的偏移距离。

4. 发明申请

US20060234440A1 ALIGNMENT MARK AND ALIGNMENT METHOD FOR THE FABRICATION OF TRENCH-CAPACITOR DRAM DEVICES 有权
标题翻译：用于制造TRENCH-CAPACITOR DRAM器件的对准标记和对准方法
公开(公告)号：US20060234440A1
公开(公告)日：2006-10-19
申请号：US11160683
申请日：2005-07-05
申请人： Yuan-Hsun WU , An-Hsiung Liu , Chiang-Lin Shih , Pei-Ing Lee , Hui-Min Mao , Lin-Chin Su
发明人： Yuan-Hsun WU , An-Hsiung Liu , Chiang-Lin Shih , Pei-Ing Lee , Hui-Min Mao , Lin-Chin Su
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： G03F9/7084 , G03F7/70633 , G03F9/708 , H01L23/544 , H01L27/1087 , H01L2223/54453 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： A small-size (w
摘要翻译：提出了与“k1工艺”结合的小尺寸（w <0.5微米）对准标记，其特别适用于需要高精度AA-DT对准的沟槽电容器DRAM器件的制造。利用“k1工艺”来蚀刻散布在对准标记沟槽中的多晶硅，并且在AA图案转印之前刷新沟槽轮廓，从而提高晶片对准精度和精度。

5. 发明申请

US20090068813A1 METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20090068813A1
公开(公告)日：2009-03-12
申请号：US11964516
申请日：2007-12-26
申请人： Shian-Jyh Lin , Shun-Fu Chen , Tse-Chuan Kuo , An-Hsiung Liu
发明人： Shian-Jyh Lin , Shun-Fu Chen , Tse-Chuan Kuo , An-Hsiung Liu
IPC分类号： H01L21/02
CPC分类号： H01L29/945 , H01L23/544 , H01L27/1087 , H01L29/66181 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating the semiconductor device comprises providing a semiconductor substrate having a device region and a testkey region. A first trench is formed in the device region and a second trench is formed in the testkey region. A conductive layer with a first etching selectivity is formed in the first and second trenches. A first implantation process is performed in a first direction to form a first doped region with a first impurity and an undoped region in the conductive layer simultaneously and respectively in the device region and in the testkey region. A second implantation process is performed in the second trench to form a second doped region with a second impurity in the conductive layer, wherein the conductive layer in the second trench has a second etching selectivity higher than the first etching selectivity.
摘要翻译：一种制造半导体器件的方法包括提供具有器件区域和测试键区域的半导体衬底。在器件区域中形成第一沟槽，并且在测试键区域中形成第二沟槽。在第一和第二沟槽中形成具有第一蚀刻选择性的导电层。在第一方向上执行第一注入工艺以在导电层中同时并分别在器件区域和测试键区中形成具有第一杂质和未掺杂区的第一掺杂区。在第二沟槽中执行第二注入工艺以在导电层中形成具有第二杂质的第二掺杂区，其中第二沟槽中的导电层具有高于第一蚀刻选择性的第二蚀刻选择性。

6. 发明申请

US20070190736A1 OVERLAY ALIGNMENT MARK AND ALIGNMENT METHOD FOR THE FABRICATION OF TRENCH-CAPACITOR DRAM DEVICES 有权
标题翻译：覆盖电容器DRAM器件的覆盖对准标记和对准方法
公开(公告)号：US20070190736A1
公开(公告)日：2007-08-16
申请号：US11616849
申请日：2006-12-27
申请人： An-Hsiung Liu , Chiang-Lin Shih , Wen-Bin Wu , Hui-Min Mao , Lin-Chin Su , Pei-Ing Lee
发明人： An-Hsiung Liu , Chiang-Lin Shih , Wen-Bin Wu , Hui-Min Mao , Lin-Chin Su , Pei-Ing Lee
IPC分类号： H01L21/20
CPC分类号： H01L29/66181 , G03F7/70633 , G03F9/7076 , G03F9/708 , G03F9/7084 , H01L23/544 , H01L27/1087 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A small-size (w
摘要翻译：提出了与“k1工艺”结合的小尺寸（w <0.5微米）对准标记，其特别适用于制造需要高精度AA-DT和GC-DT重叠对准的沟槽电容器DRAM器件。利用“k1工艺”来蚀刻散布在对准标记沟槽中的多晶硅，并刷新沟槽轮廓，从而提高覆盖对准精度和精度。

7. 发明申请

US20100171942A1 METHOD FOR WAFER ALIGNMENT 有权
标题翻译：波形对准方法
公开(公告)号：US20100171942A1
公开(公告)日：2010-07-08
申请号：US12406951
申请日：2009-03-18
申请人： An-Hsiung Liu
发明人： An-Hsiung Liu
IPC分类号： G03B27/32
CPC分类号： G03B27/32
摘要： A method for wafer alignment includes the following steps. First, a wafer including a first material layer and a second material layer on the top of the first material layer is provided, wherein the first material layer includes a first alignment mark. Then, the wafer is aligned in an exposure tool. After that, the second material layer is patterned to form a second alignment mark. Finally, an offset distance between the first alignment mark and the second alignment mark is measured in the exposure tool.
摘要翻译：晶片对准的方法包括以下步骤。首先，提供在第一材料层的顶部包括第一材料层和第二材料层的晶片，其中第一材料层包括第一对准标记。然后，晶片在曝光工具中对准。之后，将第二材料层图案化以形成第二对准标记。最后，在曝光工具中测量第一对准标记和第二对准标记之间的偏移距离。

8. 发明申请

US20080242100A1 SEMICONDUCTOR DEVICE AND FABRICATIONS THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080242100A1
公开(公告)日：2008-10-02
申请号：US11971001
申请日：2008-01-08
申请人： Wei-Tung Yang , An-Hsiung Liu
发明人： Wei-Tung Yang , An-Hsiung Liu
IPC分类号： H01L21/308
CPC分类号： H01L21/32139 , H01L21/76816 , H01L27/10891 , H01L27/10894
摘要： A method for forming a semiconductor device is disclosed. A substrate comprising a structural layer thereon is provided. A hard mask layer is formed on the structural layer. A photoresist layer is formed on the hard mask layer. The photoresist layer is patterned to from a plurality of main photoresist patterns and at least one dummy photoresist pattern between the main photoresist patterns or adjacent to one of the main photoresist patterns, wherein width of the dummy photoresist pattern is less than that of the main photoresist patterns. Two main photoresist patterns are separated with each other by a first opening, and two dummy photoresist patterns are separated with each other by a second opening. Width of the second opening is less than that of the first opening. The hard mask layer is patterned using the patterned photoresist layer as a mask. The structural layer is patterned using the patterned hard mask layer as a mask.
摘要翻译：公开了一种用于形成半导体器件的方法。提供了包括其上的结构层的衬底。在结构层上形成硬掩模层。在硬掩模层上形成光致抗蚀剂层。光致抗蚀剂层从多个主光致抗蚀剂图案和主光致抗蚀剂图案之间的至少一个伪光致抗蚀剂图案图案化，或者与主光致抗蚀剂图案之一相邻，其中，伪光刻胶图案的宽度小于主光致抗蚀剂图案的宽度模式。两个主要的光致抗蚀剂图案通过第一开口彼此分离，并且两个伪光刻胶图案通过第二开口彼此分离。第二开口的宽度小于第一开口的宽度。使用图案化的光致抗蚀剂层作为掩模来对硬掩模层进行图案化。使用图案化的硬掩模层作为掩模来对结构层进行图案化。

9. 发明授权

US08053370B2 Semiconductor device and fabrications thereof 有权
标题翻译：半导体器件及其制造
公开(公告)号：US08053370B2
公开(公告)日：2011-11-08
申请号：US11971001
申请日：2008-01-08
申请人： Wei-Tung Yang , An-Hsiung Liu
发明人： Wei-Tung Yang , An-Hsiung Liu
IPC分类号： H01L21/302
CPC分类号： H01L21/32139 , H01L21/76816 , H01L27/10891 , H01L27/10894
摘要： A method for forming a semiconductor device is disclosed. A substrate comprising a structural layer thereon is provided. A hard mask layer is formed on the structural layer. A photoresist layer is formed on the hard mask layer. The photoresist layer is patterned to from a plurality of main photoresist patterns and at least one dummy photoresist pattern between the main photoresist patterns or adjacent to one of the main photoresist patterns, wherein width of the dummy photoresist pattern is less than that of the main photoresist patterns. Two main photoresist patterns are separated with each other by a first opening, and two dummy photoresist patterns are separated with each other by a second opening. Width of the second opening is less than that of the first opening. The hard mask layer is patterned using the patterned photoresist layer as a mask. The structural layer is patterned using the patterned hard mask layer as a mask.
摘要翻译：公开了一种用于形成半导体器件的方法。提供了包括其上的结构层的衬底。在结构层上形成硬掩模层。在硬掩模层上形成光致抗蚀剂层。光致抗蚀剂层从多个主光致抗蚀剂图案和主光致抗蚀剂图案之间的至少一个伪光致抗蚀剂图案图案化，或者与主光致抗蚀剂图案之一相邻，其中，伪光刻胶图案的宽度小于主光致抗蚀剂图案的宽度模式。两个主要的光致抗蚀剂图案通过第一开口彼此分离，并且两个伪光刻胶图案通过第二开口彼此分离。第二开口的宽度小于第一开口的宽度。使用图案化的光致抗蚀剂层作为掩模来对硬掩模层进行图案化。使用图案化的硬掩模层作为掩模来对结构层进行图案化。

10. 发明授权

US07803701B2 Method for fabricating a semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US07803701B2
公开(公告)日：2010-09-28
申请号：US11964516
申请日：2007-12-26
申请人： Shian-Jyh Lin , Shun-Fu Chen , Tse-Chuan Kuo , An-Hsiung Liu
发明人： Shian-Jyh Lin , Shun-Fu Chen , Tse-Chuan Kuo , An-Hsiung Liu
IPC分类号： H01L21/8242 , H01L21/425
CPC分类号： H01L29/945 , H01L23/544 , H01L27/1087 , H01L29/66181 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating the semiconductor device comprises providing a semiconductor substrate having a device region and a testkey region. A first trench is formed in the device region and a second trench is formed in the testkey region. A conductive layer with a first etching selectivity is formed in the first and second trenches. A first implantation process is performed in a first direction to form a first doped region with a first impurity and an undoped region in the conductive layer simultaneously and respectively in the device region and in the testkey region. A second implantation process is performed in the second trench to form a second doped region with a second impurity in the conductive layer, wherein the conductive layer in the second trench has a second etching selectivity higher than the first etching selectivity.
摘要翻译：一种制造半导体器件的方法包括提供具有器件区域和测试键区域的半导体衬底。在器件区域中形成第一沟槽，并且在测试键区域中形成第二沟槽。在第一和第二沟槽中形成具有第一蚀刻选择性的导电层。在第一方向上执行第一注入工艺以在导电层中同时并分别在器件区域和测试键区中形成具有第一杂质和未掺杂区的第一掺杂区。在第二沟槽中执行第二注入工艺以在导电层中形成具有第二杂质的第二掺杂区，其中第二沟槽中的导电层具有高于第一蚀刻选择性的第二蚀刻选择性。

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